Revision c227f099 hw/ppc_prep.c
| b/hw/ppc_prep.c | ||
|---|---|---|
| 112 | 112 |
/* PCI intack register */ |
| 113 | 113 |
/* Read-only register (?) */ |
| 114 | 114 |
static void _PPC_intack_write (void *opaque, |
| 115 |
a_target_phys_addr addr, uint32_t value)
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|
| 115 |
target_phys_addr_t addr, uint32_t value)
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|
| 116 | 116 |
{
|
| 117 | 117 |
#if 0 |
| 118 | 118 |
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
|
| ... | ... | |
| 120 | 120 |
#endif |
| 121 | 121 |
} |
| 122 | 122 |
|
| 123 |
static inline uint32_t _PPC_intack_read(a_target_phys_addr addr)
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| 123 |
static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
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| 124 | 124 |
{
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| 125 | 125 |
uint32_t retval = 0; |
| 126 | 126 |
|
| ... | ... | |
| 134 | 134 |
return retval; |
| 135 | 135 |
} |
| 136 | 136 |
|
| 137 |
static uint32_t PPC_intack_readb (void *opaque, a_target_phys_addr addr)
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static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
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| 138 | 138 |
{
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| 139 | 139 |
return _PPC_intack_read(addr); |
| 140 | 140 |
} |
| 141 | 141 |
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static uint32_t PPC_intack_readw (void *opaque, a_target_phys_addr addr)
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static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
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| 143 | 143 |
{
|
| 144 | 144 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 145 | 145 |
return bswap16(_PPC_intack_read(addr)); |
| ... | ... | |
| 148 | 148 |
#endif |
| 149 | 149 |
} |
| 150 | 150 |
|
| 151 |
static uint32_t PPC_intack_readl (void *opaque, a_target_phys_addr addr)
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static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
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| 152 | 152 |
{
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| 153 | 153 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 154 | 154 |
return bswap32(_PPC_intack_read(addr)); |
| ... | ... | |
| 197 | 197 |
} XCSR; |
| 198 | 198 |
|
| 199 | 199 |
static void PPC_XCSR_writeb (void *opaque, |
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a_target_phys_addr addr, uint32_t value)
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target_phys_addr_t addr, uint32_t value)
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| 201 | 201 |
{
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| 202 | 202 |
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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| 203 | 203 |
value); |
| 204 | 204 |
} |
| 205 | 205 |
|
| 206 | 206 |
static void PPC_XCSR_writew (void *opaque, |
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a_target_phys_addr addr, uint32_t value)
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target_phys_addr_t addr, uint32_t value)
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| 208 | 208 |
{
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| 209 | 209 |
#ifdef TARGET_WORDS_BIGENDIAN |
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value = bswap16(value); |
| ... | ... | |
| 214 | 214 |
} |
| 215 | 215 |
|
| 216 | 216 |
static void PPC_XCSR_writel (void *opaque, |
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a_target_phys_addr addr, uint32_t value)
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef TARGET_WORDS_BIGENDIAN |
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value = bswap32(value); |
| ... | ... | |
| 223 | 223 |
value); |
| 224 | 224 |
} |
| 225 | 225 |
|
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static uint32_t PPC_XCSR_readb (void *opaque, a_target_phys_addr addr)
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static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
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| 227 | 227 |
{
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uint32_t retval = 0; |
| 229 | 229 |
|
| ... | ... | |
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return retval; |
| 234 | 234 |
} |
| 235 | 235 |
|
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static uint32_t PPC_XCSR_readw (void *opaque, a_target_phys_addr addr)
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static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t retval = 0; |
| 239 | 239 |
|
| ... | ... | |
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return retval; |
| 247 | 247 |
} |
| 248 | 248 |
|
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static uint32_t PPC_XCSR_readl (void *opaque, a_target_phys_addr addr)
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static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
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| 250 | 250 |
{
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| 251 | 251 |
uint32_t retval = 0; |
| 252 | 252 |
|
| ... | ... | |
| 273 | 273 |
#endif |
| 274 | 274 |
|
| 275 | 275 |
/* Fake super-io ports for PREP platform (Intel 82378ZB) */ |
| 276 |
typedef struct sysctrl {
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typedef struct sysctrl_t {
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| 277 | 277 |
qemu_irq reset_irq; |
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a_m48t59 *nvram;
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m48t59_t *nvram;
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| 279 | 279 |
uint8_t state; |
| 280 | 280 |
uint8_t syscontrol; |
| 281 | 281 |
uint8_t fake_io[2]; |
| 282 | 282 |
int contiguous_map; |
| 283 | 283 |
int endian; |
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} a_sysctrl;
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} sysctrl_t;
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| 285 | 285 |
|
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enum {
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| 287 | 287 |
STATE_HARDFILE = 0x01, |
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}; |
| 289 | 289 |
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static a_sysctrl *sysctrl;
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static sysctrl_t *sysctrl;
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static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
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{
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a_sysctrl *sysctrl = opaque;
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sysctrl_t *sysctrl = opaque;
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PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
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val); |
| ... | ... | |
| 300 | 300 |
|
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static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
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{
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a_sysctrl *sysctrl = opaque;
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sysctrl_t *sysctrl = opaque;
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PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
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sysctrl->fake_io[addr - 0x0398]); |
| ... | ... | |
| 309 | 309 |
|
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static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
| 311 | 311 |
{
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a_sysctrl *sysctrl = opaque;
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sysctrl_t *sysctrl = opaque;
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| 313 | 313 |
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PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
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addr - PPC_IO_BASE, val); |
| ... | ... | |
| 376 | 376 |
|
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static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
| 378 | 378 |
{
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a_sysctrl *sysctrl = opaque;
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sysctrl_t *sysctrl = opaque;
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| 380 | 380 |
uint32_t retval = 0xFF; |
| 381 | 381 |
|
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switch (addr) {
|
| ... | ... | |
| 440 | 440 |
return retval; |
| 441 | 441 |
} |
| 442 | 442 |
|
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static inline a_target_phys_addr prep_IO_address(a_sysctrl *sysctrl,
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a_target_phys_addr addr)
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static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
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target_phys_addr_t addr)
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{
|
| 446 | 446 |
if (sysctrl->contiguous_map == 0) {
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| 447 | 447 |
/* 64 KB contiguous space for IOs */ |
| ... | ... | |
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return addr; |
| 455 | 455 |
} |
| 456 | 456 |
|
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static void PPC_prep_io_writeb (void *opaque, a_target_phys_addr addr,
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static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
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| 458 | 458 |
uint32_t value) |
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{
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a_sysctrl *sysctrl = opaque;
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sysctrl_t *sysctrl = opaque;
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| 461 | 461 |
|
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addr = prep_IO_address(sysctrl, addr); |
| 463 | 463 |
cpu_outb(addr, value); |
| 464 | 464 |
} |
| 465 | 465 |
|
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static uint32_t PPC_prep_io_readb (void *opaque, a_target_phys_addr addr)
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static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
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| 467 | 467 |
{
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a_sysctrl *sysctrl = opaque;
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sysctrl_t *sysctrl = opaque;
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| 469 | 469 |
uint32_t ret; |
| 470 | 470 |
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addr = prep_IO_address(sysctrl, addr); |
| ... | ... | |
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return ret; |
| 475 | 475 |
} |
| 476 | 476 |
|
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static void PPC_prep_io_writew (void *opaque, a_target_phys_addr addr,
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static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
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| 478 | 478 |
uint32_t value) |
| 479 | 479 |
{
|
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a_sysctrl *sysctrl = opaque;
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sysctrl_t *sysctrl = opaque;
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| 481 | 481 |
|
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addr = prep_IO_address(sysctrl, addr); |
| 483 | 483 |
#ifdef TARGET_WORDS_BIGENDIAN |
| ... | ... | |
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cpu_outw(addr, value); |
| 488 | 488 |
} |
| 489 | 489 |
|
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static uint32_t PPC_prep_io_readw (void *opaque, a_target_phys_addr addr)
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static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
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| 491 | 491 |
{
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a_sysctrl *sysctrl = opaque;
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sysctrl_t *sysctrl = opaque;
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| 493 | 493 |
uint32_t ret; |
| 494 | 494 |
|
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addr = prep_IO_address(sysctrl, addr); |
| ... | ... | |
| 502 | 502 |
return ret; |
| 503 | 503 |
} |
| 504 | 504 |
|
| 505 |
static void PPC_prep_io_writel (void *opaque, a_target_phys_addr addr,
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static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
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| 506 | 506 |
uint32_t value) |
| 507 | 507 |
{
|
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a_sysctrl *sysctrl = opaque;
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sysctrl_t *sysctrl = opaque;
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| 509 | 509 |
|
| 510 | 510 |
addr = prep_IO_address(sysctrl, addr); |
| 511 | 511 |
#ifdef TARGET_WORDS_BIGENDIAN |
| ... | ... | |
| 515 | 515 |
cpu_outl(addr, value); |
| 516 | 516 |
} |
| 517 | 517 |
|
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static uint32_t PPC_prep_io_readl (void *opaque, a_target_phys_addr addr)
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static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
|
|
| 519 | 519 |
{
|
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a_sysctrl *sysctrl = opaque;
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sysctrl_t *sysctrl = opaque;
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| 521 | 521 |
uint32_t ret; |
| 522 | 522 |
|
| 523 | 523 |
addr = prep_IO_address(sysctrl, addr); |
| ... | ... | |
| 545 | 545 |
#define NVRAM_SIZE 0x2000 |
| 546 | 546 |
|
| 547 | 547 |
/* PowerPC PREP hardware initialisation */ |
| 548 |
static void ppc_prep_init (a_ram_addr ram_size,
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static void ppc_prep_init (ram_addr_t ram_size,
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| 549 | 549 |
const char *boot_device, |
| 550 | 550 |
const char *kernel_filename, |
| 551 | 551 |
const char *kernel_cmdline, |
| ... | ... | |
| 554 | 554 |
{
|
| 555 | 555 |
CPUState *env = NULL, *envs[MAX_CPUS]; |
| 556 | 556 |
char *filename; |
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a_nvram nvram;
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a_m48t59 *m48t59;
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nvram_t nvram;
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m48t59_t *m48t59;
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| 559 | 559 |
int PPC_io_memory; |
| 560 | 560 |
int linux_boot, i, nb_nics1, bios_size; |
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a_ram_addr ram_offset, bios_offset;
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ram_addr_t ram_offset, bios_offset;
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| 562 | 562 |
uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
| 563 | 563 |
PCIBus *pci_bus; |
| 564 | 564 |
qemu_irq *i8259; |
| ... | ... | |
| 567 | 567 |
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
| 568 | 568 |
BlockDriverState *fd[MAX_FD]; |
| 569 | 569 |
|
| 570 |
sysctrl = qemu_mallocz(sizeof(a_sysctrl));
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sysctrl = qemu_mallocz(sizeof(sysctrl_t));
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| 571 | 571 |
|
| 572 | 572 |
linux_boot = (kernel_filename != NULL); |
| 573 | 573 |
|
| ... | ... | |
| 606 | 606 |
bios_size = -1; |
| 607 | 607 |
} |
| 608 | 608 |
if (bios_size > 0 && bios_size <= BIOS_SIZE) {
|
| 609 |
a_target_phys_addr bios_addr;
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target_phys_addr_t bios_addr;
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| 610 | 610 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
| 611 | 611 |
bios_addr = (uint32_t)(-bios_size); |
| 612 | 612 |
cpu_register_physical_memory(bios_addr, bios_size, |
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