Revision c227f099 hw/pxa.h
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# define PXA2XX_INTERNAL_SIZE 0x40000 |
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/* pxa2xx_pic.c */ |
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qemu_irq *pxa2xx_pic_init(a_target_phys_addr base, CPUState *env);
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qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
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/* pxa2xx_timer.c */ |
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void pxa25x_timer_init(a_target_phys_addr base, qemu_irq *irqs);
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void pxa27x_timer_init(a_target_phys_addr base, qemu_irq *irqs, qemu_irq irq4);
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void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
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void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
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/* pxa2xx_gpio.c */ |
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typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo; |
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PXA2xxGPIOInfo *pxa2xx_gpio_init(a_target_phys_addr base,
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PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
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CPUState *env, qemu_irq *pic, int lines); |
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qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s); |
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void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s, |
| ... | ... | |
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/* pxa2xx_dma.c */ |
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typedef struct PXA2xxDMAState PXA2xxDMAState; |
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PXA2xxDMAState *pxa255_dma_init(a_target_phys_addr base,
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PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
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qemu_irq irq); |
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PXA2xxDMAState *pxa27x_dma_init(a_target_phys_addr base,
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PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
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qemu_irq irq); |
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void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on); |
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/* pxa2xx_lcd.c */ |
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typedef struct PXA2xxLCDState PXA2xxLCDState; |
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PXA2xxLCDState *pxa2xx_lcdc_init(a_target_phys_addr base,
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PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
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qemu_irq irq); |
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void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler); |
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void pxa2xx_lcdc_oritentation(void *opaque, int angle); |
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/* pxa2xx_mmci.c */ |
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typedef struct PXA2xxMMCIState PXA2xxMMCIState; |
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PXA2xxMMCIState *pxa2xx_mmci_init(a_target_phys_addr base,
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PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
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BlockDriverState *bd, qemu_irq irq, void *dma); |
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void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, |
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qemu_irq coverswitch); |
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/* pxa2xx_pcmcia.c */ |
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typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState; |
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PXA2xxPCMCIAState *pxa2xx_pcmcia_init(a_target_phys_addr base);
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PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
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int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card); |
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int pxa2xx_pcmcia_dettach(void *opaque); |
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void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); |
| ... | ... | |
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int row; |
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}; |
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typedef struct PXA2xxKeyPadState PXA2xxKeyPadState; |
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PXA2xxKeyPadState *pxa27x_keypad_init(a_target_phys_addr base,
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PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
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qemu_irq irq); |
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void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map, |
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int size); |
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/* pxa2xx.c */ |
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typedef struct PXA2xxI2CState PXA2xxI2CState; |
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PXA2xxI2CState *pxa2xx_i2c_init(a_target_phys_addr base,
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PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
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qemu_irq irq, uint32_t page_size); |
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i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s); |
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| ... | ... | |
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PXA2xxKeyPadState *kp; |
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/* Power management */ |
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a_target_phys_addr pm_base;
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target_phys_addr_t pm_base;
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uint32_t pm_regs[0x40]; |
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/* Clock management */ |
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a_target_phys_addr cm_base;
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target_phys_addr_t cm_base;
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uint32_t cm_regs[4]; |
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uint32_t clkcfg; |
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/* Memory management */ |
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a_target_phys_addr mm_base;
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target_phys_addr_t mm_base;
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uint32_t mm_regs[0x1a]; |
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/* Performance monitoring */ |
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uint32_t pmnc; |
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/* Real-Time clock */ |
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a_target_phys_addr rtc_base;
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target_phys_addr_t rtc_base;
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uint32_t rttr; |
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uint32_t rtsr; |
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uint32_t rtar; |
| ... | ... | |
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PXA2xxState *pxa255_init(unsigned int sdram_size); |
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/* usb-ohci.c */ |
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void usb_ohci_init_pxa(a_target_phys_addr base, int num_ports, int devfn,
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void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
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qemu_irq irq); |
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#endif /* PXA_H */ |
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