Revision c227f099 hw/pxa2xx.c
b/hw/pxa2xx.c | ||
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17 | 17 |
#include "qemu-char.h" |
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|
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static struct { |
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a_target_phys_addr io_base;
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|
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target_phys_addr_t io_base;
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21 | 21 |
int irqn; |
22 | 22 |
} pxa255_serial[] = { |
23 | 23 |
{ 0x40100000, PXA2XX_PIC_FFUART }, |
... | ... | |
33 | 33 |
}; |
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35 | 35 |
typedef struct PXASSPDef { |
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a_target_phys_addr io_base;
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target_phys_addr_t io_base;
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37 | 37 |
int irqn; |
38 | 38 |
} PXASSPDef; |
39 | 39 |
|
... | ... | |
88 | 88 |
#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ |
89 | 89 |
#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ |
90 | 90 |
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static uint32_t pxa2xx_pm_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
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92 | 92 |
{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
94 | 94 |
|
... | ... | |
106 | 106 |
return 0; |
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} |
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static void pxa2xx_pm_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
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110 | 110 |
uint32_t value) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
... | ... | |
171 | 171 |
#define OSCC 0x08 /* Oscillator Configuration register */ |
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#define CCSR 0x0c /* Core Clock Status register */ |
173 | 173 |
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static uint32_t pxa2xx_cm_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
177 | 177 |
|
... | ... | |
191 | 191 |
return 0; |
192 | 192 |
} |
193 | 193 |
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static void pxa2xx_cm_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
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195 | 195 |
uint32_t value) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
... | ... | |
481 | 481 |
#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ |
482 | 482 |
#define SA1110 0x64 /* SA-1110 Memory Compatibility register */ |
483 | 483 |
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static uint32_t pxa2xx_mm_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
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485 | 485 |
{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
487 | 487 |
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... | ... | |
497 | 497 |
return 0; |
498 | 498 |
} |
499 | 499 |
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static void pxa2xx_mm_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
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501 | 501 |
uint32_t value) |
502 | 502 |
{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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656 | 656 |
pxa2xx_ssp_int_update(s); |
657 | 657 |
} |
658 | 658 |
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static uint32_t pxa2xx_ssp_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
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660 | 660 |
{ |
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PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
662 | 662 |
uint32_t retval; |
... | ... | |
701 | 701 |
return 0; |
702 | 702 |
} |
703 | 703 |
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static void pxa2xx_ssp_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
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705 | 705 |
uint32_t value) |
706 | 706 |
{ |
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PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
... | ... | |
1008 | 1008 |
pxa2xx_rtc_int_update(s); |
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} |
1010 | 1010 |
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static uint32_t pxa2xx_rtc_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
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1012 | 1012 |
{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
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1053 | 1053 |
return 0; |
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} |
1055 | 1055 |
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static void pxa2xx_rtc_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{ |
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PXA2xxState *s = (PXA2xxState *) opaque; |
... | ... | |
1263 | 1263 |
PXA2xxI2CSlaveState *slave; |
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i2c_bus *bus; |
1265 | 1265 |
qemu_irq irq; |
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a_target_phys_addr offset;
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target_phys_addr_t offset;
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1267 | 1267 |
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1268 | 1268 |
uint16_t control; |
1269 | 1269 |
uint16_t status; |
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1343 | 1343 |
return 1; |
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} |
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static uint32_t pxa2xx_i2c_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
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{ |
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PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
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|
... | ... | |
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return 0; |
1371 | 1371 |
} |
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static void pxa2xx_i2c_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
1375 | 1375 |
{ |
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PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
... | ... | |
1495 | 1495 |
.send = pxa2xx_i2c_tx |
1496 | 1496 |
}; |
1497 | 1497 |
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PXA2xxI2CState *pxa2xx_i2c_init(a_target_phys_addr base,
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PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
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1499 | 1499 |
qemu_irq irq, uint32_t region_size) |
1500 | 1500 |
{ |
1501 | 1501 |
int iomemtype; |
... | ... | |
1582 | 1582 |
#define SADIV 0x60 /* Serial Audio Clock Divider register */ |
1583 | 1583 |
#define SADR 0x80 /* Serial Audio Data register */ |
1584 | 1584 |
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static uint32_t pxa2xx_i2s_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
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1586 | 1586 |
{ |
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PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
1588 | 1588 |
|
... | ... | |
1613 | 1613 |
return 0; |
1614 | 1614 |
} |
1615 | 1615 |
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static void pxa2xx_i2s_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
1618 | 1618 |
{ |
1619 | 1619 |
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
... | ... | |
1736 | 1736 |
pxa2xx_i2s_update(s); |
1737 | 1737 |
} |
1738 | 1738 |
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static PXA2xxI2SState *pxa2xx_i2s_init(a_target_phys_addr base,
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static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
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1740 | 1740 |
qemu_irq irq, PXA2xxDMAState *dma) |
1741 | 1741 |
{ |
1742 | 1742 |
int iomemtype; |
... | ... | |
1830 | 1830 |
#define ICSR1 0x18 /* FICP Status register 1 */ |
1831 | 1831 |
#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ |
1832 | 1832 |
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static uint32_t pxa2xx_fir_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
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1834 | 1834 |
{ |
1835 | 1835 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
1836 | 1836 |
uint8_t ret; |
... | ... | |
1867 | 1867 |
return 0; |
1868 | 1868 |
} |
1869 | 1869 |
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static void pxa2xx_fir_write(void *opaque, a_target_phys_addr addr,
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1870 |
static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
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1871 | 1871 |
uint32_t value) |
1872 | 1872 |
{ |
1873 | 1873 |
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
... | ... | |
1994 | 1994 |
return 0; |
1995 | 1995 |
} |
1996 | 1996 |
|
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static PXA2xxFIrState *pxa2xx_fir_init(a_target_phys_addr base,
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static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
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1998 | 1998 |
qemu_irq irq, PXA2xxDMAState *dma, |
1999 | 1999 |
CharDriverState *chr) |
2000 | 2000 |
{ |
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