Revision c227f099 hw/pxa2xx.c
| b/hw/pxa2xx.c | ||
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#include "qemu-char.h" |
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static struct {
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a_target_phys_addr io_base;
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target_phys_addr_t io_base;
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int irqn; |
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} pxa255_serial[] = {
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{ 0x40100000, PXA2XX_PIC_FFUART },
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| ... | ... | |
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}; |
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typedef struct PXASSPDef {
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a_target_phys_addr io_base;
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target_phys_addr_t io_base;
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int irqn; |
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} PXASSPDef; |
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|
| ... | ... | |
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#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ |
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#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ |
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static uint32_t pxa2xx_pm_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
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{
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PXA2xxState *s = (PXA2xxState *) opaque; |
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|
| ... | ... | |
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return 0; |
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} |
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static void pxa2xx_pm_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{
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PXA2xxState *s = (PXA2xxState *) opaque; |
| ... | ... | |
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#define OSCC 0x08 /* Oscillator Configuration register */ |
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#define CCSR 0x0c /* Core Clock Status register */ |
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static uint32_t pxa2xx_cm_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
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{
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PXA2xxState *s = (PXA2xxState *) opaque; |
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|
| ... | ... | |
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return 0; |
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} |
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static void pxa2xx_cm_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{
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PXA2xxState *s = (PXA2xxState *) opaque; |
| ... | ... | |
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#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ |
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#define SA1110 0x64 /* SA-1110 Memory Compatibility register */ |
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static uint32_t pxa2xx_mm_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
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{
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PXA2xxState *s = (PXA2xxState *) opaque; |
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|
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return 0; |
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} |
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static void pxa2xx_mm_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{
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PXA2xxState *s = (PXA2xxState *) opaque; |
| ... | ... | |
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pxa2xx_ssp_int_update(s); |
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} |
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static uint32_t pxa2xx_ssp_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
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{
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PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
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uint32_t retval; |
| ... | ... | |
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return 0; |
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} |
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static void pxa2xx_ssp_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{
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PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
| ... | ... | |
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pxa2xx_rtc_int_update(s); |
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} |
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static uint32_t pxa2xx_rtc_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
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{
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PXA2xxState *s = (PXA2xxState *) opaque; |
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|
| ... | ... | |
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return 0; |
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} |
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static void pxa2xx_rtc_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{
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PXA2xxState *s = (PXA2xxState *) opaque; |
| ... | ... | |
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PXA2xxI2CSlaveState *slave; |
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i2c_bus *bus; |
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qemu_irq irq; |
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a_target_phys_addr offset;
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target_phys_addr_t offset;
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uint16_t control; |
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uint16_t status; |
| ... | ... | |
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return 1; |
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} |
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static uint32_t pxa2xx_i2c_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
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{
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PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
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|
| ... | ... | |
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return 0; |
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} |
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static void pxa2xx_i2c_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{
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PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
| ... | ... | |
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.send = pxa2xx_i2c_tx |
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}; |
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PXA2xxI2CState *pxa2xx_i2c_init(a_target_phys_addr base,
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PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
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qemu_irq irq, uint32_t region_size) |
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{
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int iomemtype; |
| ... | ... | |
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#define SADIV 0x60 /* Serial Audio Clock Divider register */ |
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#define SADR 0x80 /* Serial Audio Data register */ |
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static uint32_t pxa2xx_i2s_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
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{
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PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
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|
| ... | ... | |
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return 0; |
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} |
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static void pxa2xx_i2s_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{
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PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
| ... | ... | |
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pxa2xx_i2s_update(s); |
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} |
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static PXA2xxI2SState *pxa2xx_i2s_init(a_target_phys_addr base,
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static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
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qemu_irq irq, PXA2xxDMAState *dma) |
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{
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int iomemtype; |
| ... | ... | |
| 1830 | 1830 |
#define ICSR1 0x18 /* FICP Status register 1 */ |
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#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ |
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static uint32_t pxa2xx_fir_read(void *opaque, a_target_phys_addr addr)
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static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
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{
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PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
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uint8_t ret; |
| ... | ... | |
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return 0; |
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} |
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static void pxa2xx_fir_write(void *opaque, a_target_phys_addr addr,
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static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
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uint32_t value) |
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{
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PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
| ... | ... | |
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return 0; |
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} |
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static PXA2xxFIrState *pxa2xx_fir_init(a_target_phys_addr base,
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static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
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qemu_irq irq, PXA2xxDMAState *dma, |
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CharDriverState *chr) |
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{
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