Revision c227f099 hw/pxa2xx_mmci.c

b/hw/pxa2xx_mmci.c
211 211
    pxa2xx_mmci_fifo_update(s);
212 212
}
213 213

  
214
static uint32_t pxa2xx_mmci_read(void *opaque, a_target_phys_addr offset)
214
static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
215 215
{
216 216
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
217 217
    uint32_t ret;
......
273 273
}
274 274

  
275 275
static void pxa2xx_mmci_write(void *opaque,
276
                a_target_phys_addr offset, uint32_t value)
276
                target_phys_addr_t offset, uint32_t value)
277 277
{
278 278
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
279 279

  
......
382 382
    }
383 383
}
384 384

  
385
static uint32_t pxa2xx_mmci_readb(void *opaque, a_target_phys_addr offset)
385
static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
386 386
{
387 387
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
388 388
    s->ac_width = 1;
389 389
    return pxa2xx_mmci_read(opaque, offset);
390 390
}
391 391

  
392
static uint32_t pxa2xx_mmci_readh(void *opaque, a_target_phys_addr offset)
392
static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
393 393
{
394 394
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
395 395
    s->ac_width = 2;
396 396
    return pxa2xx_mmci_read(opaque, offset);
397 397
}
398 398

  
399
static uint32_t pxa2xx_mmci_readw(void *opaque, a_target_phys_addr offset)
399
static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
400 400
{
401 401
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
402 402
    s->ac_width = 4;
......
410 410
};
411 411

  
412 412
static void pxa2xx_mmci_writeb(void *opaque,
413
                a_target_phys_addr offset, uint32_t value)
413
                target_phys_addr_t offset, uint32_t value)
414 414
{
415 415
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
416 416
    s->ac_width = 1;
......
418 418
}
419 419

  
420 420
static void pxa2xx_mmci_writeh(void *opaque,
421
                a_target_phys_addr offset, uint32_t value)
421
                target_phys_addr_t offset, uint32_t value)
422 422
{
423 423
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
424 424
    s->ac_width = 2;
......
426 426
}
427 427

  
428 428
static void pxa2xx_mmci_writew(void *opaque,
429
                a_target_phys_addr offset, uint32_t value)
429
                target_phys_addr_t offset, uint32_t value)
430 430
{
431 431
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
432 432
    s->ac_width = 4;
......
517 517
    return 0;
518 518
}
519 519

  
520
PXA2xxMMCIState *pxa2xx_mmci_init(a_target_phys_addr base,
520
PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
521 521
                BlockDriverState *bd, qemu_irq irq, void *dma)
522 522
{
523 523
    int iomemtype;

Also available in: Unified diff