Revision c227f099 hw/pxa2xx_pic.c
| b/hw/pxa2xx_pic.c | ||
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| 113 | 113 |
return ichp; |
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} |
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static uint32_t pxa2xx_pic_mem_read(void *opaque, a_target_phys_addr offset)
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static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset)
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{
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PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
| 119 | 119 |
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| ... | ... | |
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} |
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} |
| 154 | 154 |
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static void pxa2xx_pic_mem_write(void *opaque, a_target_phys_addr offset,
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static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
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uint32_t value) |
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{
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PXA2xxPICState *s = (PXA2xxPICState *) opaque; |
| ... | ... | |
| 204 | 204 |
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static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm) |
| 206 | 206 |
{
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a_target_phys_addr offset;
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target_phys_addr_t offset;
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if (pxa2xx_cp_reg_map[reg] == -1) {
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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| ... | ... | |
| 218 | 218 |
static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm, |
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uint32_t value) |
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{
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a_target_phys_addr offset;
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target_phys_addr_t offset;
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if (pxa2xx_cp_reg_map[reg] == -1) {
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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| ... | ... | |
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return 0; |
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} |
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qemu_irq *pxa2xx_pic_init(a_target_phys_addr base, CPUState *env)
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qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
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{
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| 281 | 281 |
PXA2xxPICState *s; |
| 282 | 282 |
int iomemtype; |
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