Revision c227f099 hw/r2d.c
| b/hw/r2d.c | ||
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| 73 | 73 |
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| 74 | 74 |
/* output pin */ |
| 75 | 75 |
qemu_irq irl; |
| 76 |
} a_r2d_fpga;
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| 76 |
} r2d_fpga_t;
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| 77 | 77 |
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enum r2d_fpga_irq {
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PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, |
| ... | ... | |
| 97 | 97 |
[TP] = { 12, 1<<15 },
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| 98 | 98 |
}; |
| 99 | 99 |
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static void update_irl(a_r2d_fpga *fpga)
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static void update_irl(r2d_fpga_t *fpga)
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{
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int i, irl = 15; |
| 103 | 103 |
for (i = 0; i < NR_IRQS; i++) |
| ... | ... | |
| 109 | 109 |
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| 110 | 110 |
static void r2d_fpga_irq_set(void *opaque, int n, int level) |
| 111 | 111 |
{
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a_r2d_fpga *fpga = opaque;
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r2d_fpga_t *fpga = opaque;
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if (level) |
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fpga->irlmon |= irqtab[n].msk; |
| 115 | 115 |
else |
| ... | ... | |
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update_irl(fpga); |
| 118 | 118 |
} |
| 119 | 119 |
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static uint32_t r2d_fpga_read(void *opaque, a_target_phys_addr addr)
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static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
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{
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a_r2d_fpga *s = opaque;
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r2d_fpga_t *s = opaque;
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| 123 | 123 |
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switch (addr) {
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case PA_IRLMSK: |
| ... | ... | |
| 136 | 136 |
} |
| 137 | 137 |
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static void |
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r2d_fpga_write(void *opaque, a_target_phys_addr addr, uint32_t value)
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r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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a_r2d_fpga *s = opaque;
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r2d_fpga_t *s = opaque;
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| 142 | 142 |
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switch (addr) {
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| 144 | 144 |
case PA_IRLMSK: |
| ... | ... | |
| 169 | 169 |
NULL, |
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}; |
| 171 | 171 |
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static qemu_irq *r2d_fpga_init(a_target_phys_addr base, qemu_irq irl)
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static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
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{
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int iomemtype; |
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a_r2d_fpga *s;
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r2d_fpga_t *s;
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| 176 | 176 |
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s = qemu_mallocz(sizeof(a_r2d_fpga));
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s = qemu_mallocz(sizeof(r2d_fpga_t));
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| 178 | 178 |
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s->irl = irl; |
| 180 | 180 |
|
| ... | ... | |
| 197 | 197 |
return intx[d->devfn >> 3]; |
| 198 | 198 |
} |
| 199 | 199 |
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static void r2d_init(a_ram_addr ram_size,
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static void r2d_init(ram_addr_t ram_size,
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| 201 | 201 |
const char *boot_device, |
| 202 | 202 |
const char *kernel_filename, const char *kernel_cmdline, |
| 203 | 203 |
const char *initrd_filename, const char *cpu_model) |
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{
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CPUState *env; |
| 206 | 206 |
struct SH7750State *s; |
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a_ram_addr sdram_addr;
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ram_addr_t sdram_addr;
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| 208 | 208 |
qemu_irq *irq; |
| 209 | 209 |
PCIBus *pci; |
| 210 | 210 |
DriveInfo *dinfo; |
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