Revision c227f099 target-mips/translate_init.c
| b/target-mips/translate_init.c | ||
|---|---|---|
| 61 | 61 |
MMU_TYPE_R8000 |
| 62 | 62 |
}; |
| 63 | 63 |
|
| 64 |
struct mips_def {
|
|
| 64 |
struct mips_def_t {
|
|
| 65 | 65 |
const char *name; |
| 66 | 66 |
int32_t CP0_PRid; |
| 67 | 67 |
int32_t CP0_Config0; |
| ... | ... | |
| 94 | 94 |
|
| 95 | 95 |
/*****************************************************************************/ |
| 96 | 96 |
/* MIPS CPU definitions */ |
| 97 |
static const a_mips_def mips_defs[] =
|
|
| 97 |
static const mips_def_t mips_defs[] =
|
|
| 98 | 98 |
{
|
| 99 | 99 |
{
|
| 100 | 100 |
.name = "4Kc", |
| ... | ... | |
| 416 | 416 |
#endif |
| 417 | 417 |
}; |
| 418 | 418 |
|
| 419 |
static const a_mips_def *cpu_mips_find_by_name (const char *name)
|
|
| 419 |
static const mips_def_t *cpu_mips_find_by_name (const char *name)
|
|
| 420 | 420 |
{
|
| 421 | 421 |
int i; |
| 422 | 422 |
|
| ... | ... | |
| 439 | 439 |
} |
| 440 | 440 |
|
| 441 | 441 |
#ifndef CONFIG_USER_ONLY |
| 442 |
static void no_mmu_init (CPUMIPSState *env, const a_mips_def *def)
|
|
| 442 |
static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 443 | 443 |
{
|
| 444 | 444 |
env->tlb->nb_tlb = 1; |
| 445 | 445 |
env->tlb->map_address = &no_mmu_map_address; |
| 446 | 446 |
} |
| 447 | 447 |
|
| 448 |
static void fixed_mmu_init (CPUMIPSState *env, const a_mips_def *def)
|
|
| 448 |
static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 449 | 449 |
{
|
| 450 | 450 |
env->tlb->nb_tlb = 1; |
| 451 | 451 |
env->tlb->map_address = &fixed_mmu_map_address; |
| 452 | 452 |
} |
| 453 | 453 |
|
| 454 |
static void r4k_mmu_init (CPUMIPSState *env, const a_mips_def *def)
|
|
| 454 |
static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 455 | 455 |
{
|
| 456 | 456 |
env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
| 457 | 457 |
env->tlb->map_address = &r4k_map_address; |
| ... | ... | |
| 461 | 461 |
env->tlb->helper_tlbr = r4k_helper_tlbr; |
| 462 | 462 |
} |
| 463 | 463 |
|
| 464 |
static void mmu_init (CPUMIPSState *env, const a_mips_def *def)
|
|
| 464 |
static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 465 | 465 |
{
|
| 466 | 466 |
env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext)); |
| 467 | 467 |
|
| ... | ... | |
| 486 | 486 |
} |
| 487 | 487 |
#endif /* CONFIG_USER_ONLY */ |
| 488 | 488 |
|
| 489 |
static void fpu_init (CPUMIPSState *env, const a_mips_def *def)
|
|
| 489 |
static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 490 | 490 |
{
|
| 491 | 491 |
int i; |
| 492 | 492 |
|
| ... | ... | |
| 504 | 504 |
#endif |
| 505 | 505 |
} |
| 506 | 506 |
|
| 507 |
static void mvp_init (CPUMIPSState *env, const a_mips_def *def)
|
|
| 507 |
static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
|
|
| 508 | 508 |
{
|
| 509 | 509 |
env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext)); |
| 510 | 510 |
|
| ... | ... | |
| 531 | 531 |
(0x1 << CP0MVPC1_PCP1); |
| 532 | 532 |
} |
| 533 | 533 |
|
| 534 |
static int cpu_mips_register (CPUMIPSState *env, const a_mips_def *def)
|
|
| 534 |
static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
|
|
| 535 | 535 |
{
|
| 536 | 536 |
env->CP0_PRid = def->CP0_PRid; |
| 537 | 537 |
env->CP0_Config0 = def->CP0_Config0; |
Also available in: Unified diff