Revision c227f099 target-ppc/translate.c
| b/target-ppc/translate.c | ||
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| 191 | 191 |
int fpu_enabled; |
| 192 | 192 |
int altivec_enabled; |
| 193 | 193 |
int spe_enabled; |
| 194 |
a_ppc_spr *spr_cb; /* Needed to check rights for mfspr/mtspr */
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| 194 |
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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| 195 | 195 |
int singlestep_enabled; |
| 196 | 196 |
} DisasContext; |
| 197 | 197 |
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| 198 |
struct opc_handler {
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| 198 |
struct opc_handler_t {
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| 199 | 199 |
/* invalid bits */ |
| 200 | 200 |
uint32_t inval; |
| 201 | 201 |
/* instruction type */ |
| ... | ... | |
| 318 | 318 |
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
| 319 | 319 |
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type) |
| 320 | 320 |
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typedef struct opcode {
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typedef struct opcode_t {
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| 322 | 322 |
unsigned char opc1, opc2, opc3; |
| 323 | 323 |
#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
| 324 | 324 |
unsigned char pad[5]; |
| 325 | 325 |
#else |
| 326 | 326 |
unsigned char pad[1]; |
| 327 | 327 |
#endif |
| 328 |
an_opc_handler handler;
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opc_handler_t handler;
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| 329 | 329 |
const char *oname; |
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} an_opcode;
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} opcode_t;
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| 331 | 331 |
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| 332 | 332 |
/*****************************************************************************/ |
| 333 | 333 |
/*** Instruction decoding ***/ |
| ... | ... | |
| 530 | 530 |
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
| 531 | 531 |
} |
| 532 | 532 |
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| 533 |
static an_opc_handler invalid_handler = {
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static opc_handler_t invalid_handler = {
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| 534 | 534 |
.inval = 0xFFFFFFFF, |
| 535 | 535 |
.type = PPC_NONE, |
| 536 | 536 |
.handler = gen_invalid, |
| ... | ... | |
| 7975 | 7975 |
GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
| 7976 | 7976 |
GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // |
| 7977 | 7977 |
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| 7978 |
static an_opcode opcodes[] = {
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static opcode_t opcodes[] = {
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| 7979 | 7979 |
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
| 7980 | 7980 |
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), |
| 7981 | 7981 |
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
| ... | ... | |
| 8903 | 8903 |
int flags) |
| 8904 | 8904 |
{
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| 8905 | 8905 |
#if defined(DO_PPC_STATISTICS) |
| 8906 |
an_opc_handler **t1, **t2, **t3, *handler;
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opc_handler_t **t1, **t2, **t3, *handler;
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| 8907 | 8907 |
int op1, op2, op3; |
| 8908 | 8908 |
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| 8909 | 8909 |
t1 = env->opcodes; |
| ... | ... | |
| 8951 | 8951 |
int search_pc) |
| 8952 | 8952 |
{
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| 8953 | 8953 |
DisasContext ctx, *ctxp = &ctx; |
| 8954 |
an_opc_handler **table, *handler;
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opc_handler_t **table, *handler;
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| 8955 | 8955 |
target_ulong pc_start; |
| 8956 | 8956 |
uint16_t *gen_opc_end; |
| 8957 | 8957 |
CPUBreakpoint *bp; |
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