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/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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enum {
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TLBRET_DIRTY = -4,
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TLBRET_INVALID = -3,
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TLBRET_NOMATCH = -2,
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TLBRET_BADADDR = -1,
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TLBRET_MATCH = 0
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}; |
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|
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/* no MMU emulation */
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int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, |
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target_ulong address, int rw, int access_type) |
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{
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE; |
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return TLBRET_MATCH;
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} |
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|
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/* fixed mapping MMU emulation */
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int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot, |
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target_ulong address, int rw, int access_type) |
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{
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if (address <= (int32_t)0x7FFFFFFFUL) { |
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if (!(env->CP0_Status & (1 << CP0St_ERL))) |
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*physical = address + 0x40000000UL;
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else
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*physical = address; |
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} else if (address <= (int32_t)0xBFFFFFFFUL) |
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*physical = address & 0x1FFFFFFF;
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else
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*physical = address; |
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|
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*prot = PAGE_READ | PAGE_WRITE; |
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return TLBRET_MATCH;
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} |
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|
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/* MIPS32/MIPS64 R4000-style MMU emulation */
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int r4k_map_address (CPUState *env, target_ulong *physical, int *prot, |
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target_ulong address, int rw, int access_type) |
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{
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uint8_t ASID = env->CP0_EntryHi & 0xFF;
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int i;
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|
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for (i = 0; i < env->tlb->tlb_in_use; i++) { |
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r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; |
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/* 1k pages are not supported. */
|
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target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
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target_ulong tag = address & ~mask; |
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target_ulong VPN = tlb->VPN & ~mask; |
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#if defined(TARGET_MIPS64)
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tag &= env->SEGMask; |
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#endif
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|
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/* Check ASID, virtual page number & size */
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if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
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/* TLB match */
|
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int n = !!(address & mask & ~(mask >> 1)); |
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/* Check access rights */
|
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if (!(n ? tlb->V1 : tlb->V0))
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return TLBRET_INVALID;
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if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { |
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*physical = tlb->PFN[n] | (address & (mask >> 1));
|
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*prot = PAGE_READ; |
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if (n ? tlb->D1 : tlb->D0)
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*prot |= PAGE_WRITE; |
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return TLBRET_MATCH;
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} |
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return TLBRET_DIRTY;
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} |
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} |
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return TLBRET_NOMATCH;
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} |
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|
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#if !defined(CONFIG_USER_ONLY)
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static int get_physical_address (CPUState *env, target_ulong *physical, |
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int *prot, target_ulong address,
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int rw, int access_type) |
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{
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/* User mode can only access useg/xuseg */
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int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
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int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
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int kernel_mode = !user_mode && !supervisor_mode;
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#if defined(TARGET_MIPS64)
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int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
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int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
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int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
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#endif
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int ret = TLBRET_MATCH;
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|
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#if 0
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qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
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#endif
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|
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if (address <= (int32_t)0x7FFFFFFFUL) { |
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/* useg */
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if (env->CP0_Status & (1 << CP0St_ERL)) { |
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*physical = address & 0xFFFFFFFF;
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*prot = PAGE_READ | PAGE_WRITE; |
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} else {
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
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} |
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#if defined(TARGET_MIPS64)
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} else if (address < 0x4000000000000000ULL) { |
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/* xuseg */
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if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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} else if (address < 0x8000000000000000ULL) { |
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/* xsseg */
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if ((supervisor_mode || kernel_mode) &&
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SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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} else if (address < 0xC000000000000000ULL) { |
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/* xkphys */
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if (kernel_mode && KX &&
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(address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
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*physical = address & env->PAMask; |
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*prot = PAGE_READ | PAGE_WRITE; |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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} else if (address < 0xFFFFFFFF80000000ULL) { |
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/* xkseg */
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if (kernel_mode && KX &&
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address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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#endif
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} else if (address < (int32_t)0xA0000000UL) { |
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/* kseg0 */
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if (kernel_mode) {
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*physical = address - (int32_t)0x80000000UL;
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*prot = PAGE_READ | PAGE_WRITE; |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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} else if (address < (int32_t)0xC0000000UL) { |
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/* kseg1 */
|
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if (kernel_mode) {
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*physical = address - (int32_t)0xA0000000UL;
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*prot = PAGE_READ | PAGE_WRITE; |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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} else if (address < (int32_t)0xE0000000UL) { |
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/* sseg (kseg2) */
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if (supervisor_mode || kernel_mode) {
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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} else {
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/* kseg3 */
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/* XXX: debug segment is not emulated */
|
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if (kernel_mode) {
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ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); |
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} else {
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ret = TLBRET_BADADDR; |
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} |
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} |
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#if 0
|
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qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
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address, rw, access_type, *physical, *prot, ret);
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#endif
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return ret;
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} |
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#endif
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|
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
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{
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#if defined(CONFIG_USER_ONLY)
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return addr;
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#else
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target_ulong phys_addr; |
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int prot;
|
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|
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if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) |
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return -1; |
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return phys_addr;
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#endif
|
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} |
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|
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int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{
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#if !defined(CONFIG_USER_ONLY)
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target_ulong physical; |
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int prot;
|
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#endif
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int exception = 0, error_code = 0; |
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int access_type;
|
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int ret = 0; |
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|
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#if 0
|
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log_cpu_state(env, 0);
|
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#endif
|
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qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n", |
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__func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu); |
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|
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rw &= 1;
|
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|
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/* data access */
|
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/* XXX: put correct access by using cpu_restore_state()
|
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correctly */
|
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access_type = ACCESS_INT; |
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#if defined(CONFIG_USER_ONLY)
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ret = TLBRET_NOMATCH; |
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#else
|
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ret = get_physical_address(env, &physical, &prot, |
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address, rw, access_type); |
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qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n", |
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__func__, address, ret, physical, prot); |
| 248 |
if (ret == TLBRET_MATCH) {
|
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ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
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physical & TARGET_PAGE_MASK, prot, |
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mmu_idx, is_softmmu); |
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} else if (ret < 0) |
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#endif
|
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{
|
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switch (ret) {
|
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default:
|
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case TLBRET_BADADDR:
|
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/* Reference to kernel address from user mode or supervisor mode */
|
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/* Reference to supervisor address from user mode */
|
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if (rw)
|
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exception = EXCP_AdES; |
| 262 |
else
|
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exception = EXCP_AdEL; |
| 264 |
break;
|
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case TLBRET_NOMATCH:
|
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/* No TLB match for a mapped address */
|
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if (rw)
|
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exception = EXCP_TLBS; |
| 269 |
else
|
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exception = EXCP_TLBL; |
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error_code = 1;
|
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break;
|
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case TLBRET_INVALID:
|
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/* TLB match with no valid bit */
|
| 275 |
if (rw)
|
| 276 |
exception = EXCP_TLBS; |
| 277 |
else
|
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exception = EXCP_TLBL; |
| 279 |
break;
|
| 280 |
case TLBRET_DIRTY:
|
| 281 |
/* TLB match but 'D' bit is cleared */
|
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exception = EXCP_LTLBL; |
| 283 |
break;
|
| 284 |
|
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} |
| 286 |
/* Raise exception */
|
| 287 |
env->CP0_BadVAddr = address; |
| 288 |
env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
|
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((address >> 9) & 0x007ffff0); |
| 290 |
env->CP0_EntryHi = |
| 291 |
(env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); |
| 292 |
#if defined(TARGET_MIPS64)
|
| 293 |
env->CP0_EntryHi &= env->SEGMask; |
| 294 |
env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | |
| 295 |
((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | |
| 296 |
((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); |
| 297 |
#endif
|
| 298 |
env->exception_index = exception; |
| 299 |
env->error_code = error_code; |
| 300 |
ret = 1;
|
| 301 |
} |
| 302 |
|
| 303 |
return ret;
|
| 304 |
} |
| 305 |
|
| 306 |
static const char * const excp_names[EXCP_LAST + 1] = { |
| 307 |
[EXCP_RESET] = "reset",
|
| 308 |
[EXCP_SRESET] = "soft reset",
|
| 309 |
[EXCP_DSS] = "debug single step",
|
| 310 |
[EXCP_DINT] = "debug interrupt",
|
| 311 |
[EXCP_NMI] = "non-maskable interrupt",
|
| 312 |
[EXCP_MCHECK] = "machine check",
|
| 313 |
[EXCP_EXT_INTERRUPT] = "interrupt",
|
| 314 |
[EXCP_DFWATCH] = "deferred watchpoint",
|
| 315 |
[EXCP_DIB] = "debug instruction breakpoint",
|
| 316 |
[EXCP_IWATCH] = "instruction fetch watchpoint",
|
| 317 |
[EXCP_AdEL] = "address error load",
|
| 318 |
[EXCP_AdES] = "address error store",
|
| 319 |
[EXCP_TLBF] = "TLB refill",
|
| 320 |
[EXCP_IBE] = "instruction bus error",
|
| 321 |
[EXCP_DBp] = "debug breakpoint",
|
| 322 |
[EXCP_SYSCALL] = "syscall",
|
| 323 |
[EXCP_BREAK] = "break",
|
| 324 |
[EXCP_CpU] = "coprocessor unusable",
|
| 325 |
[EXCP_RI] = "reserved instruction",
|
| 326 |
[EXCP_OVERFLOW] = "arithmetic overflow",
|
| 327 |
[EXCP_TRAP] = "trap",
|
| 328 |
[EXCP_FPE] = "floating point",
|
| 329 |
[EXCP_DDBS] = "debug data break store",
|
| 330 |
[EXCP_DWATCH] = "data watchpoint",
|
| 331 |
[EXCP_LTLBL] = "TLB modify",
|
| 332 |
[EXCP_TLBL] = "TLB load",
|
| 333 |
[EXCP_TLBS] = "TLB store",
|
| 334 |
[EXCP_DBE] = "data bus error",
|
| 335 |
[EXCP_DDBL] = "debug data break load",
|
| 336 |
[EXCP_THREAD] = "thread",
|
| 337 |
[EXCP_MDMX] = "MDMX",
|
| 338 |
[EXCP_C2E] = "precise coprocessor 2",
|
| 339 |
[EXCP_CACHE] = "cache error",
|
| 340 |
}; |
| 341 |
|
| 342 |
void do_interrupt (CPUState *env)
|
| 343 |
{
|
| 344 |
#if !defined(CONFIG_USER_ONLY)
|
| 345 |
target_ulong offset; |
| 346 |
int cause = -1; |
| 347 |
const char *name; |
| 348 |
|
| 349 |
if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
|
| 350 |
if (env->exception_index < 0 || env->exception_index > EXCP_LAST) |
| 351 |
name = "unknown";
|
| 352 |
else
|
| 353 |
name = excp_names[env->exception_index]; |
| 354 |
|
| 355 |
qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", |
| 356 |
__func__, env->active_tc.PC, env->CP0_EPC, name); |
| 357 |
} |
| 358 |
if (env->exception_index == EXCP_EXT_INTERRUPT &&
|
| 359 |
(env->hflags & MIPS_HFLAG_DM)) |
| 360 |
env->exception_index = EXCP_DINT; |
| 361 |
offset = 0x180;
|
| 362 |
switch (env->exception_index) {
|
| 363 |
case EXCP_DSS:
|
| 364 |
env->CP0_Debug |= 1 << CP0DB_DSS;
|
| 365 |
/* Debug single step cannot be raised inside a delay slot and
|
| 366 |
resume will always occur on the next instruction
|
| 367 |
(but we assume the pc has always been updated during
|
| 368 |
code translation). */
|
| 369 |
env->CP0_DEPC = env->active_tc.PC; |
| 370 |
goto enter_debug_mode;
|
| 371 |
case EXCP_DINT:
|
| 372 |
env->CP0_Debug |= 1 << CP0DB_DINT;
|
| 373 |
goto set_DEPC;
|
| 374 |
case EXCP_DIB:
|
| 375 |
env->CP0_Debug |= 1 << CP0DB_DIB;
|
| 376 |
goto set_DEPC;
|
| 377 |
case EXCP_DBp:
|
| 378 |
env->CP0_Debug |= 1 << CP0DB_DBp;
|
| 379 |
goto set_DEPC;
|
| 380 |
case EXCP_DDBS:
|
| 381 |
env->CP0_Debug |= 1 << CP0DB_DDBS;
|
| 382 |
goto set_DEPC;
|
| 383 |
case EXCP_DDBL:
|
| 384 |
env->CP0_Debug |= 1 << CP0DB_DDBL;
|
| 385 |
set_DEPC:
|
| 386 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
| 387 |
/* If the exception was raised from a delay slot,
|
| 388 |
come back to the jump. */
|
| 389 |
env->CP0_DEPC = env->active_tc.PC - 4;
|
| 390 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
| 391 |
} else {
|
| 392 |
env->CP0_DEPC = env->active_tc.PC; |
| 393 |
} |
| 394 |
enter_debug_mode:
|
| 395 |
env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
| 396 |
env->hflags &= ~(MIPS_HFLAG_KSU); |
| 397 |
/* EJTAG probe trap enable is not implemented... */
|
| 398 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
| 399 |
env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
| 400 |
env->active_tc.PC = (int32_t)0xBFC00480;
|
| 401 |
break;
|
| 402 |
case EXCP_RESET:
|
| 403 |
cpu_reset(env); |
| 404 |
break;
|
| 405 |
case EXCP_SRESET:
|
| 406 |
env->CP0_Status |= (1 << CP0St_SR);
|
| 407 |
memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); |
| 408 |
goto set_error_EPC;
|
| 409 |
case EXCP_NMI:
|
| 410 |
env->CP0_Status |= (1 << CP0St_NMI);
|
| 411 |
set_error_EPC:
|
| 412 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
| 413 |
/* If the exception was raised from a delay slot,
|
| 414 |
come back to the jump. */
|
| 415 |
env->CP0_ErrorEPC = env->active_tc.PC - 4;
|
| 416 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
| 417 |
} else {
|
| 418 |
env->CP0_ErrorEPC = env->active_tc.PC; |
| 419 |
} |
| 420 |
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
| 421 |
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
| 422 |
env->hflags &= ~(MIPS_HFLAG_KSU); |
| 423 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) |
| 424 |
env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
| 425 |
env->active_tc.PC = (int32_t)0xBFC00000;
|
| 426 |
break;
|
| 427 |
case EXCP_EXT_INTERRUPT:
|
| 428 |
cause = 0;
|
| 429 |
if (env->CP0_Cause & (1 << CP0Ca_IV)) |
| 430 |
offset = 0x200;
|
| 431 |
goto set_EPC;
|
| 432 |
case EXCP_LTLBL:
|
| 433 |
cause = 1;
|
| 434 |
goto set_EPC;
|
| 435 |
case EXCP_TLBL:
|
| 436 |
cause = 2;
|
| 437 |
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
| 438 |
#if defined(TARGET_MIPS64)
|
| 439 |
int R = env->CP0_BadVAddr >> 62; |
| 440 |
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
| 441 |
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
| 442 |
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
| 443 |
|
| 444 |
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
| 445 |
offset = 0x080;
|
| 446 |
else
|
| 447 |
#endif
|
| 448 |
offset = 0x000;
|
| 449 |
} |
| 450 |
goto set_EPC;
|
| 451 |
case EXCP_TLBS:
|
| 452 |
cause = 3;
|
| 453 |
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { |
| 454 |
#if defined(TARGET_MIPS64)
|
| 455 |
int R = env->CP0_BadVAddr >> 62; |
| 456 |
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
| 457 |
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; |
| 458 |
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
| 459 |
|
| 460 |
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) |
| 461 |
offset = 0x080;
|
| 462 |
else
|
| 463 |
#endif
|
| 464 |
offset = 0x000;
|
| 465 |
} |
| 466 |
goto set_EPC;
|
| 467 |
case EXCP_AdEL:
|
| 468 |
cause = 4;
|
| 469 |
goto set_EPC;
|
| 470 |
case EXCP_AdES:
|
| 471 |
cause = 5;
|
| 472 |
goto set_EPC;
|
| 473 |
case EXCP_IBE:
|
| 474 |
cause = 6;
|
| 475 |
goto set_EPC;
|
| 476 |
case EXCP_DBE:
|
| 477 |
cause = 7;
|
| 478 |
goto set_EPC;
|
| 479 |
case EXCP_SYSCALL:
|
| 480 |
cause = 8;
|
| 481 |
goto set_EPC;
|
| 482 |
case EXCP_BREAK:
|
| 483 |
cause = 9;
|
| 484 |
goto set_EPC;
|
| 485 |
case EXCP_RI:
|
| 486 |
cause = 10;
|
| 487 |
goto set_EPC;
|
| 488 |
case EXCP_CpU:
|
| 489 |
cause = 11;
|
| 490 |
env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
|
| 491 |
(env->error_code << CP0Ca_CE); |
| 492 |
goto set_EPC;
|
| 493 |
case EXCP_OVERFLOW:
|
| 494 |
cause = 12;
|
| 495 |
goto set_EPC;
|
| 496 |
case EXCP_TRAP:
|
| 497 |
cause = 13;
|
| 498 |
goto set_EPC;
|
| 499 |
case EXCP_FPE:
|
| 500 |
cause = 15;
|
| 501 |
goto set_EPC;
|
| 502 |
case EXCP_C2E:
|
| 503 |
cause = 18;
|
| 504 |
goto set_EPC;
|
| 505 |
case EXCP_MDMX:
|
| 506 |
cause = 22;
|
| 507 |
goto set_EPC;
|
| 508 |
case EXCP_DWATCH:
|
| 509 |
cause = 23;
|
| 510 |
/* XXX: TODO: manage defered watch exceptions */
|
| 511 |
goto set_EPC;
|
| 512 |
case EXCP_MCHECK:
|
| 513 |
cause = 24;
|
| 514 |
goto set_EPC;
|
| 515 |
case EXCP_THREAD:
|
| 516 |
cause = 25;
|
| 517 |
goto set_EPC;
|
| 518 |
case EXCP_CACHE:
|
| 519 |
cause = 30;
|
| 520 |
if (env->CP0_Status & (1 << CP0St_BEV)) { |
| 521 |
offset = 0x100;
|
| 522 |
} else {
|
| 523 |
offset = 0x20000100;
|
| 524 |
} |
| 525 |
set_EPC:
|
| 526 |
if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
| 527 |
if (env->hflags & MIPS_HFLAG_BMASK) {
|
| 528 |
/* If the exception was raised from a delay slot,
|
| 529 |
come back to the jump. */
|
| 530 |
env->CP0_EPC = env->active_tc.PC - 4;
|
| 531 |
env->CP0_Cause |= (1 << CP0Ca_BD);
|
| 532 |
} else {
|
| 533 |
env->CP0_EPC = env->active_tc.PC; |
| 534 |
env->CP0_Cause &= ~(1 << CP0Ca_BD);
|
| 535 |
} |
| 536 |
env->CP0_Status |= (1 << CP0St_EXL);
|
| 537 |
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; |
| 538 |
env->hflags &= ~(MIPS_HFLAG_KSU); |
| 539 |
} |
| 540 |
env->hflags &= ~MIPS_HFLAG_BMASK; |
| 541 |
if (env->CP0_Status & (1 << CP0St_BEV)) { |
| 542 |
env->active_tc.PC = (int32_t)0xBFC00200;
|
| 543 |
} else {
|
| 544 |
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
|
| 545 |
} |
| 546 |
env->active_tc.PC += offset; |
| 547 |
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
|
| 548 |
break;
|
| 549 |
default:
|
| 550 |
qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
| 551 |
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
|
| 552 |
exit(1);
|
| 553 |
} |
| 554 |
if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
|
| 555 |
qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" |
| 556 |
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
| 557 |
__func__, env->active_tc.PC, env->CP0_EPC, cause, |
| 558 |
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
| 559 |
env->CP0_DEPC); |
| 560 |
} |
| 561 |
#endif
|
| 562 |
env->exception_index = EXCP_NONE; |
| 563 |
} |
| 564 |
|
| 565 |
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) |
| 566 |
{
|
| 567 |
r4k_tlb_t *tlb; |
| 568 |
target_ulong addr; |
| 569 |
target_ulong end; |
| 570 |
uint8_t ASID = env->CP0_EntryHi & 0xFF;
|
| 571 |
target_ulong mask; |
| 572 |
|
| 573 |
tlb = &env->tlb->mmu.r4k.tlb[idx]; |
| 574 |
/* The qemu TLB is flushed when the ASID changes, so no need to
|
| 575 |
flush these entries again. */
|
| 576 |
if (tlb->G == 0 && tlb->ASID != ASID) { |
| 577 |
return;
|
| 578 |
} |
| 579 |
|
| 580 |
if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
|
| 581 |
/* For tlbwr, we can shadow the discarded entry into
|
| 582 |
a new (fake) TLB entry, as long as the guest can not
|
| 583 |
tell that it's there. */
|
| 584 |
env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; |
| 585 |
env->tlb->tlb_in_use++; |
| 586 |
return;
|
| 587 |
} |
| 588 |
|
| 589 |
/* 1k pages are not supported. */
|
| 590 |
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
|
| 591 |
if (tlb->V0) {
|
| 592 |
addr = tlb->VPN & ~mask; |
| 593 |
#if defined(TARGET_MIPS64)
|
| 594 |
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
| 595 |
addr |= 0x3FFFFF0000000000ULL;
|
| 596 |
} |
| 597 |
#endif
|
| 598 |
end = addr | (mask >> 1);
|
| 599 |
while (addr < end) {
|
| 600 |
tlb_flush_page (env, addr); |
| 601 |
addr += TARGET_PAGE_SIZE; |
| 602 |
} |
| 603 |
} |
| 604 |
if (tlb->V1) {
|
| 605 |
addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
| 606 |
#if defined(TARGET_MIPS64)
|
| 607 |
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
| 608 |
addr |= 0x3FFFFF0000000000ULL;
|
| 609 |
} |
| 610 |
#endif
|
| 611 |
end = addr | mask; |
| 612 |
while (addr - 1 < end) { |
| 613 |
tlb_flush_page (env, addr); |
| 614 |
addr += TARGET_PAGE_SIZE; |
| 615 |
} |
| 616 |
} |
| 617 |
} |