Revision c2432a42 hw/sh7750.c
| b/hw/sh7750.c | ||
|---|---|---|
| 42 | 42 |
uint32_t periph_freq; |
| 43 | 43 |
/* SDRAM controller */ |
| 44 | 44 |
uint32_t bcr1; |
| 45 |
uint32_t bcr2; |
|
| 45 |
uint16_t bcr2; |
|
| 46 |
uint16_t bcr3; |
|
| 47 |
uint32_t bcr4; |
|
| 46 | 48 |
uint16_t rfcr; |
| 49 |
/* PCMCIA controller */ |
|
| 50 |
uint16_t pcr; |
|
| 47 | 51 |
/* IO ports */ |
| 48 | 52 |
uint16_t gpioic; |
| 49 | 53 |
uint32_t pctra; |
| ... | ... | |
| 66 | 70 |
struct intc_desc intc; |
| 67 | 71 |
} SH7750State; |
| 68 | 72 |
|
| 69 |
|
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static int inline has_bcr3_and_bcr4(SH7750State * s) |
|
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{
|
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return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4); |
|
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} |
|
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/********************************************************************** |
| 71 | 78 |
I/O ports |
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**********************************************************************/ |
| ... | ... | |
| 211 | 218 |
switch (addr) {
|
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case SH7750_BCR2_A7: |
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return s->bcr2; |
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case SH7750_BCR3_A7: |
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if(!has_bcr3_and_bcr4(s)) |
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error_access("word read", addr);
|
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return s->bcr3; |
|
| 214 | 225 |
case SH7750_FRQCR_A7: |
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return 0; |
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case SH7750_PCR_A7: |
|
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return s->pcr; |
|
| 216 | 229 |
case SH7750_RFCR_A7: |
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fprintf(stderr, |
| 218 | 231 |
"Read access to refresh count register, incrementing\n"); |
| ... | ... | |
| 221 | 234 |
return porta_lines(s); |
| 222 | 235 |
case SH7750_PDTRB_A7: |
| 223 | 236 |
return portb_lines(s); |
| 237 |
case SH7750_RTCOR_A7: |
|
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case SH7750_RTCNT_A7: |
|
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case SH7750_RTCSR_A7: |
|
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ignore_access("word read", addr);
|
|
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return 0; |
|
| 224 | 242 |
default: |
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error_access("word read", addr);
|
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assert(0); |
| ... | ... | |
| 235 | 253 |
case SH7750_BCR1_A7: |
| 236 | 254 |
return s->bcr1; |
| 237 | 255 |
case SH7750_BCR4_A7: |
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if(!has_bcr3_and_bcr4(s)) |
|
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error_access("long read", addr);
|
|
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return s->bcr4; |
|
| 238 | 259 |
case SH7750_WCR1_A7: |
| 239 | 260 |
case SH7750_WCR2_A7: |
| 240 | 261 |
case SH7750_WCR3_A7: |
| ... | ... | |
| 271 | 292 |
} |
| 272 | 293 |
} |
| 273 | 294 |
|
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#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ |
|
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&& a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) |
|
| 274 | 297 |
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr, |
| 275 | 298 |
uint32_t mem_value) |
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{
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switch (addr) {
|
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/* PRECHARGE ? XXXXX */ |
|
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case SH7750_PRECHARGE0_A7: |
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case SH7750_PRECHARGE1_A7: |
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|
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if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
|
|
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ignore_access("byte write", addr);
|
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return; |
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default: |
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error_access("byte write", addr);
|
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assert(0); |
|
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} |
| 305 |
|
|
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error_access("byte write", addr);
|
|
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assert(0); |
|
| 287 | 308 |
} |
| 288 | 309 |
|
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static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr, |
| ... | ... | |
| 298 | 319 |
s->bcr2 = mem_value; |
| 299 | 320 |
return; |
| 300 | 321 |
case SH7750_BCR3_A7: |
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case SH7750_RTCOR_A7: |
|
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if(!has_bcr3_and_bcr4(s)) |
|
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error_access("word write", addr);
|
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s->bcr3 = mem_value; |
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return; |
|
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case SH7750_PCR_A7: |
|
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s->pcr = mem_value; |
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return; |
|
| 302 | 329 |
case SH7750_RTCNT_A7: |
| 330 |
case SH7750_RTCOR_A7: |
|
| 303 | 331 |
case SH7750_RTCSR_A7: |
| 304 | 332 |
ignore_access("word write", addr);
|
| 305 | 333 |
return; |
| ... | ... | |
| 343 | 371 |
s->bcr1 = mem_value; |
| 344 | 372 |
return; |
| 345 | 373 |
case SH7750_BCR4_A7: |
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if(!has_bcr3_and_bcr4(s)) |
|
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error_access("long write", addr);
|
|
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s->bcr4 = mem_value; |
|
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return; |
|
| 346 | 378 |
case SH7750_WCR1_A7: |
| 347 | 379 |
case SH7750_WCR2_A7: |
| 348 | 380 |
case SH7750_WCR3_A7: |
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