Revision c2432a42 hw/sh7750_regs.h
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#define SH7750_RFCR_KEY 0xA400 /* RFCR write key */ |
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/* Synchronous DRAM mode registers - SDMR */ |
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#define SH7750_SDMR2_REGOFS 0x900000 /* base offset */ |
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#define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */ |
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#define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS) |
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#define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS) |
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#define SH7750_SDMR3_REGOFS 0x940000 /* offset */ |
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#define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */ |
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#define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS) |
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#define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS) |
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/* |
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* Direct Memory Access Controller (DMAC) |
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*/ |
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*/ |
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#define SH7750_BCR3_A7 0x1f800050 |
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#define SH7750_BCR4_A7 0x1e0a00f0 |
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#define SH7750_PRECHARGE0_A7 0x1f900088 |
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#define SH7750_PRECHARGE1_A7 0x1f940088 |
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#endif |
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