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    jmp_buf jmp_env;                                                    \

    int exception_index;                                                \

                                                                        \

    int cpu_index; /* CPU index (informative) */                        \

    int running; /* Nonzero if cpu is currently running(usermode).  */  \

    /* user data */                                                     \

    CPUState **penv;

    int cpu_index;

    env->next_cpu = NULL;

    penv = &first_cpu;

    cpu_index = 0;

    TAILQ_INIT(&env->breakpoints);

    TAILQ_INIT(&env->watchpoints);

    *penv = env;

#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)

    register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,

                    cpu_common_save, cpu_common_load, env);

   We don't require a full sync, only that no cpus are executing guest code.

   The alternative is to map target atomic ops onto host equivalents,

   which requires quite a lot of per host/target work.  */

static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;

static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;

static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;

        thread_env->next_cpu = NULL;

        pending_cpus = 0;

        pthread_mutex_init(&exclusive_lock, NULL);

        pthread_cond_init(&exclusive_cond, NULL);

        pthread_cond_init(&exclusive_resume, NULL);

        pthread_mutex_init(&tb_lock, NULL);

    exclusive_idle();

    pthread_mutex_unlock(&exclusive_lock);

}

#else /* if !USE_NPTL */

/* These are no-ops because we are not threadsafe.  */

static inline void cpu_exec_start(CPUState *env)

        gdbserver_fork(thread_env);

    }

}

#endif

    uint32_t v86flags;

    uint32_t v86mask;

#endif

#ifdef TARGET_M68K

    int sim_syscalls;

#endif

extern unsigned long last_brk;

void mmap_lock(void);

void mmap_unlock(void);

#if defined(USE_NPTL)

void mmap_fork_start(void);

void mmap_fork_end(int child);

    return err;

}

			      struct target_sigcontext *sc)

{

    unsigned int err = 0;

}

#define __NR_sys_uname __NR_uname

#define __NR_sys_faccessat __NR_faccessat

#define __NR_sys_fchmodat __NR_fchmodat

    return -ENOSYS;

}

#endif

_syscall1(int,sys_uname,struct new_utsname *,buf)

#if defined(TARGET_NR_faccessat) && defined(__NR_faccessat)

_syscall4(int,sys_faccessat,int,dirfd,const char *,pathname,int,mode,int,flags)

        nptl_flags = flags;

        flags &= ~CLONE_NPTL_FLAGS2;

        if (nptl_flags & CLONE_SETTLS)

            cpu_set_tls (new_env, newtls);

        sigprocmask(SIG_BLOCK, &sigmask, &info.sigmask);

        ret = pthread_create(&info.thread, &attr, clone_func, &info);

        sigprocmask(SIG_SETMASK, &info.sigmask, NULL);

        pthread_attr_destroy(&attr);

            ts = (TaskState *)env->opaque;

            if (flags & CLONE_SETTLS)

                cpu_set_tls (env, newtls);

#endif

        } else {

            fork_end(0);

    switch(num) {

    case TARGET_NR_exit:

#ifdef HAVE_GPROF

        _mcleanup();

#endif

        gdb_exit(cpu_env, arg1);

        ret = 0; /* avoid warning */

        break;

    case TARGET_NR_read:

#define TARGET_LONG_BITS 64

#include "cpu-defs.h"

#include <setjmp.h>

    pal_handler_t *pal_handler;

};

#define cpu_init cpu_alpha_init

#define cpu_exec cpu_alpha_exec

#define cpu_gen_code cpu_alpha_gen_code

#define ELF_MACHINE	EM_ARM

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_PAGE_BITS 10

#endif

#define cpu_init cpu_arm_init

#define cpu_exec cpu_arm_exec

#define cpu_gen_code cpu_arm_gen_code

#define TARGET_LONG_BITS 32

#include "cpu-defs.h"

#define TARGET_HAS_ICE 1

#define TARGET_PAGE_BITS 13

#define MMAP_SHIFT TARGET_PAGE_BITS

#define cpu_init cpu_cris_init

#define cpu_exec cpu_cris_exec

#define cpu_gen_code cpu_cris_gen_code

#define ELF_MACHINE	EM_386

#endif

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_PAGE_BITS 12

#define cpu_init cpu_x86_init

#define cpu_exec cpu_x86_exec

#define cpu_gen_code cpu_x86_gen_code

#define TARGET_LONG_BITS 32

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_PAGE_BITS 10

#endif

#define cpu_init cpu_m68k_init

#define cpu_exec cpu_m68k_exec

#define cpu_gen_code cpu_m68k_gen_code

#define ELF_MACHINE	EM_MIPS

#include "config.h"

#include "mips-defs.h"

#include "cpu-defs.h"

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,

                          int unused, int size);

#define cpu_init cpu_mips_init

#define cpu_exec cpu_mips_exec

#define cpu_gen_code cpu_mips_gen_code

#endif /* defined (TARGET_PPC64) */

#include "cpu-defs.h"

#define REGX "%016" PRIx64

int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);

int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);

#define cpu_init cpu_ppc_init

#define cpu_exec cpu_ppc_exec

#define cpu_gen_code cpu_ppc_gen_code

#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)

#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)

#include "cpu-defs.h"

#include "softfloat.h"

#include "softfloat.h"

#define cpu_init cpu_sh4_init

#define cpu_exec cpu_sh4_exec

#define cpu_gen_code cpu_sh4_gen_code

#define TARGET_PHYS_ADDR_BITS 64

#include "cpu-defs.h"

#include "softfloat.h"

                          int is_asi, int size);

int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);

#define cpu_init cpu_sparc_init

#define cpu_exec cpu_sparc_exec

#define cpu_gen_code cpu_sparc_gen_code