root / target-m68k / cpu.h @ c2764719
History | View | Annotate | Download (7.1 kB)
1 |
/*
|
---|---|
2 |
* m68k virtual CPU header
|
3 |
*
|
4 |
* Copyright (c) 2005-2007 CodeSourcery
|
5 |
* Written by Paul Brook
|
6 |
*
|
7 |
* This library is free software; you can redistribute it and/or
|
8 |
* modify it under the terms of the GNU Lesser General Public
|
9 |
* License as published by the Free Software Foundation; either
|
10 |
* version 2 of the License, or (at your option) any later version.
|
11 |
*
|
12 |
* This library is distributed in the hope that it will be useful,
|
13 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
15 |
* General Public License for more details.
|
16 |
*
|
17 |
* You should have received a copy of the GNU Lesser General Public
|
18 |
* License along with this library; if not, write to the Free Software
|
19 |
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
|
20 |
*/
|
21 |
#ifndef CPU_M68K_H
|
22 |
#define CPU_M68K_H
|
23 |
|
24 |
#define TARGET_LONG_BITS 32 |
25 |
|
26 |
#define CPUState struct CPUM68KState |
27 |
|
28 |
#include "cpu-defs.h" |
29 |
|
30 |
#include "softfloat.h" |
31 |
|
32 |
#define MAX_QREGS 32 |
33 |
|
34 |
#define TARGET_HAS_ICE 1 |
35 |
|
36 |
#define ELF_MACHINE EM_68K
|
37 |
|
38 |
#define EXCP_ACCESS 2 /* Access (MMU) error. */ |
39 |
#define EXCP_ADDRESS 3 /* Address error. */ |
40 |
#define EXCP_ILLEGAL 4 /* Illegal instruction. */ |
41 |
#define EXCP_DIV0 5 /* Divide by zero */ |
42 |
#define EXCP_PRIVILEGE 8 /* Privilege violation. */ |
43 |
#define EXCP_TRACE 9 |
44 |
#define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ |
45 |
#define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ |
46 |
#define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ |
47 |
#define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ |
48 |
#define EXCP_FORMAT 14 /* RTE format error. */ |
49 |
#define EXCP_UNINITIALIZED 15 |
50 |
#define EXCP_TRAP0 32 /* User trap #0. */ |
51 |
#define EXCP_TRAP15 47 /* User trap #15. */ |
52 |
#define EXCP_UNSUPPORTED 61 |
53 |
#define EXCP_ICE 13 |
54 |
|
55 |
#define EXCP_RTE 0x100 |
56 |
#define EXCP_HALT_INSN 0x101 |
57 |
|
58 |
#define NB_MMU_MODES 2 |
59 |
|
60 |
typedef struct CPUM68KState { |
61 |
uint32_t dregs[8];
|
62 |
uint32_t aregs[8];
|
63 |
uint32_t pc; |
64 |
uint32_t sr; |
65 |
|
66 |
/* SSP and USP. The current_sp is stored in aregs[7], the other here. */
|
67 |
int current_sp;
|
68 |
uint32_t sp[2];
|
69 |
|
70 |
/* Condition flags. */
|
71 |
uint32_t cc_op; |
72 |
uint32_t cc_dest; |
73 |
uint32_t cc_src; |
74 |
uint32_t cc_x; |
75 |
|
76 |
float64 fregs[8];
|
77 |
float64 fp_result; |
78 |
uint32_t fpcr; |
79 |
uint32_t fpsr; |
80 |
float_status fp_status; |
81 |
|
82 |
uint64_t mactmp; |
83 |
/* EMAC Hardware deals with 48-bit values composed of one 32-bit and
|
84 |
two 8-bit parts. We store a single 64-bit value and
|
85 |
rearrange/extend this when changing modes. */
|
86 |
uint64_t macc[4];
|
87 |
uint32_t macsr; |
88 |
uint32_t mac_mask; |
89 |
|
90 |
/* Temporary storage for DIV helpers. */
|
91 |
uint32_t div1; |
92 |
uint32_t div2; |
93 |
|
94 |
/* MMU status. */
|
95 |
struct {
|
96 |
uint32_t ar; |
97 |
} mmu; |
98 |
|
99 |
/* Control registers. */
|
100 |
uint32_t vbr; |
101 |
uint32_t mbar; |
102 |
uint32_t rambar0; |
103 |
uint32_t cacr; |
104 |
|
105 |
/* ??? remove this. */
|
106 |
uint32_t t1; |
107 |
|
108 |
int pending_vector;
|
109 |
int pending_level;
|
110 |
|
111 |
uint32_t qregs[MAX_QREGS]; |
112 |
|
113 |
CPU_COMMON |
114 |
|
115 |
uint32_t features; |
116 |
} CPUM68KState; |
117 |
|
118 |
void m68k_tcg_init(void); |
119 |
CPUM68KState *cpu_m68k_init(const char *cpu_model); |
120 |
int cpu_m68k_exec(CPUM68KState *s);
|
121 |
void cpu_m68k_close(CPUM68KState *s);
|
122 |
void do_interrupt(int is_hw); |
123 |
/* you can call this signal handler from your SIGBUS and SIGSEGV
|
124 |
signal handlers to inform the virtual CPU of exceptions. non zero
|
125 |
is returned if the signal was handled by the virtual CPU. */
|
126 |
int cpu_m68k_signal_handler(int host_signum, void *pinfo, |
127 |
void *puc);
|
128 |
void cpu_m68k_flush_flags(CPUM68KState *, int); |
129 |
|
130 |
enum {
|
131 |
CC_OP_DYNAMIC, /* Use env->cc_op */
|
132 |
CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
|
133 |
CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
|
134 |
CC_OP_ADD, /* CC_DEST = result, CC_SRC = source */
|
135 |
CC_OP_SUB, /* CC_DEST = result, CC_SRC = source */
|
136 |
CC_OP_CMPB, /* CC_DEST = result, CC_SRC = source */
|
137 |
CC_OP_CMPW, /* CC_DEST = result, CC_SRC = source */
|
138 |
CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */
|
139 |
CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */
|
140 |
CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
|
141 |
}; |
142 |
|
143 |
#define CCF_C 0x01 |
144 |
#define CCF_V 0x02 |
145 |
#define CCF_Z 0x04 |
146 |
#define CCF_N 0x08 |
147 |
#define CCF_X 0x10 |
148 |
|
149 |
#define SR_I_SHIFT 8 |
150 |
#define SR_I 0x0700 |
151 |
#define SR_M 0x1000 |
152 |
#define SR_S 0x2000 |
153 |
#define SR_T 0x8000 |
154 |
|
155 |
#define M68K_SSP 0 |
156 |
#define M68K_USP 1 |
157 |
|
158 |
/* CACR fields are implementation defined, but some bits are common. */
|
159 |
#define M68K_CACR_EUSP 0x10 |
160 |
|
161 |
#define MACSR_PAV0 0x100 |
162 |
#define MACSR_OMC 0x080 |
163 |
#define MACSR_SU 0x040 |
164 |
#define MACSR_FI 0x020 |
165 |
#define MACSR_RT 0x010 |
166 |
#define MACSR_N 0x008 |
167 |
#define MACSR_Z 0x004 |
168 |
#define MACSR_V 0x002 |
169 |
#define MACSR_EV 0x001 |
170 |
|
171 |
void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector); |
172 |
void m68k_set_macsr(CPUM68KState *env, uint32_t val);
|
173 |
void m68k_switch_sp(CPUM68KState *env);
|
174 |
|
175 |
#define M68K_FPCR_PREC (1 << 6) |
176 |
|
177 |
void do_m68k_semihosting(CPUM68KState *env, int nr); |
178 |
|
179 |
/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
|
180 |
Each feature covers the subset of instructions common to the
|
181 |
ISA revisions mentioned. */
|
182 |
|
183 |
enum m68k_features {
|
184 |
M68K_FEATURE_CF_ISA_A, |
185 |
M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
|
186 |
M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
|
187 |
M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
|
188 |
M68K_FEATURE_CF_FPU, |
189 |
M68K_FEATURE_CF_MAC, |
190 |
M68K_FEATURE_CF_EMAC, |
191 |
M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
|
192 |
M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
|
193 |
M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
|
194 |
M68K_FEATURE_WORD_INDEX /* word sized address index registers. */
|
195 |
}; |
196 |
|
197 |
static inline int m68k_feature(CPUM68KState *env, int feature) |
198 |
{ |
199 |
return (env->features & (1u << feature)) != 0; |
200 |
} |
201 |
|
202 |
void register_m68k_insns (CPUM68KState *env);
|
203 |
|
204 |
#ifdef CONFIG_USER_ONLY
|
205 |
/* Linux uses 8k pages. */
|
206 |
#define TARGET_PAGE_BITS 13 |
207 |
#else
|
208 |
/* Smallest TLB entry size is 1k. */
|
209 |
#define TARGET_PAGE_BITS 10 |
210 |
#endif
|
211 |
|
212 |
#define cpu_init cpu_m68k_init
|
213 |
#define cpu_exec cpu_m68k_exec
|
214 |
#define cpu_gen_code cpu_m68k_gen_code
|
215 |
#define cpu_signal_handler cpu_m68k_signal_handler
|
216 |
|
217 |
/* MMU modes definitions */
|
218 |
#define MMU_MODE0_SUFFIX _kernel
|
219 |
#define MMU_MODE1_SUFFIX _user
|
220 |
#define MMU_USER_IDX 1 |
221 |
static inline int cpu_mmu_index (CPUState *env) |
222 |
{ |
223 |
return (env->sr & SR_S) == 0 ? 1 : 0; |
224 |
} |
225 |
|
226 |
#if defined(CONFIG_USER_ONLY)
|
227 |
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
228 |
{ |
229 |
if (newsp)
|
230 |
env->aregs[7] = newsp;
|
231 |
env->dregs[0] = 0; |
232 |
} |
233 |
#endif
|
234 |
|
235 |
#include "cpu-all.h" |
236 |
#include "exec-all.h" |
237 |
|
238 |
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
239 |
{ |
240 |
env->pc = tb->pc; |
241 |
} |
242 |
|
243 |
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
244 |
target_ulong *cs_base, int *flags)
|
245 |
{ |
246 |
*pc = env->pc; |
247 |
*cs_base = 0;
|
248 |
*flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
|
249 |
| (env->sr & SR_S) /* Bit 13 */
|
250 |
| ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ |
251 |
} |
252 |
|
253 |
#endif
|