Revision c29b735c target-ppc/cpu.h
| b/target-ppc/cpu.h | ||
|---|---|---|
| 642 | 642 |
powerpc_input_t bus_model; |
| 643 | 643 |
int bfd_mach; |
| 644 | 644 |
uint32_t flags; |
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uint64_t insns_flags; |
|
| 645 | 646 |
|
| 646 | 647 |
int error_code; |
| 647 | 648 |
uint32_t pending_interrupts; |
| ... | ... | |
| 1320 | 1321 |
#define SPR_E500_SVR (0x3FF) |
| 1321 | 1322 |
|
| 1322 | 1323 |
/*****************************************************************************/ |
| 1324 |
/* PowerPC Instructions types definitions */ |
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| 1325 |
enum {
|
|
| 1326 |
PPC_NONE = 0x0000000000000000ULL, |
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| 1327 |
/* PowerPC base instructions set */ |
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| 1328 |
PPC_INSNS_BASE = 0x0000000000000001ULL, |
|
| 1329 |
/* integer operations instructions */ |
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| 1330 |
#define PPC_INTEGER PPC_INSNS_BASE |
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| 1331 |
/* flow control instructions */ |
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#define PPC_FLOW PPC_INSNS_BASE |
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| 1333 |
/* virtual memory instructions */ |
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| 1334 |
#define PPC_MEM PPC_INSNS_BASE |
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| 1335 |
/* ld/st with reservation instructions */ |
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#define PPC_RES PPC_INSNS_BASE |
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| 1337 |
/* spr/msr access instructions */ |
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#define PPC_MISC PPC_INSNS_BASE |
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| 1339 |
/* Deprecated instruction sets */ |
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| 1340 |
/* Original POWER instruction set */ |
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| 1341 |
PPC_POWER = 0x0000000000000002ULL, |
|
| 1342 |
/* POWER2 instruction set extension */ |
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| 1343 |
PPC_POWER2 = 0x0000000000000004ULL, |
|
| 1344 |
/* Power RTC support */ |
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| 1345 |
PPC_POWER_RTC = 0x0000000000000008ULL, |
|
| 1346 |
/* Power-to-PowerPC bridge (601) */ |
|
| 1347 |
PPC_POWER_BR = 0x0000000000000010ULL, |
|
| 1348 |
/* 64 bits PowerPC instruction set */ |
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| 1349 |
PPC_64B = 0x0000000000000020ULL, |
|
| 1350 |
/* New 64 bits extensions (PowerPC 2.0x) */ |
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| 1351 |
PPC_64BX = 0x0000000000000040ULL, |
|
| 1352 |
/* 64 bits hypervisor extensions */ |
|
| 1353 |
PPC_64H = 0x0000000000000080ULL, |
|
| 1354 |
/* New wait instruction (PowerPC 2.0x) */ |
|
| 1355 |
PPC_WAIT = 0x0000000000000100ULL, |
|
| 1356 |
/* Time base mftb instruction */ |
|
| 1357 |
PPC_MFTB = 0x0000000000000200ULL, |
|
| 1358 |
|
|
| 1359 |
/* Fixed-point unit extensions */ |
|
| 1360 |
/* PowerPC 602 specific */ |
|
| 1361 |
PPC_602_SPEC = 0x0000000000000400ULL, |
|
| 1362 |
/* isel instruction */ |
|
| 1363 |
PPC_ISEL = 0x0000000000000800ULL, |
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| 1364 |
/* popcntb instruction */ |
|
| 1365 |
PPC_POPCNTB = 0x0000000000001000ULL, |
|
| 1366 |
/* string load / store */ |
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| 1367 |
PPC_STRING = 0x0000000000002000ULL, |
|
| 1368 |
|
|
| 1369 |
/* Floating-point unit extensions */ |
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| 1370 |
/* Optional floating point instructions */ |
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| 1371 |
PPC_FLOAT = 0x0000000000010000ULL, |
|
| 1372 |
/* New floating-point extensions (PowerPC 2.0x) */ |
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| 1373 |
PPC_FLOAT_EXT = 0x0000000000020000ULL, |
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| 1374 |
PPC_FLOAT_FSQRT = 0x0000000000040000ULL, |
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| 1375 |
PPC_FLOAT_FRES = 0x0000000000080000ULL, |
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| 1376 |
PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL, |
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| 1377 |
PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL, |
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| 1378 |
PPC_FLOAT_FSEL = 0x0000000000400000ULL, |
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| 1379 |
PPC_FLOAT_STFIWX = 0x0000000000800000ULL, |
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| 1380 |
|
|
| 1381 |
/* Vector/SIMD extensions */ |
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| 1382 |
/* Altivec support */ |
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| 1383 |
PPC_ALTIVEC = 0x0000000001000000ULL, |
|
| 1384 |
/* PowerPC 2.03 SPE extension */ |
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| 1385 |
PPC_SPE = 0x0000000002000000ULL, |
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| 1386 |
/* PowerPC 2.03 SPE single-precision floating-point extension */ |
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PPC_SPE_SINGLE = 0x0000000004000000ULL, |
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| 1388 |
/* PowerPC 2.03 SPE double-precision floating-point extension */ |
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| 1389 |
PPC_SPE_DOUBLE = 0x0000000008000000ULL, |
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| 1390 |
|
|
| 1391 |
/* Optional memory control instructions */ |
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| 1392 |
PPC_MEM_TLBIA = 0x0000000010000000ULL, |
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| 1393 |
PPC_MEM_TLBIE = 0x0000000020000000ULL, |
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| 1394 |
PPC_MEM_TLBSYNC = 0x0000000040000000ULL, |
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| 1395 |
/* sync instruction */ |
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| 1396 |
PPC_MEM_SYNC = 0x0000000080000000ULL, |
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| 1397 |
/* eieio instruction */ |
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| 1398 |
PPC_MEM_EIEIO = 0x0000000100000000ULL, |
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| 1399 |
|
|
| 1400 |
/* Cache control instructions */ |
|
| 1401 |
PPC_CACHE = 0x0000000200000000ULL, |
|
| 1402 |
/* icbi instruction */ |
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| 1403 |
PPC_CACHE_ICBI = 0x0000000400000000ULL, |
|
| 1404 |
/* dcbz instruction with fixed cache line size */ |
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| 1405 |
PPC_CACHE_DCBZ = 0x0000000800000000ULL, |
|
| 1406 |
/* dcbz instruction with tunable cache line size */ |
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| 1407 |
PPC_CACHE_DCBZT = 0x0000001000000000ULL, |
|
| 1408 |
/* dcba instruction */ |
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| 1409 |
PPC_CACHE_DCBA = 0x0000002000000000ULL, |
|
| 1410 |
/* Freescale cache locking instructions */ |
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| 1411 |
PPC_CACHE_LOCK = 0x0000004000000000ULL, |
|
| 1412 |
|
|
| 1413 |
/* MMU related extensions */ |
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| 1414 |
/* external control instructions */ |
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| 1415 |
PPC_EXTERN = 0x0000010000000000ULL, |
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| 1416 |
/* segment register access instructions */ |
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| 1417 |
PPC_SEGMENT = 0x0000020000000000ULL, |
|
| 1418 |
/* PowerPC 6xx TLB management instructions */ |
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| 1419 |
PPC_6xx_TLB = 0x0000040000000000ULL, |
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| 1420 |
/* PowerPC 74xx TLB management instructions */ |
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| 1421 |
PPC_74xx_TLB = 0x0000080000000000ULL, |
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| 1422 |
/* PowerPC 40x TLB management instructions */ |
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| 1423 |
PPC_40x_TLB = 0x0000100000000000ULL, |
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| 1424 |
/* segment register access instructions for PowerPC 64 "bridge" */ |
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| 1425 |
PPC_SEGMENT_64B = 0x0000200000000000ULL, |
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| 1426 |
/* SLB management */ |
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| 1427 |
PPC_SLBI = 0x0000400000000000ULL, |
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| 1428 |
|
|
| 1429 |
/* Embedded PowerPC dedicated instructions */ |
|
| 1430 |
PPC_WRTEE = 0x0001000000000000ULL, |
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| 1431 |
/* PowerPC 40x exception model */ |
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| 1432 |
PPC_40x_EXCP = 0x0002000000000000ULL, |
|
| 1433 |
/* PowerPC 405 Mac instructions */ |
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| 1434 |
PPC_405_MAC = 0x0004000000000000ULL, |
|
| 1435 |
/* PowerPC 440 specific instructions */ |
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| 1436 |
PPC_440_SPEC = 0x0008000000000000ULL, |
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| 1437 |
/* BookE (embedded) PowerPC specification */ |
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| 1438 |
PPC_BOOKE = 0x0010000000000000ULL, |
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| 1439 |
/* mfapidi instruction */ |
|
| 1440 |
PPC_MFAPIDI = 0x0020000000000000ULL, |
|
| 1441 |
/* tlbiva instruction */ |
|
| 1442 |
PPC_TLBIVA = 0x0040000000000000ULL, |
|
| 1443 |
/* tlbivax instruction */ |
|
| 1444 |
PPC_TLBIVAX = 0x0080000000000000ULL, |
|
| 1445 |
/* PowerPC 4xx dedicated instructions */ |
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| 1446 |
PPC_4xx_COMMON = 0x0100000000000000ULL, |
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| 1447 |
/* PowerPC 40x ibct instructions */ |
|
| 1448 |
PPC_40x_ICBT = 0x0200000000000000ULL, |
|
| 1449 |
/* rfmci is not implemented in all BookE PowerPC */ |
|
| 1450 |
PPC_RFMCI = 0x0400000000000000ULL, |
|
| 1451 |
/* rfdi instruction */ |
|
| 1452 |
PPC_RFDI = 0x0800000000000000ULL, |
|
| 1453 |
/* DCR accesses */ |
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| 1454 |
PPC_DCR = 0x1000000000000000ULL, |
|
| 1455 |
/* DCR extended accesse */ |
|
| 1456 |
PPC_DCRX = 0x2000000000000000ULL, |
|
| 1457 |
/* user-mode DCR access, implemented in PowerPC 460 */ |
|
| 1458 |
PPC_DCRUX = 0x4000000000000000ULL, |
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| 1459 |
}; |
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| 1460 |
|
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| 1461 |
/*****************************************************************************/ |
|
| 1323 | 1462 |
/* Memory access type : |
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* may be needed for precise access rights control and precise exceptions. |
| 1325 | 1464 |
*/ |
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