Revision c29b735c target-ppc/translate.c
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} |
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/*****************************************************************************/ |
460 |
/* PowerPC Instructions types definitions */ |
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enum { |
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PPC_NONE = 0x0000000000000000ULL, |
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/* PowerPC base instructions set */ |
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PPC_INSNS_BASE = 0x0000000000000001ULL, |
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/* integer operations instructions */ |
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#define PPC_INTEGER PPC_INSNS_BASE |
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/* flow control instructions */ |
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#define PPC_FLOW PPC_INSNS_BASE |
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/* virtual memory instructions */ |
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#define PPC_MEM PPC_INSNS_BASE |
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/* ld/st with reservation instructions */ |
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#define PPC_RES PPC_INSNS_BASE |
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/* spr/msr access instructions */ |
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#define PPC_MISC PPC_INSNS_BASE |
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/* Deprecated instruction sets */ |
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/* Original POWER instruction set */ |
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PPC_POWER = 0x0000000000000002ULL, |
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/* POWER2 instruction set extension */ |
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PPC_POWER2 = 0x0000000000000004ULL, |
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480 |
/* Power RTC support */ |
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PPC_POWER_RTC = 0x0000000000000008ULL, |
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/* Power-to-PowerPC bridge (601) */ |
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PPC_POWER_BR = 0x0000000000000010ULL, |
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484 |
/* 64 bits PowerPC instruction set */ |
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PPC_64B = 0x0000000000000020ULL, |
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486 |
/* New 64 bits extensions (PowerPC 2.0x) */ |
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PPC_64BX = 0x0000000000000040ULL, |
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/* 64 bits hypervisor extensions */ |
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PPC_64H = 0x0000000000000080ULL, |
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/* New wait instruction (PowerPC 2.0x) */ |
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PPC_WAIT = 0x0000000000000100ULL, |
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/* Time base mftb instruction */ |
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PPC_MFTB = 0x0000000000000200ULL, |
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494 |
|
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/* Fixed-point unit extensions */ |
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/* PowerPC 602 specific */ |
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PPC_602_SPEC = 0x0000000000000400ULL, |
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498 |
/* isel instruction */ |
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PPC_ISEL = 0x0000000000000800ULL, |
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500 |
/* popcntb instruction */ |
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PPC_POPCNTB = 0x0000000000001000ULL, |
|
502 |
/* string load / store */ |
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PPC_STRING = 0x0000000000002000ULL, |
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504 |
|
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505 |
/* Floating-point unit extensions */ |
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/* Optional floating point instructions */ |
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PPC_FLOAT = 0x0000000000010000ULL, |
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/* New floating-point extensions (PowerPC 2.0x) */ |
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PPC_FLOAT_EXT = 0x0000000000020000ULL, |
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PPC_FLOAT_FSQRT = 0x0000000000040000ULL, |
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PPC_FLOAT_FRES = 0x0000000000080000ULL, |
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PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL, |
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PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL, |
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PPC_FLOAT_FSEL = 0x0000000000400000ULL, |
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PPC_FLOAT_STFIWX = 0x0000000000800000ULL, |
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516 |
|
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/* Vector/SIMD extensions */ |
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518 |
/* Altivec support */ |
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PPC_ALTIVEC = 0x0000000001000000ULL, |
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520 |
/* PowerPC 2.03 SPE extension */ |
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PPC_SPE = 0x0000000002000000ULL, |
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522 |
/* PowerPC 2.03 SPE single-precision floating-point extension */ |
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PPC_SPE_SINGLE = 0x0000000004000000ULL, |
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/* PowerPC 2.03 SPE double-precision floating-point extension */ |
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PPC_SPE_DOUBLE = 0x0000000008000000ULL, |
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|
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/* Optional memory control instructions */ |
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PPC_MEM_TLBIA = 0x0000000010000000ULL, |
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PPC_MEM_TLBIE = 0x0000000020000000ULL, |
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PPC_MEM_TLBSYNC = 0x0000000040000000ULL, |
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/* sync instruction */ |
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PPC_MEM_SYNC = 0x0000000080000000ULL, |
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533 |
/* eieio instruction */ |
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PPC_MEM_EIEIO = 0x0000000100000000ULL, |
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535 |
|
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/* Cache control instructions */ |
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PPC_CACHE = 0x0000000200000000ULL, |
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538 |
/* icbi instruction */ |
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PPC_CACHE_ICBI = 0x0000000400000000ULL, |
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540 |
/* dcbz instruction with fixed cache line size */ |
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PPC_CACHE_DCBZ = 0x0000000800000000ULL, |
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542 |
/* dcbz instruction with tunable cache line size */ |
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PPC_CACHE_DCBZT = 0x0000001000000000ULL, |
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/* dcba instruction */ |
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PPC_CACHE_DCBA = 0x0000002000000000ULL, |
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/* Freescale cache locking instructions */ |
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PPC_CACHE_LOCK = 0x0000004000000000ULL, |
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548 |
|
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/* MMU related extensions */ |
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/* external control instructions */ |
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PPC_EXTERN = 0x0000010000000000ULL, |
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/* segment register access instructions */ |
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PPC_SEGMENT = 0x0000020000000000ULL, |
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554 |
/* PowerPC 6xx TLB management instructions */ |
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PPC_6xx_TLB = 0x0000040000000000ULL, |
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556 |
/* PowerPC 74xx TLB management instructions */ |
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557 |
PPC_74xx_TLB = 0x0000080000000000ULL, |
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558 |
/* PowerPC 40x TLB management instructions */ |
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PPC_40x_TLB = 0x0000100000000000ULL, |
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/* segment register access instructions for PowerPC 64 "bridge" */ |
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PPC_SEGMENT_64B = 0x0000200000000000ULL, |
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/* SLB management */ |
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PPC_SLBI = 0x0000400000000000ULL, |
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/* Embedded PowerPC dedicated instructions */ |
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PPC_WRTEE = 0x0001000000000000ULL, |
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/* PowerPC 40x exception model */ |
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PPC_40x_EXCP = 0x0002000000000000ULL, |
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/* PowerPC 405 Mac instructions */ |
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PPC_405_MAC = 0x0004000000000000ULL, |
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/* PowerPC 440 specific instructions */ |
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PPC_440_SPEC = 0x0008000000000000ULL, |
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/* BookE (embedded) PowerPC specification */ |
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PPC_BOOKE = 0x0010000000000000ULL, |
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/* mfapidi instruction */ |
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PPC_MFAPIDI = 0x0020000000000000ULL, |
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/* tlbiva instruction */ |
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PPC_TLBIVA = 0x0040000000000000ULL, |
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579 |
/* tlbivax instruction */ |
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PPC_TLBIVAX = 0x0080000000000000ULL, |
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/* PowerPC 4xx dedicated instructions */ |
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PPC_4xx_COMMON = 0x0100000000000000ULL, |
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/* PowerPC 40x ibct instructions */ |
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PPC_40x_ICBT = 0x0200000000000000ULL, |
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/* rfmci is not implemented in all BookE PowerPC */ |
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PPC_RFMCI = 0x0400000000000000ULL, |
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/* rfdi instruction */ |
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PPC_RFDI = 0x0800000000000000ULL, |
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/* DCR accesses */ |
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PPC_DCR = 0x1000000000000000ULL, |
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/* DCR extended accesse */ |
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PPC_DCRX = 0x2000000000000000ULL, |
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/* user-mode DCR access, implemented in PowerPC 460 */ |
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PPC_DCRUX = 0x4000000000000000ULL, |
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}; |
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|
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/*****************************************************************************/ |
|
598 | 460 |
/* PowerPC instructions table */ |
599 | 461 |
#if HOST_LONG_BITS == 64 |
600 | 462 |
#define OPC_ALIGN 8 |
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