root / target-ppc / helper.c @ c3d420ea
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/*
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* PowerPC emulation helpers for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "helper_regs.h" |
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#include "qemu-common.h" |
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#include "kvm.h" |
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//#define DEBUG_MMU
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//#define DEBUG_BATS
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//#define DEBUG_SLB
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//#define DEBUG_SOFTWARE_TLB
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//#define DUMP_PAGE_TABLES
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//#define DEBUG_EXCEPTIONS
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//#define FLUSH_ALL_TLBS
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|
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#ifdef DEBUG_MMU
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# define LOG_MMU(...) qemu_log(__VA_ARGS__)
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# define LOG_MMU_STATE(env) log_cpu_state((env), 0) |
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#else
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# define LOG_MMU(...) do { } while (0) |
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# define LOG_MMU_STATE(...) do { } while (0) |
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#endif
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#ifdef DEBUG_SOFTWARE_TLB
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# define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
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#else
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# define LOG_SWTLB(...) do { } while (0) |
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#endif
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#ifdef DEBUG_BATS
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# define LOG_BATS(...) qemu_log(__VA_ARGS__)
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#else
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# define LOG_BATS(...) do { } while (0) |
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#endif
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#ifdef DEBUG_SLB
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# define LOG_SLB(...) qemu_log(__VA_ARGS__)
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#else
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# define LOG_SLB(...) do { } while (0) |
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#endif
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#ifdef DEBUG_EXCEPTIONS
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# define LOG_EXCP(...) qemu_log(__VA_ARGS__)
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#else
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# define LOG_EXCP(...) do { } while (0) |
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#endif
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/*****************************************************************************/
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/* PowerPC MMU emulation */
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#if defined(CONFIG_USER_ONLY)
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int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{
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int exception, error_code;
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if (rw == 2) { |
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exception = POWERPC_EXCP_ISI; |
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error_code = 0x40000000;
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} else {
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exception = POWERPC_EXCP_DSI; |
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error_code = 0x40000000;
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if (rw)
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error_code |= 0x02000000;
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env->spr[SPR_DAR] = address; |
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env->spr[SPR_DSISR] = error_code; |
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} |
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env->exception_index = exception; |
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env->error_code = error_code; |
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return 1; |
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} |
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#else
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/* Common routines used by software and hardware TLBs emulation */
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static inline int pte_is_valid(target_ulong pte0) |
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{
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return pte0 & 0x80000000 ? 1 : 0; |
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} |
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static inline void pte_invalidate(target_ulong *pte0) |
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{
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*pte0 &= ~0x80000000;
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} |
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#if defined(TARGET_PPC64)
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static inline int pte64_is_valid(target_ulong pte0) |
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{
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return pte0 & 0x0000000000000001ULL ? 1 : 0; |
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} |
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static inline void pte64_invalidate(target_ulong *pte0) |
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{
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*pte0 &= ~0x0000000000000001ULL;
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} |
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#endif
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#define PTE_PTEM_MASK 0x7FFFFFBF |
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#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) |
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#if defined(TARGET_PPC64)
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#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL |
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#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) |
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#endif
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static inline int pp_check(int key, int pp, int nx) |
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{
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int access;
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/* Compute access rights */
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/* When pp is 3/7, the result is undefined. Set it to noaccess */
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access = 0;
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if (key == 0) { |
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switch (pp) {
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case 0x0: |
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case 0x1: |
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case 0x2: |
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access |= PAGE_WRITE; |
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/* No break here */
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case 0x3: |
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case 0x6: |
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access |= PAGE_READ; |
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break;
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} |
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} else {
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switch (pp) {
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case 0x0: |
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case 0x6: |
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access = 0;
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break;
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case 0x1: |
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case 0x3: |
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access = PAGE_READ; |
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break;
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case 0x2: |
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access = PAGE_READ | PAGE_WRITE; |
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break;
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} |
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} |
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if (nx == 0) |
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access |= PAGE_EXEC; |
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return access;
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} |
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static inline int check_prot(int prot, int rw, int access_type) |
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{
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int ret;
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if (access_type == ACCESS_CODE) {
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if (prot & PAGE_EXEC)
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ret = 0;
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else
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ret = -2;
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} else if (rw) { |
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if (prot & PAGE_WRITE)
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ret = 0;
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else
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ret = -2;
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} else {
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if (prot & PAGE_READ)
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ret = 0;
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else
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ret = -2;
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} |
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return ret;
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} |
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static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0, |
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target_ulong pte1, int h, int rw, int type) |
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{
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target_ulong ptem, mmask; |
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int access, ret, pteh, ptev, pp;
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ret = -1;
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/* Check validity and table match */
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#if defined(TARGET_PPC64)
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if (is_64b) {
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ptev = pte64_is_valid(pte0); |
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pteh = (pte0 >> 1) & 1; |
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} else
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#endif
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{
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ptev = pte_is_valid(pte0); |
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pteh = (pte0 >> 6) & 1; |
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} |
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if (ptev && h == pteh) {
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/* Check vsid & api */
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#if defined(TARGET_PPC64)
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if (is_64b) {
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ptem = pte0 & PTE64_PTEM_MASK; |
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mmask = PTE64_CHECK_MASK; |
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pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004); |
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ctx->nx = (pte1 >> 2) & 1; /* No execute bit */ |
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ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */ |
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} else
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#endif
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{
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ptem = pte0 & PTE_PTEM_MASK; |
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mmask = PTE_CHECK_MASK; |
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pp = pte1 & 0x00000003;
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} |
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if (ptem == ctx->ptem) {
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if (ctx->raddr != (target_phys_addr_t)-1ULL) { |
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/* all matches should have equal RPN, WIMG & PP */
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if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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qemu_log("Bad RPN/WIMG/PP\n");
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return -3; |
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} |
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} |
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/* Compute access rights */
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access = pp_check(ctx->key, pp, ctx->nx); |
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/* Keep the matching PTE informations */
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ctx->raddr = pte1; |
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ctx->prot = access; |
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ret = check_prot(ctx->prot, rw, type); |
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if (ret == 0) { |
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/* Access granted */
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LOG_MMU("PTE access granted !\n");
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} else {
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/* Access right violation */
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LOG_MMU("PTE access rejected\n");
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} |
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} |
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} |
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return ret;
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} |
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static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0, |
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target_ulong pte1, int h, int rw, int type) |
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{
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return _pte_check(ctx, 0, pte0, pte1, h, rw, type); |
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} |
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#if defined(TARGET_PPC64)
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static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0, |
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target_ulong pte1, int h, int rw, int type) |
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{
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return _pte_check(ctx, 1, pte0, pte1, h, rw, type); |
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} |
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#endif
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static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p, |
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int ret, int rw) |
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{
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int store = 0; |
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/* Update page flags */
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if (!(*pte1p & 0x00000100)) { |
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/* Update accessed flag */
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*pte1p |= 0x00000100;
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store = 1;
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} |
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if (!(*pte1p & 0x00000080)) { |
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if (rw == 1 && ret == 0) { |
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/* Update changed flag */
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*pte1p |= 0x00000080;
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store = 1;
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} else {
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/* Force page fault for first write access */
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ctx->prot &= ~PAGE_WRITE; |
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} |
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} |
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return store;
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} |
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/* Software driven TLB helpers */
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static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way, |
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int is_code)
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{
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int nr;
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/* Select TLB num in a way from address */
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nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
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/* Select TLB way */
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nr += env->tlb_per_way * way; |
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/* 6xx have separate TLBs for instructions and data */
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if (is_code && env->id_tlbs == 1) |
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nr += env->nb_tlb; |
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return nr;
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} |
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static inline void ppc6xx_tlb_invalidate_all(CPUState *env) |
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{
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ppc6xx_tlb_t *tlb; |
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int nr, max;
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|
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//LOG_SWTLB("Invalidate all TLBs\n");
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/* Invalidate all defined software TLB */
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max = env->nb_tlb; |
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if (env->id_tlbs == 1) |
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max *= 2;
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for (nr = 0; nr < max; nr++) { |
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tlb = &env->tlb[nr].tlb6; |
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pte_invalidate(&tlb->pte0); |
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} |
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tlb_flush(env, 1);
|
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} |
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|
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static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env, |
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target_ulong eaddr, |
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int is_code, int match_epn) |
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{
|
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#if !defined(FLUSH_ALL_TLBS)
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ppc6xx_tlb_t *tlb; |
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int way, nr;
|
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|
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/* Invalidate ITLB + DTLB, all ways */
|
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for (way = 0; way < env->nb_ways; way++) { |
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nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); |
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tlb = &env->tlb[nr].tlb6; |
| 341 |
if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
| 342 |
LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr, |
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env->nb_tlb, eaddr); |
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pte_invalidate(&tlb->pte0); |
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tlb_flush_page(env, tlb->EPN); |
| 346 |
} |
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} |
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#else
|
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/* XXX: PowerPC specification say this is valid as well */
|
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ppc6xx_tlb_invalidate_all(env); |
| 351 |
#endif
|
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} |
| 353 |
|
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static inline void ppc6xx_tlb_invalidate_virt(CPUState *env, |
| 355 |
target_ulong eaddr, int is_code)
|
| 356 |
{
|
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__ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
|
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} |
| 359 |
|
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void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, |
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target_ulong pte0, target_ulong pte1) |
| 362 |
{
|
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ppc6xx_tlb_t *tlb; |
| 364 |
int nr;
|
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|
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nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); |
| 367 |
tlb = &env->tlb[nr].tlb6; |
| 368 |
LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx |
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" PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1); |
| 370 |
/* Invalidate any pending reference in Qemu for this virtual address */
|
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__ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
|
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tlb->pte0 = pte0; |
| 373 |
tlb->pte1 = pte1; |
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tlb->EPN = EPN; |
| 375 |
/* Store last way for LRU mechanism */
|
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env->last_way = way; |
| 377 |
} |
| 378 |
|
| 379 |
static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx, |
| 380 |
target_ulong eaddr, int rw, int access_type) |
| 381 |
{
|
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ppc6xx_tlb_t *tlb; |
| 383 |
int nr, best, way;
|
| 384 |
int ret;
|
| 385 |
|
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best = -1;
|
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ret = -1; /* No TLB found */ |
| 388 |
for (way = 0; way < env->nb_ways; way++) { |
| 389 |
nr = ppc6xx_tlb_getnum(env, eaddr, way, |
| 390 |
access_type == ACCESS_CODE ? 1 : 0); |
| 391 |
tlb = &env->tlb[nr].tlb6; |
| 392 |
/* This test "emulates" the PTE index match for hardware TLBs */
|
| 393 |
if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
|
| 394 |
LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx |
| 395 |
"] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb, |
| 396 |
pte_is_valid(tlb->pte0) ? "valid" : "inval", |
| 397 |
tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); |
| 398 |
continue;
|
| 399 |
} |
| 400 |
LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " " |
| 401 |
TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
|
| 402 |
pte_is_valid(tlb->pte0) ? "valid" : "inval", |
| 403 |
tlb->EPN, eaddr, tlb->pte1, |
| 404 |
rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); |
| 405 |
switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { |
| 406 |
case -3: |
| 407 |
/* TLB inconsistency */
|
| 408 |
return -1; |
| 409 |
case -2: |
| 410 |
/* Access violation */
|
| 411 |
ret = -2;
|
| 412 |
best = nr; |
| 413 |
break;
|
| 414 |
case -1: |
| 415 |
default:
|
| 416 |
/* No match */
|
| 417 |
break;
|
| 418 |
case 0: |
| 419 |
/* access granted */
|
| 420 |
/* XXX: we should go on looping to check all TLBs consistency
|
| 421 |
* but we can speed-up the whole thing as the
|
| 422 |
* result would be undefined if TLBs are not consistent.
|
| 423 |
*/
|
| 424 |
ret = 0;
|
| 425 |
best = nr; |
| 426 |
goto done;
|
| 427 |
} |
| 428 |
} |
| 429 |
if (best != -1) { |
| 430 |
done:
|
| 431 |
LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n", |
| 432 |
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); |
| 433 |
/* Update page flags */
|
| 434 |
pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
| 435 |
} |
| 436 |
|
| 437 |
return ret;
|
| 438 |
} |
| 439 |
|
| 440 |
/* Perform BAT hit & translation */
|
| 441 |
static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp, |
| 442 |
int *protp, target_ulong *BATu,
|
| 443 |
target_ulong *BATl) |
| 444 |
{
|
| 445 |
target_ulong bl; |
| 446 |
int pp, valid, prot;
|
| 447 |
|
| 448 |
bl = (*BATu & 0x00001FFC) << 15; |
| 449 |
valid = 0;
|
| 450 |
prot = 0;
|
| 451 |
if (((msr_pr == 0) && (*BATu & 0x00000002)) || |
| 452 |
((msr_pr != 0) && (*BATu & 0x00000001))) { |
| 453 |
valid = 1;
|
| 454 |
pp = *BATl & 0x00000003;
|
| 455 |
if (pp != 0) { |
| 456 |
prot = PAGE_READ | PAGE_EXEC; |
| 457 |
if (pp == 0x2) |
| 458 |
prot |= PAGE_WRITE; |
| 459 |
} |
| 460 |
} |
| 461 |
*blp = bl; |
| 462 |
*validp = valid; |
| 463 |
*protp = prot; |
| 464 |
} |
| 465 |
|
| 466 |
static inline void bat_601_size_prot(CPUState *env, target_ulong *blp, |
| 467 |
int *validp, int *protp, |
| 468 |
target_ulong *BATu, target_ulong *BATl) |
| 469 |
{
|
| 470 |
target_ulong bl; |
| 471 |
int key, pp, valid, prot;
|
| 472 |
|
| 473 |
bl = (*BATl & 0x0000003F) << 17; |
| 474 |
LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n", |
| 475 |
(uint8_t)(*BATl & 0x0000003F), bl, ~bl);
|
| 476 |
prot = 0;
|
| 477 |
valid = (*BATl >> 6) & 1; |
| 478 |
if (valid) {
|
| 479 |
pp = *BATu & 0x00000003;
|
| 480 |
if (msr_pr == 0) |
| 481 |
key = (*BATu >> 3) & 1; |
| 482 |
else
|
| 483 |
key = (*BATu >> 2) & 1; |
| 484 |
prot = pp_check(key, pp, 0);
|
| 485 |
} |
| 486 |
*blp = bl; |
| 487 |
*validp = valid; |
| 488 |
*protp = prot; |
| 489 |
} |
| 490 |
|
| 491 |
static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual, |
| 492 |
int rw, int type) |
| 493 |
{
|
| 494 |
target_ulong *BATlt, *BATut, *BATu, *BATl; |
| 495 |
target_ulong BEPIl, BEPIu, bl; |
| 496 |
int i, valid, prot;
|
| 497 |
int ret = -1; |
| 498 |
|
| 499 |
LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__, |
| 500 |
type == ACCESS_CODE ? 'I' : 'D', virtual); |
| 501 |
switch (type) {
|
| 502 |
case ACCESS_CODE:
|
| 503 |
BATlt = env->IBAT[1];
|
| 504 |
BATut = env->IBAT[0];
|
| 505 |
break;
|
| 506 |
default:
|
| 507 |
BATlt = env->DBAT[1];
|
| 508 |
BATut = env->DBAT[0];
|
| 509 |
break;
|
| 510 |
} |
| 511 |
for (i = 0; i < env->nb_BATs; i++) { |
| 512 |
BATu = &BATut[i]; |
| 513 |
BATl = &BATlt[i]; |
| 514 |
BEPIu = *BATu & 0xF0000000;
|
| 515 |
BEPIl = *BATu & 0x0FFE0000;
|
| 516 |
if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
|
| 517 |
bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl); |
| 518 |
} else {
|
| 519 |
bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); |
| 520 |
} |
| 521 |
LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx |
| 522 |
" BATl " TARGET_FMT_lx "\n", __func__, |
| 523 |
type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl); |
| 524 |
if ((virtual & 0xF0000000) == BEPIu && |
| 525 |
((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
|
| 526 |
/* BAT matches */
|
| 527 |
if (valid != 0) { |
| 528 |
/* Get physical address */
|
| 529 |
ctx->raddr = (*BATl & 0xF0000000) |
|
| 530 |
((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
| 531 |
(virtual & 0x0001F000);
|
| 532 |
/* Compute access rights */
|
| 533 |
ctx->prot = prot; |
| 534 |
ret = check_prot(ctx->prot, rw, type); |
| 535 |
if (ret == 0) |
| 536 |
LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n", |
| 537 |
i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
| 538 |
ctx->prot & PAGE_WRITE ? 'W' : '-'); |
| 539 |
break;
|
| 540 |
} |
| 541 |
} |
| 542 |
} |
| 543 |
if (ret < 0) { |
| 544 |
#if defined(DEBUG_BATS)
|
| 545 |
if (qemu_log_enabled()) {
|
| 546 |
LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual); |
| 547 |
for (i = 0; i < 4; i++) { |
| 548 |
BATu = &BATut[i]; |
| 549 |
BATl = &BATlt[i]; |
| 550 |
BEPIu = *BATu & 0xF0000000;
|
| 551 |
BEPIl = *BATu & 0x0FFE0000;
|
| 552 |
bl = (*BATu & 0x00001FFC) << 15; |
| 553 |
LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx |
| 554 |
" BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " " |
| 555 |
TARGET_FMT_lx " " TARGET_FMT_lx "\n", |
| 556 |
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
| 557 |
*BATu, *BATl, BEPIu, BEPIl, bl); |
| 558 |
} |
| 559 |
} |
| 560 |
#endif
|
| 561 |
} |
| 562 |
/* No hit */
|
| 563 |
return ret;
|
| 564 |
} |
| 565 |
|
| 566 |
/* PTE table lookup */
|
| 567 |
static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw, |
| 568 |
int type, int target_page_bits) |
| 569 |
{
|
| 570 |
target_ulong base, pte0, pte1; |
| 571 |
int i, good = -1; |
| 572 |
int ret, r;
|
| 573 |
|
| 574 |
ret = -1; /* No entry found */ |
| 575 |
base = ctx->pg_addr[h]; |
| 576 |
for (i = 0; i < 8; i++) { |
| 577 |
#if defined(TARGET_PPC64)
|
| 578 |
if (is_64b) {
|
| 579 |
pte0 = ldq_phys(base + (i * 16));
|
| 580 |
pte1 = ldq_phys(base + (i * 16) + 8); |
| 581 |
|
| 582 |
/* We have a TLB that saves 4K pages, so let's
|
| 583 |
* split a huge page to 4k chunks */
|
| 584 |
if (target_page_bits != TARGET_PAGE_BITS)
|
| 585 |
pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1)) |
| 586 |
& TARGET_PAGE_MASK; |
| 587 |
|
| 588 |
r = pte64_check(ctx, pte0, pte1, h, rw, type); |
| 589 |
LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " |
| 590 |
TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", |
| 591 |
base + (i * 16), pte0, pte1, (int)(pte0 & 1), h, |
| 592 |
(int)((pte0 >> 1) & 1), ctx->ptem); |
| 593 |
} else
|
| 594 |
#endif
|
| 595 |
{
|
| 596 |
pte0 = ldl_phys(base + (i * 8));
|
| 597 |
pte1 = ldl_phys(base + (i * 8) + 4); |
| 598 |
r = pte32_check(ctx, pte0, pte1, h, rw, type); |
| 599 |
LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " |
| 600 |
TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", |
| 601 |
base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h, |
| 602 |
(int)((pte0 >> 6) & 1), ctx->ptem); |
| 603 |
} |
| 604 |
switch (r) {
|
| 605 |
case -3: |
| 606 |
/* PTE inconsistency */
|
| 607 |
return -1; |
| 608 |
case -2: |
| 609 |
/* Access violation */
|
| 610 |
ret = -2;
|
| 611 |
good = i; |
| 612 |
break;
|
| 613 |
case -1: |
| 614 |
default:
|
| 615 |
/* No PTE match */
|
| 616 |
break;
|
| 617 |
case 0: |
| 618 |
/* access granted */
|
| 619 |
/* XXX: we should go on looping to check all PTEs consistency
|
| 620 |
* but if we can speed-up the whole thing as the
|
| 621 |
* result would be undefined if PTEs are not consistent.
|
| 622 |
*/
|
| 623 |
ret = 0;
|
| 624 |
good = i; |
| 625 |
goto done;
|
| 626 |
} |
| 627 |
} |
| 628 |
if (good != -1) { |
| 629 |
done:
|
| 630 |
LOG_MMU("found PTE at addr " TARGET_FMT_lx " prot=%01x ret=%d\n", |
| 631 |
ctx->raddr, ctx->prot, ret); |
| 632 |
/* Update page flags */
|
| 633 |
pte1 = ctx->raddr; |
| 634 |
if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
| 635 |
#if defined(TARGET_PPC64)
|
| 636 |
if (is_64b) {
|
| 637 |
stq_phys_notdirty(base + (good * 16) + 8, pte1); |
| 638 |
} else
|
| 639 |
#endif
|
| 640 |
{
|
| 641 |
stl_phys_notdirty(base + (good * 8) + 4, pte1); |
| 642 |
} |
| 643 |
} |
| 644 |
} |
| 645 |
|
| 646 |
return ret;
|
| 647 |
} |
| 648 |
|
| 649 |
static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type, |
| 650 |
int target_page_bits)
|
| 651 |
{
|
| 652 |
return _find_pte(ctx, 0, h, rw, type, target_page_bits); |
| 653 |
} |
| 654 |
|
| 655 |
#if defined(TARGET_PPC64)
|
| 656 |
static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type, |
| 657 |
int target_page_bits)
|
| 658 |
{
|
| 659 |
return _find_pte(ctx, 1, h, rw, type, target_page_bits); |
| 660 |
} |
| 661 |
#endif
|
| 662 |
|
| 663 |
static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw, |
| 664 |
int type, int target_page_bits) |
| 665 |
{
|
| 666 |
#if defined(TARGET_PPC64)
|
| 667 |
if (env->mmu_model & POWERPC_MMU_64)
|
| 668 |
return find_pte64(ctx, h, rw, type, target_page_bits);
|
| 669 |
#endif
|
| 670 |
|
| 671 |
return find_pte32(ctx, h, rw, type, target_page_bits);
|
| 672 |
} |
| 673 |
|
| 674 |
#if defined(TARGET_PPC64)
|
| 675 |
static ppc_slb_t *slb_get_entry(CPUPPCState *env, int nr) |
| 676 |
{
|
| 677 |
ppc_slb_t *retval = &env->slb[nr]; |
| 678 |
|
| 679 |
#if 0 // XXX implement bridge mode?
|
| 680 |
if (env->spr[SPR_ASR] & 1) {
|
| 681 |
target_phys_addr_t sr_base;
|
| 682 |
|
| 683 |
sr_base = env->spr[SPR_ASR] & 0xfffffffffffff000;
|
| 684 |
sr_base += (12 * nr);
|
| 685 |
|
| 686 |
retval->tmp64 = ldq_phys(sr_base);
|
| 687 |
retval->tmp = ldl_phys(sr_base + 8);
|
| 688 |
}
|
| 689 |
#endif
|
| 690 |
|
| 691 |
return retval;
|
| 692 |
} |
| 693 |
|
| 694 |
static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb) |
| 695 |
{
|
| 696 |
ppc_slb_t *entry = &env->slb[nr]; |
| 697 |
|
| 698 |
if (slb == entry)
|
| 699 |
return;
|
| 700 |
|
| 701 |
entry->tmp64 = slb->tmp64; |
| 702 |
entry->tmp = slb->tmp; |
| 703 |
} |
| 704 |
|
| 705 |
static inline int slb_is_valid(ppc_slb_t *slb) |
| 706 |
{
|
| 707 |
return (int)(slb->tmp64 & 0x0000000008000000ULL); |
| 708 |
} |
| 709 |
|
| 710 |
static inline void slb_invalidate(ppc_slb_t *slb) |
| 711 |
{
|
| 712 |
slb->tmp64 &= ~0x0000000008000000ULL;
|
| 713 |
} |
| 714 |
|
| 715 |
static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr, |
| 716 |
target_ulong *vsid, target_ulong *page_mask, |
| 717 |
int *attr, int *target_page_bits) |
| 718 |
{
|
| 719 |
target_ulong mask; |
| 720 |
int n, ret;
|
| 721 |
|
| 722 |
ret = -5;
|
| 723 |
LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); |
| 724 |
mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
| 725 |
for (n = 0; n < env->slb_nr; n++) { |
| 726 |
ppc_slb_t *slb = slb_get_entry(env, n); |
| 727 |
|
| 728 |
LOG_SLB("%s: seg %d %016" PRIx64 " %08" |
| 729 |
PRIx32 "\n", __func__, n, slb->tmp64, slb->tmp);
|
| 730 |
if (slb_is_valid(slb)) {
|
| 731 |
/* SLB entry is valid */
|
| 732 |
mask = 0xFFFFFFFFF0000000ULL;
|
| 733 |
if (slb->tmp & 0x8) { |
| 734 |
/* 16 MB PTEs */
|
| 735 |
if (target_page_bits)
|
| 736 |
*target_page_bits = 24;
|
| 737 |
} else {
|
| 738 |
/* 4 KB PTEs */
|
| 739 |
if (target_page_bits)
|
| 740 |
*target_page_bits = TARGET_PAGE_BITS; |
| 741 |
} |
| 742 |
if ((eaddr & mask) == (slb->tmp64 & mask)) {
|
| 743 |
/* SLB match */
|
| 744 |
*vsid = ((slb->tmp64 << 24) | (slb->tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
| 745 |
*page_mask = ~mask; |
| 746 |
*attr = slb->tmp & 0xFF;
|
| 747 |
ret = n; |
| 748 |
break;
|
| 749 |
} |
| 750 |
} |
| 751 |
} |
| 752 |
|
| 753 |
return ret;
|
| 754 |
} |
| 755 |
|
| 756 |
void ppc_slb_invalidate_all (CPUPPCState *env)
|
| 757 |
{
|
| 758 |
int n, do_invalidate;
|
| 759 |
|
| 760 |
do_invalidate = 0;
|
| 761 |
/* XXX: Warning: slbia never invalidates the first segment */
|
| 762 |
for (n = 1; n < env->slb_nr; n++) { |
| 763 |
ppc_slb_t *slb = slb_get_entry(env, n); |
| 764 |
|
| 765 |
if (slb_is_valid(slb)) {
|
| 766 |
slb_invalidate(slb); |
| 767 |
slb_set_entry(env, n, slb); |
| 768 |
/* XXX: given the fact that segment size is 256 MB or 1TB,
|
| 769 |
* and we still don't have a tlb_flush_mask(env, n, mask)
|
| 770 |
* in Qemu, we just invalidate all TLBs
|
| 771 |
*/
|
| 772 |
do_invalidate = 1;
|
| 773 |
} |
| 774 |
} |
| 775 |
if (do_invalidate)
|
| 776 |
tlb_flush(env, 1);
|
| 777 |
} |
| 778 |
|
| 779 |
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
|
| 780 |
{
|
| 781 |
target_ulong vsid, page_mask; |
| 782 |
int attr;
|
| 783 |
int n;
|
| 784 |
|
| 785 |
n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL);
|
| 786 |
if (n >= 0) { |
| 787 |
ppc_slb_t *slb = slb_get_entry(env, n); |
| 788 |
|
| 789 |
if (slb_is_valid(slb)) {
|
| 790 |
slb_invalidate(slb); |
| 791 |
slb_set_entry(env, n, slb); |
| 792 |
/* XXX: given the fact that segment size is 256 MB or 1TB,
|
| 793 |
* and we still don't have a tlb_flush_mask(env, n, mask)
|
| 794 |
* in Qemu, we just invalidate all TLBs
|
| 795 |
*/
|
| 796 |
tlb_flush(env, 1);
|
| 797 |
} |
| 798 |
} |
| 799 |
} |
| 800 |
|
| 801 |
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
|
| 802 |
{
|
| 803 |
target_ulong rt; |
| 804 |
ppc_slb_t *slb = slb_get_entry(env, slb_nr); |
| 805 |
|
| 806 |
if (slb_is_valid(slb)) {
|
| 807 |
/* SLB entry is valid */
|
| 808 |
/* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
|
| 809 |
rt = slb->tmp >> 8; /* 65:88 => 40:63 */ |
| 810 |
rt |= (slb->tmp64 & 0x7) << 24; /* 62:64 => 37:39 */ |
| 811 |
/* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
|
| 812 |
rt |= ((slb->tmp >> 4) & 0xF) << 27; |
| 813 |
} else {
|
| 814 |
rt = 0;
|
| 815 |
} |
| 816 |
LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d " |
| 817 |
TARGET_FMT_lx "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
|
| 818 |
|
| 819 |
return rt;
|
| 820 |
} |
| 821 |
|
| 822 |
void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
|
| 823 |
{
|
| 824 |
ppc_slb_t *slb; |
| 825 |
|
| 826 |
uint64_t vsid; |
| 827 |
uint64_t esid; |
| 828 |
int flags, valid, slb_nr;
|
| 829 |
|
| 830 |
vsid = rs >> 12;
|
| 831 |
flags = ((rs >> 8) & 0xf); |
| 832 |
|
| 833 |
esid = rb >> 28;
|
| 834 |
valid = (rb & (1 << 27)); |
| 835 |
slb_nr = rb & 0xfff;
|
| 836 |
|
| 837 |
slb = slb_get_entry(env, slb_nr); |
| 838 |
slb->tmp64 = (esid << 28) | valid | (vsid >> 24); |
| 839 |
slb->tmp = (vsid << 8) | (flags << 3); |
| 840 |
|
| 841 |
LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64 |
| 842 |
" %08" PRIx32 "\n", __func__, slb_nr, rb, rs, slb->tmp64, |
| 843 |
slb->tmp); |
| 844 |
|
| 845 |
slb_set_entry(env, slb_nr, slb); |
| 846 |
} |
| 847 |
#endif /* defined(TARGET_PPC64) */ |
| 848 |
|
| 849 |
/* Perform segment based translation */
|
| 850 |
static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1, |
| 851 |
int sdr_sh,
|
| 852 |
target_phys_addr_t hash, |
| 853 |
target_phys_addr_t mask) |
| 854 |
{
|
| 855 |
return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask); |
| 856 |
} |
| 857 |
|
| 858 |
static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, |
| 859 |
target_ulong eaddr, int rw, int type) |
| 860 |
{
|
| 861 |
target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask; |
| 862 |
target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
| 863 |
#if defined(TARGET_PPC64)
|
| 864 |
int attr;
|
| 865 |
#endif
|
| 866 |
int ds, vsid_sh, sdr_sh, pr, target_page_bits;
|
| 867 |
int ret, ret2;
|
| 868 |
|
| 869 |
pr = msr_pr; |
| 870 |
#if defined(TARGET_PPC64)
|
| 871 |
if (env->mmu_model & POWERPC_MMU_64) {
|
| 872 |
LOG_MMU("Check SLBs\n");
|
| 873 |
ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr, |
| 874 |
&target_page_bits); |
| 875 |
if (ret < 0) |
| 876 |
return ret;
|
| 877 |
ctx->key = ((attr & 0x40) && (pr != 0)) || |
| 878 |
((attr & 0x80) && (pr == 0)) ? 1 : 0; |
| 879 |
ds = 0;
|
| 880 |
ctx->nx = attr & 0x10 ? 1 : 0; |
| 881 |
ctx->eaddr = eaddr; |
| 882 |
vsid_mask = 0x00003FFFFFFFFF80ULL;
|
| 883 |
vsid_sh = 7;
|
| 884 |
sdr_sh = 18;
|
| 885 |
sdr_mask = 0x3FF80;
|
| 886 |
} else
|
| 887 |
#endif /* defined(TARGET_PPC64) */ |
| 888 |
{
|
| 889 |
sr = env->sr[eaddr >> 28];
|
| 890 |
page_mask = 0x0FFFFFFF;
|
| 891 |
ctx->key = (((sr & 0x20000000) && (pr != 0)) || |
| 892 |
((sr & 0x40000000) && (pr == 0))) ? 1 : 0; |
| 893 |
ds = sr & 0x80000000 ? 1 : 0; |
| 894 |
ctx->nx = sr & 0x10000000 ? 1 : 0; |
| 895 |
vsid = sr & 0x00FFFFFF;
|
| 896 |
vsid_mask = 0x01FFFFC0;
|
| 897 |
vsid_sh = 6;
|
| 898 |
sdr_sh = 16;
|
| 899 |
sdr_mask = 0xFFC0;
|
| 900 |
target_page_bits = TARGET_PAGE_BITS; |
| 901 |
LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip=" |
| 902 |
TARGET_FMT_lx " lr=" TARGET_FMT_lx
|
| 903 |
" ir=%d dr=%d pr=%d %d t=%d\n",
|
| 904 |
eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, |
| 905 |
(int)msr_dr, pr != 0 ? 1 : 0, rw, type); |
| 906 |
} |
| 907 |
LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n", |
| 908 |
ctx->key, ds, ctx->nx, vsid); |
| 909 |
ret = -1;
|
| 910 |
if (!ds) {
|
| 911 |
/* Check if instruction fetch is allowed, if needed */
|
| 912 |
if (type != ACCESS_CODE || ctx->nx == 0) { |
| 913 |
/* Page address translation */
|
| 914 |
/* Primary table address */
|
| 915 |
sdr = env->sdr1; |
| 916 |
pgidx = (eaddr & page_mask) >> target_page_bits; |
| 917 |
#if defined(TARGET_PPC64)
|
| 918 |
if (env->mmu_model & POWERPC_MMU_64) {
|
| 919 |
htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); |
| 920 |
/* XXX: this is false for 1 TB segments */
|
| 921 |
hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
| 922 |
} else
|
| 923 |
#endif
|
| 924 |
{
|
| 925 |
htab_mask = sdr & 0x000001FF;
|
| 926 |
hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; |
| 927 |
} |
| 928 |
mask = (htab_mask << sdr_sh) | sdr_mask; |
| 929 |
LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx |
| 930 |
" mask " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
| 931 |
sdr, sdr_sh, hash, mask, page_mask); |
| 932 |
ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
| 933 |
/* Secondary table address */
|
| 934 |
hash = (~hash) & vsid_mask; |
| 935 |
LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx |
| 936 |
" mask " TARGET_FMT_plx "\n", sdr, sdr_sh, hash, mask); |
| 937 |
ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
|
| 938 |
#if defined(TARGET_PPC64)
|
| 939 |
if (env->mmu_model & POWERPC_MMU_64) {
|
| 940 |
/* Only 5 bits of the page index are used in the AVPN */
|
| 941 |
if (target_page_bits > 23) { |
| 942 |
ctx->ptem = (vsid << 12) |
|
| 943 |
((pgidx << (target_page_bits - 16)) & 0xF80); |
| 944 |
} else {
|
| 945 |
ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); |
| 946 |
} |
| 947 |
} else
|
| 948 |
#endif
|
| 949 |
{
|
| 950 |
ctx->ptem = (vsid << 7) | (pgidx >> 10); |
| 951 |
} |
| 952 |
/* Initialize real address with an invalid value */
|
| 953 |
ctx->raddr = (target_phys_addr_t)-1ULL;
|
| 954 |
if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
|
| 955 |
env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
|
| 956 |
/* Software TLB search */
|
| 957 |
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); |
| 958 |
} else {
|
| 959 |
LOG_MMU("0 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " " |
| 960 |
"api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx |
| 961 |
" pg_addr=" TARGET_FMT_plx "\n", |
| 962 |
sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
|
| 963 |
/* Primary table lookup */
|
| 964 |
ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
|
| 965 |
if (ret < 0) { |
| 966 |
/* Secondary table lookup */
|
| 967 |
if (eaddr != 0xEFFFFFFF) |
| 968 |
LOG_MMU("1 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " " |
| 969 |
"api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx |
| 970 |
" pg_addr=" TARGET_FMT_plx "\n", sdr, vsid, |
| 971 |
pgidx, hash, ctx->pg_addr[1]);
|
| 972 |
ret2 = find_pte(env, ctx, 1, rw, type,
|
| 973 |
target_page_bits); |
| 974 |
if (ret2 != -1) |
| 975 |
ret = ret2; |
| 976 |
} |
| 977 |
} |
| 978 |
#if defined (DUMP_PAGE_TABLES)
|
| 979 |
if (qemu_log_enabled()) {
|
| 980 |
target_phys_addr_t curaddr; |
| 981 |
uint32_t a0, a1, a2, a3; |
| 982 |
qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx |
| 983 |
"\n", sdr, mask + 0x80); |
| 984 |
for (curaddr = sdr; curaddr < (sdr + mask + 0x80); |
| 985 |
curaddr += 16) {
|
| 986 |
a0 = ldl_phys(curaddr); |
| 987 |
a1 = ldl_phys(curaddr + 4);
|
| 988 |
a2 = ldl_phys(curaddr + 8);
|
| 989 |
a3 = ldl_phys(curaddr + 12);
|
| 990 |
if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { |
| 991 |
qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
|
| 992 |
curaddr, a0, a1, a2, a3); |
| 993 |
} |
| 994 |
} |
| 995 |
} |
| 996 |
#endif
|
| 997 |
} else {
|
| 998 |
LOG_MMU("No access allowed\n");
|
| 999 |
ret = -3;
|
| 1000 |
} |
| 1001 |
} else {
|
| 1002 |
LOG_MMU("direct store...\n");
|
| 1003 |
/* Direct-store segment : absolutely *BUGGY* for now */
|
| 1004 |
switch (type) {
|
| 1005 |
case ACCESS_INT:
|
| 1006 |
/* Integer load/store : only access allowed */
|
| 1007 |
break;
|
| 1008 |
case ACCESS_CODE:
|
| 1009 |
/* No code fetch is allowed in direct-store areas */
|
| 1010 |
return -4; |
| 1011 |
case ACCESS_FLOAT:
|
| 1012 |
/* Floating point load/store */
|
| 1013 |
return -4; |
| 1014 |
case ACCESS_RES:
|
| 1015 |
/* lwarx, ldarx or srwcx. */
|
| 1016 |
return -4; |
| 1017 |
case ACCESS_CACHE:
|
| 1018 |
/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
|
| 1019 |
/* Should make the instruction do no-op.
|
| 1020 |
* As it already do no-op, it's quite easy :-)
|
| 1021 |
*/
|
| 1022 |
ctx->raddr = eaddr; |
| 1023 |
return 0; |
| 1024 |
case ACCESS_EXT:
|
| 1025 |
/* eciwx or ecowx */
|
| 1026 |
return -4; |
| 1027 |
default:
|
| 1028 |
qemu_log("ERROR: instruction should not need "
|
| 1029 |
"address translation\n");
|
| 1030 |
return -4; |
| 1031 |
} |
| 1032 |
if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
| 1033 |
ctx->raddr = eaddr; |
| 1034 |
ret = 2;
|
| 1035 |
} else {
|
| 1036 |
ret = -2;
|
| 1037 |
} |
| 1038 |
} |
| 1039 |
|
| 1040 |
return ret;
|
| 1041 |
} |
| 1042 |
|
| 1043 |
/* Generic TLB check function for embedded PowerPC implementations */
|
| 1044 |
static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb, |
| 1045 |
target_phys_addr_t *raddrp, |
| 1046 |
target_ulong address, uint32_t pid, int ext,
|
| 1047 |
int i)
|
| 1048 |
{
|
| 1049 |
target_ulong mask; |
| 1050 |
|
| 1051 |
/* Check valid flag */
|
| 1052 |
if (!(tlb->prot & PAGE_VALID)) {
|
| 1053 |
qemu_log("%s: TLB %d not valid\n", __func__, i);
|
| 1054 |
return -1; |
| 1055 |
} |
| 1056 |
mask = ~(tlb->size - 1);
|
| 1057 |
LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx |
| 1058 |
" " TARGET_FMT_lx " %u\n", __func__, i, address, pid, tlb->EPN, |
| 1059 |
mask, (uint32_t)tlb->PID); |
| 1060 |
/* Check PID */
|
| 1061 |
if (tlb->PID != 0 && tlb->PID != pid) |
| 1062 |
return -1; |
| 1063 |
/* Check effective address */
|
| 1064 |
if ((address & mask) != tlb->EPN)
|
| 1065 |
return -1; |
| 1066 |
*raddrp = (tlb->RPN & mask) | (address & ~mask); |
| 1067 |
#if (TARGET_PHYS_ADDR_BITS >= 36) |
| 1068 |
if (ext) {
|
| 1069 |
/* Extend the physical address to 36 bits */
|
| 1070 |
*raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32; |
| 1071 |
} |
| 1072 |
#endif
|
| 1073 |
|
| 1074 |
return 0; |
| 1075 |
} |
| 1076 |
|
| 1077 |
/* Generic TLB search function for PowerPC embedded implementations */
|
| 1078 |
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
|
| 1079 |
{
|
| 1080 |
ppcemb_tlb_t *tlb; |
| 1081 |
target_phys_addr_t raddr; |
| 1082 |
int i, ret;
|
| 1083 |
|
| 1084 |
/* Default return value is no match */
|
| 1085 |
ret = -1;
|
| 1086 |
for (i = 0; i < env->nb_tlb; i++) { |
| 1087 |
tlb = &env->tlb[i].tlbe; |
| 1088 |
if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
| 1089 |
ret = i; |
| 1090 |
break;
|
| 1091 |
} |
| 1092 |
} |
| 1093 |
|
| 1094 |
return ret;
|
| 1095 |
} |
| 1096 |
|
| 1097 |
/* Helpers specific to PowerPC 40x implementations */
|
| 1098 |
static inline void ppc4xx_tlb_invalidate_all(CPUState *env) |
| 1099 |
{
|
| 1100 |
ppcemb_tlb_t *tlb; |
| 1101 |
int i;
|
| 1102 |
|
| 1103 |
for (i = 0; i < env->nb_tlb; i++) { |
| 1104 |
tlb = &env->tlb[i].tlbe; |
| 1105 |
tlb->prot &= ~PAGE_VALID; |
| 1106 |
} |
| 1107 |
tlb_flush(env, 1);
|
| 1108 |
} |
| 1109 |
|
| 1110 |
static inline void ppc4xx_tlb_invalidate_virt(CPUState *env, |
| 1111 |
target_ulong eaddr, uint32_t pid) |
| 1112 |
{
|
| 1113 |
#if !defined(FLUSH_ALL_TLBS)
|
| 1114 |
ppcemb_tlb_t *tlb; |
| 1115 |
target_phys_addr_t raddr; |
| 1116 |
target_ulong page, end; |
| 1117 |
int i;
|
| 1118 |
|
| 1119 |
for (i = 0; i < env->nb_tlb; i++) { |
| 1120 |
tlb = &env->tlb[i].tlbe; |
| 1121 |
if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
| 1122 |
end = tlb->EPN + tlb->size; |
| 1123 |
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
|
| 1124 |
tlb_flush_page(env, page); |
| 1125 |
tlb->prot &= ~PAGE_VALID; |
| 1126 |
break;
|
| 1127 |
} |
| 1128 |
} |
| 1129 |
#else
|
| 1130 |
ppc4xx_tlb_invalidate_all(env); |
| 1131 |
#endif
|
| 1132 |
} |
| 1133 |
|
| 1134 |
static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
| 1135 |
target_ulong address, int rw, int access_type) |
| 1136 |
{
|
| 1137 |
ppcemb_tlb_t *tlb; |
| 1138 |
target_phys_addr_t raddr; |
| 1139 |
int i, ret, zsel, zpr, pr;
|
| 1140 |
|
| 1141 |
ret = -1;
|
| 1142 |
raddr = (target_phys_addr_t)-1ULL;
|
| 1143 |
pr = msr_pr; |
| 1144 |
for (i = 0; i < env->nb_tlb; i++) { |
| 1145 |
tlb = &env->tlb[i].tlbe; |
| 1146 |
if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
| 1147 |
env->spr[SPR_40x_PID], 0, i) < 0) |
| 1148 |
continue;
|
| 1149 |
zsel = (tlb->attr >> 4) & 0xF; |
| 1150 |
zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3; |
| 1151 |
LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
|
| 1152 |
__func__, i, zsel, zpr, rw, tlb->attr); |
| 1153 |
/* Check execute enable bit */
|
| 1154 |
switch (zpr) {
|
| 1155 |
case 0x2: |
| 1156 |
if (pr != 0) |
| 1157 |
goto check_perms;
|
| 1158 |
/* No break here */
|
| 1159 |
case 0x3: |
| 1160 |
/* All accesses granted */
|
| 1161 |
ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 1162 |
ret = 0;
|
| 1163 |
break;
|
| 1164 |
case 0x0: |
| 1165 |
if (pr != 0) { |
| 1166 |
/* Raise Zone protection fault. */
|
| 1167 |
env->spr[SPR_40x_ESR] = 1 << 22; |
| 1168 |
ctx->prot = 0;
|
| 1169 |
ret = -2;
|
| 1170 |
break;
|
| 1171 |
} |
| 1172 |
/* No break here */
|
| 1173 |
case 0x1: |
| 1174 |
check_perms:
|
| 1175 |
/* Check from TLB entry */
|
| 1176 |
/* XXX: there is a problem here or in the TLB fill code... */
|
| 1177 |
ctx->prot = tlb->prot; |
| 1178 |
ctx->prot |= PAGE_EXEC; |
| 1179 |
ret = check_prot(ctx->prot, rw, access_type); |
| 1180 |
if (ret == -2) |
| 1181 |
env->spr[SPR_40x_ESR] = 0;
|
| 1182 |
break;
|
| 1183 |
} |
| 1184 |
if (ret >= 0) { |
| 1185 |
ctx->raddr = raddr; |
| 1186 |
LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx |
| 1187 |
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
| 1188 |
ret); |
| 1189 |
return 0; |
| 1190 |
} |
| 1191 |
} |
| 1192 |
LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx |
| 1193 |
" %d %d\n", __func__, address, raddr, ctx->prot, ret);
|
| 1194 |
|
| 1195 |
return ret;
|
| 1196 |
} |
| 1197 |
|
| 1198 |
void store_40x_sler (CPUPPCState *env, uint32_t val)
|
| 1199 |
{
|
| 1200 |
/* XXX: TO BE FIXED */
|
| 1201 |
if (val != 0x00000000) { |
| 1202 |
cpu_abort(env, "Little-endian regions are not supported by now\n");
|
| 1203 |
} |
| 1204 |
env->spr[SPR_405_SLER] = val; |
| 1205 |
} |
| 1206 |
|
| 1207 |
static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx, |
| 1208 |
target_ulong address, int rw,
|
| 1209 |
int access_type)
|
| 1210 |
{
|
| 1211 |
ppcemb_tlb_t *tlb; |
| 1212 |
target_phys_addr_t raddr; |
| 1213 |
int i, prot, ret;
|
| 1214 |
|
| 1215 |
ret = -1;
|
| 1216 |
raddr = (target_phys_addr_t)-1ULL;
|
| 1217 |
for (i = 0; i < env->nb_tlb; i++) { |
| 1218 |
tlb = &env->tlb[i].tlbe; |
| 1219 |
if (ppcemb_tlb_check(env, tlb, &raddr, address,
|
| 1220 |
env->spr[SPR_BOOKE_PID], 1, i) < 0) |
| 1221 |
continue;
|
| 1222 |
if (msr_pr != 0) |
| 1223 |
prot = tlb->prot & 0xF;
|
| 1224 |
else
|
| 1225 |
prot = (tlb->prot >> 4) & 0xF; |
| 1226 |
/* Check the address space */
|
| 1227 |
if (access_type == ACCESS_CODE) {
|
| 1228 |
if (msr_ir != (tlb->attr & 1)) |
| 1229 |
continue;
|
| 1230 |
ctx->prot = prot; |
| 1231 |
if (prot & PAGE_EXEC) {
|
| 1232 |
ret = 0;
|
| 1233 |
break;
|
| 1234 |
} |
| 1235 |
ret = -3;
|
| 1236 |
} else {
|
| 1237 |
if (msr_dr != (tlb->attr & 1)) |
| 1238 |
continue;
|
| 1239 |
ctx->prot = prot; |
| 1240 |
if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
|
| 1241 |
ret = 0;
|
| 1242 |
break;
|
| 1243 |
} |
| 1244 |
ret = -2;
|
| 1245 |
} |
| 1246 |
} |
| 1247 |
if (ret >= 0) |
| 1248 |
ctx->raddr = raddr; |
| 1249 |
|
| 1250 |
return ret;
|
| 1251 |
} |
| 1252 |
|
| 1253 |
static inline int check_physical(CPUState *env, mmu_ctx_t *ctx, |
| 1254 |
target_ulong eaddr, int rw)
|
| 1255 |
{
|
| 1256 |
int in_plb, ret;
|
| 1257 |
|
| 1258 |
ctx->raddr = eaddr; |
| 1259 |
ctx->prot = PAGE_READ | PAGE_EXEC; |
| 1260 |
ret = 0;
|
| 1261 |
switch (env->mmu_model) {
|
| 1262 |
case POWERPC_MMU_32B:
|
| 1263 |
case POWERPC_MMU_601:
|
| 1264 |
case POWERPC_MMU_SOFT_6xx:
|
| 1265 |
case POWERPC_MMU_SOFT_74xx:
|
| 1266 |
case POWERPC_MMU_SOFT_4xx:
|
| 1267 |
case POWERPC_MMU_REAL:
|
| 1268 |
case POWERPC_MMU_BOOKE:
|
| 1269 |
ctx->prot |= PAGE_WRITE; |
| 1270 |
break;
|
| 1271 |
#if defined(TARGET_PPC64)
|
| 1272 |
case POWERPC_MMU_620:
|
| 1273 |
case POWERPC_MMU_64B:
|
| 1274 |
/* Real address are 60 bits long */
|
| 1275 |
ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
|
| 1276 |
ctx->prot |= PAGE_WRITE; |
| 1277 |
break;
|
| 1278 |
#endif
|
| 1279 |
case POWERPC_MMU_SOFT_4xx_Z:
|
| 1280 |
if (unlikely(msr_pe != 0)) { |
| 1281 |
/* 403 family add some particular protections,
|
| 1282 |
* using PBL/PBU registers for accesses with no translation.
|
| 1283 |
*/
|
| 1284 |
in_plb = |
| 1285 |
/* Check PLB validity */
|
| 1286 |
(env->pb[0] < env->pb[1] && |
| 1287 |
/* and address in plb area */
|
| 1288 |
eaddr >= env->pb[0] && eaddr < env->pb[1]) || |
| 1289 |
(env->pb[2] < env->pb[3] && |
| 1290 |
eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; |
| 1291 |
if (in_plb ^ msr_px) {
|
| 1292 |
/* Access in protected area */
|
| 1293 |
if (rw == 1) { |
| 1294 |
/* Access is not allowed */
|
| 1295 |
ret = -2;
|
| 1296 |
} |
| 1297 |
} else {
|
| 1298 |
/* Read-write access is allowed */
|
| 1299 |
ctx->prot |= PAGE_WRITE; |
| 1300 |
} |
| 1301 |
} |
| 1302 |
break;
|
| 1303 |
case POWERPC_MMU_MPC8xx:
|
| 1304 |
/* XXX: TODO */
|
| 1305 |
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
| 1306 |
break;
|
| 1307 |
case POWERPC_MMU_BOOKE_FSL:
|
| 1308 |
/* XXX: TODO */
|
| 1309 |
cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
| 1310 |
break;
|
| 1311 |
default:
|
| 1312 |
cpu_abort(env, "Unknown or invalid MMU model\n");
|
| 1313 |
return -1; |
| 1314 |
} |
| 1315 |
|
| 1316 |
return ret;
|
| 1317 |
} |
| 1318 |
|
| 1319 |
int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
| 1320 |
int rw, int access_type) |
| 1321 |
{
|
| 1322 |
int ret;
|
| 1323 |
|
| 1324 |
#if 0
|
| 1325 |
qemu_log("%s\n", __func__);
|
| 1326 |
#endif
|
| 1327 |
if ((access_type == ACCESS_CODE && msr_ir == 0) || |
| 1328 |
(access_type != ACCESS_CODE && msr_dr == 0)) {
|
| 1329 |
/* No address translation */
|
| 1330 |
ret = check_physical(env, ctx, eaddr, rw); |
| 1331 |
} else {
|
| 1332 |
ret = -1;
|
| 1333 |
switch (env->mmu_model) {
|
| 1334 |
case POWERPC_MMU_32B:
|
| 1335 |
case POWERPC_MMU_601:
|
| 1336 |
case POWERPC_MMU_SOFT_6xx:
|
| 1337 |
case POWERPC_MMU_SOFT_74xx:
|
| 1338 |
/* Try to find a BAT */
|
| 1339 |
if (env->nb_BATs != 0) |
| 1340 |
ret = get_bat(env, ctx, eaddr, rw, access_type); |
| 1341 |
#if defined(TARGET_PPC64)
|
| 1342 |
case POWERPC_MMU_620:
|
| 1343 |
case POWERPC_MMU_64B:
|
| 1344 |
#endif
|
| 1345 |
if (ret < 0) { |
| 1346 |
/* We didn't match any BAT entry or don't have BATs */
|
| 1347 |
ret = get_segment(env, ctx, eaddr, rw, access_type); |
| 1348 |
} |
| 1349 |
break;
|
| 1350 |
case POWERPC_MMU_SOFT_4xx:
|
| 1351 |
case POWERPC_MMU_SOFT_4xx_Z:
|
| 1352 |
ret = mmu40x_get_physical_address(env, ctx, eaddr, |
| 1353 |
rw, access_type); |
| 1354 |
break;
|
| 1355 |
case POWERPC_MMU_BOOKE:
|
| 1356 |
ret = mmubooke_get_physical_address(env, ctx, eaddr, |
| 1357 |
rw, access_type); |
| 1358 |
break;
|
| 1359 |
case POWERPC_MMU_MPC8xx:
|
| 1360 |
/* XXX: TODO */
|
| 1361 |
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
| 1362 |
break;
|
| 1363 |
case POWERPC_MMU_BOOKE_FSL:
|
| 1364 |
/* XXX: TODO */
|
| 1365 |
cpu_abort(env, "BookE FSL MMU model not implemented\n");
|
| 1366 |
return -1; |
| 1367 |
case POWERPC_MMU_REAL:
|
| 1368 |
cpu_abort(env, "PowerPC in real mode do not do any translation\n");
|
| 1369 |
return -1; |
| 1370 |
default:
|
| 1371 |
cpu_abort(env, "Unknown or invalid MMU model\n");
|
| 1372 |
return -1; |
| 1373 |
} |
| 1374 |
} |
| 1375 |
#if 0
|
| 1376 |
qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
|
| 1377 |
__func__, eaddr, ret, ctx->raddr);
|
| 1378 |
#endif
|
| 1379 |
|
| 1380 |
return ret;
|
| 1381 |
} |
| 1382 |
|
| 1383 |
target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
| 1384 |
{
|
| 1385 |
mmu_ctx_t ctx; |
| 1386 |
|
| 1387 |
if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) |
| 1388 |
return -1; |
| 1389 |
|
| 1390 |
return ctx.raddr & TARGET_PAGE_MASK;
|
| 1391 |
} |
| 1392 |
|
| 1393 |
/* Perform address translation */
|
| 1394 |
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 1395 |
int mmu_idx, int is_softmmu) |
| 1396 |
{
|
| 1397 |
mmu_ctx_t ctx; |
| 1398 |
int access_type;
|
| 1399 |
int ret = 0; |
| 1400 |
|
| 1401 |
if (rw == 2) { |
| 1402 |
/* code access */
|
| 1403 |
rw = 0;
|
| 1404 |
access_type = ACCESS_CODE; |
| 1405 |
} else {
|
| 1406 |
/* data access */
|
| 1407 |
access_type = env->access_type; |
| 1408 |
} |
| 1409 |
ret = get_physical_address(env, &ctx, address, rw, access_type); |
| 1410 |
if (ret == 0) { |
| 1411 |
tlb_set_page(env, address & TARGET_PAGE_MASK, |
| 1412 |
ctx.raddr & TARGET_PAGE_MASK, ctx.prot, |
| 1413 |
mmu_idx, TARGET_PAGE_SIZE); |
| 1414 |
ret = 0;
|
| 1415 |
} else if (ret < 0) { |
| 1416 |
LOG_MMU_STATE(env); |
| 1417 |
if (access_type == ACCESS_CODE) {
|
| 1418 |
switch (ret) {
|
| 1419 |
case -1: |
| 1420 |
/* No matches in page tables or TLB */
|
| 1421 |
switch (env->mmu_model) {
|
| 1422 |
case POWERPC_MMU_SOFT_6xx:
|
| 1423 |
env->exception_index = POWERPC_EXCP_IFTLB; |
| 1424 |
env->error_code = 1 << 18; |
| 1425 |
env->spr[SPR_IMISS] = address; |
| 1426 |
env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
|
| 1427 |
goto tlb_miss;
|
| 1428 |
case POWERPC_MMU_SOFT_74xx:
|
| 1429 |
env->exception_index = POWERPC_EXCP_IFTLB; |
| 1430 |
goto tlb_miss_74xx;
|
| 1431 |
case POWERPC_MMU_SOFT_4xx:
|
| 1432 |
case POWERPC_MMU_SOFT_4xx_Z:
|
| 1433 |
env->exception_index = POWERPC_EXCP_ITLB; |
| 1434 |
env->error_code = 0;
|
| 1435 |
env->spr[SPR_40x_DEAR] = address; |
| 1436 |
env->spr[SPR_40x_ESR] = 0x00000000;
|
| 1437 |
break;
|
| 1438 |
case POWERPC_MMU_32B:
|
| 1439 |
case POWERPC_MMU_601:
|
| 1440 |
#if defined(TARGET_PPC64)
|
| 1441 |
case POWERPC_MMU_620:
|
| 1442 |
case POWERPC_MMU_64B:
|
| 1443 |
#endif
|
| 1444 |
env->exception_index = POWERPC_EXCP_ISI; |
| 1445 |
env->error_code = 0x40000000;
|
| 1446 |
break;
|
| 1447 |
case POWERPC_MMU_BOOKE:
|
| 1448 |
/* XXX: TODO */
|
| 1449 |
cpu_abort(env, "BookE MMU model is not implemented\n");
|
| 1450 |
return -1; |
| 1451 |
case POWERPC_MMU_BOOKE_FSL:
|
| 1452 |
/* XXX: TODO */
|
| 1453 |
cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
| 1454 |
return -1; |
| 1455 |
case POWERPC_MMU_MPC8xx:
|
| 1456 |
/* XXX: TODO */
|
| 1457 |
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
| 1458 |
break;
|
| 1459 |
case POWERPC_MMU_REAL:
|
| 1460 |
cpu_abort(env, "PowerPC in real mode should never raise "
|
| 1461 |
"any MMU exceptions\n");
|
| 1462 |
return -1; |
| 1463 |
default:
|
| 1464 |
cpu_abort(env, "Unknown or invalid MMU model\n");
|
| 1465 |
return -1; |
| 1466 |
} |
| 1467 |
break;
|
| 1468 |
case -2: |
| 1469 |
/* Access rights violation */
|
| 1470 |
env->exception_index = POWERPC_EXCP_ISI; |
| 1471 |
env->error_code = 0x08000000;
|
| 1472 |
break;
|
| 1473 |
case -3: |
| 1474 |
/* No execute protection violation */
|
| 1475 |
env->exception_index = POWERPC_EXCP_ISI; |
| 1476 |
env->error_code = 0x10000000;
|
| 1477 |
break;
|
| 1478 |
case -4: |
| 1479 |
/* Direct store exception */
|
| 1480 |
/* No code fetch is allowed in direct-store areas */
|
| 1481 |
env->exception_index = POWERPC_EXCP_ISI; |
| 1482 |
env->error_code = 0x10000000;
|
| 1483 |
break;
|
| 1484 |
#if defined(TARGET_PPC64)
|
| 1485 |
case -5: |
| 1486 |
/* No match in segment table */
|
| 1487 |
if (env->mmu_model == POWERPC_MMU_620) {
|
| 1488 |
env->exception_index = POWERPC_EXCP_ISI; |
| 1489 |
/* XXX: this might be incorrect */
|
| 1490 |
env->error_code = 0x40000000;
|
| 1491 |
} else {
|
| 1492 |
env->exception_index = POWERPC_EXCP_ISEG; |
| 1493 |
env->error_code = 0;
|
| 1494 |
} |
| 1495 |
break;
|
| 1496 |
#endif
|
| 1497 |
} |
| 1498 |
} else {
|
| 1499 |
switch (ret) {
|
| 1500 |
case -1: |
| 1501 |
/* No matches in page tables or TLB */
|
| 1502 |
switch (env->mmu_model) {
|
| 1503 |
case POWERPC_MMU_SOFT_6xx:
|
| 1504 |
if (rw == 1) { |
| 1505 |
env->exception_index = POWERPC_EXCP_DSTLB; |
| 1506 |
env->error_code = 1 << 16; |
| 1507 |
} else {
|
| 1508 |
env->exception_index = POWERPC_EXCP_DLTLB; |
| 1509 |
env->error_code = 0;
|
| 1510 |
} |
| 1511 |
env->spr[SPR_DMISS] = address; |
| 1512 |
env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
|
| 1513 |
tlb_miss:
|
| 1514 |
env->error_code |= ctx.key << 19;
|
| 1515 |
env->spr[SPR_HASH1] = ctx.pg_addr[0];
|
| 1516 |
env->spr[SPR_HASH2] = ctx.pg_addr[1];
|
| 1517 |
break;
|
| 1518 |
case POWERPC_MMU_SOFT_74xx:
|
| 1519 |
if (rw == 1) { |
| 1520 |
env->exception_index = POWERPC_EXCP_DSTLB; |
| 1521 |
} else {
|
| 1522 |
env->exception_index = POWERPC_EXCP_DLTLB; |
| 1523 |
} |
| 1524 |
tlb_miss_74xx:
|
| 1525 |
/* Implement LRU algorithm */
|
| 1526 |
env->error_code = ctx.key << 19;
|
| 1527 |
env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
|
| 1528 |
((env->last_way + 1) & (env->nb_ways - 1)); |
| 1529 |
env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
|
| 1530 |
break;
|
| 1531 |
case POWERPC_MMU_SOFT_4xx:
|
| 1532 |
case POWERPC_MMU_SOFT_4xx_Z:
|
| 1533 |
env->exception_index = POWERPC_EXCP_DTLB; |
| 1534 |
env->error_code = 0;
|
| 1535 |
env->spr[SPR_40x_DEAR] = address; |
| 1536 |
if (rw)
|
| 1537 |
env->spr[SPR_40x_ESR] = 0x00800000;
|
| 1538 |
else
|
| 1539 |
env->spr[SPR_40x_ESR] = 0x00000000;
|
| 1540 |
break;
|
| 1541 |
case POWERPC_MMU_32B:
|
| 1542 |
case POWERPC_MMU_601:
|
| 1543 |
#if defined(TARGET_PPC64)
|
| 1544 |
case POWERPC_MMU_620:
|
| 1545 |
case POWERPC_MMU_64B:
|
| 1546 |
#endif
|
| 1547 |
env->exception_index = POWERPC_EXCP_DSI; |
| 1548 |
env->error_code = 0;
|
| 1549 |
env->spr[SPR_DAR] = address; |
| 1550 |
if (rw == 1) |
| 1551 |
env->spr[SPR_DSISR] = 0x42000000;
|
| 1552 |
else
|
| 1553 |
env->spr[SPR_DSISR] = 0x40000000;
|
| 1554 |
break;
|
| 1555 |
case POWERPC_MMU_MPC8xx:
|
| 1556 |
/* XXX: TODO */
|
| 1557 |
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
| 1558 |
break;
|
| 1559 |
case POWERPC_MMU_BOOKE:
|
| 1560 |
/* XXX: TODO */
|
| 1561 |
cpu_abort(env, "BookE MMU model is not implemented\n");
|
| 1562 |
return -1; |
| 1563 |
case POWERPC_MMU_BOOKE_FSL:
|
| 1564 |
/* XXX: TODO */
|
| 1565 |
cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
| 1566 |
return -1; |
| 1567 |
case POWERPC_MMU_REAL:
|
| 1568 |
cpu_abort(env, "PowerPC in real mode should never raise "
|
| 1569 |
"any MMU exceptions\n");
|
| 1570 |
return -1; |
| 1571 |
default:
|
| 1572 |
cpu_abort(env, "Unknown or invalid MMU model\n");
|
| 1573 |
return -1; |
| 1574 |
} |
| 1575 |
break;
|
| 1576 |
case -2: |
| 1577 |
/* Access rights violation */
|
| 1578 |
env->exception_index = POWERPC_EXCP_DSI; |
| 1579 |
env->error_code = 0;
|
| 1580 |
if (env->mmu_model == POWERPC_MMU_SOFT_4xx
|
| 1581 |
|| env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) {
|
| 1582 |
env->spr[SPR_40x_DEAR] = address; |
| 1583 |
if (rw) {
|
| 1584 |
env->spr[SPR_40x_ESR] |= 0x00800000;
|
| 1585 |
} |
| 1586 |
} else {
|
| 1587 |
env->spr[SPR_DAR] = address; |
| 1588 |
if (rw == 1) { |
| 1589 |
env->spr[SPR_DSISR] = 0x0A000000;
|
| 1590 |
} else {
|
| 1591 |
env->spr[SPR_DSISR] = 0x08000000;
|
| 1592 |
} |
| 1593 |
} |
| 1594 |
break;
|
| 1595 |
case -4: |
| 1596 |
/* Direct store exception */
|
| 1597 |
switch (access_type) {
|
| 1598 |
case ACCESS_FLOAT:
|
| 1599 |
/* Floating point load/store */
|
| 1600 |
env->exception_index = POWERPC_EXCP_ALIGN; |
| 1601 |
env->error_code = POWERPC_EXCP_ALIGN_FP; |
| 1602 |
env->spr[SPR_DAR] = address; |
| 1603 |
break;
|
| 1604 |
case ACCESS_RES:
|
| 1605 |
/* lwarx, ldarx or stwcx. */
|
| 1606 |
env->exception_index = POWERPC_EXCP_DSI; |
| 1607 |
env->error_code = 0;
|
| 1608 |
env->spr[SPR_DAR] = address; |
| 1609 |
if (rw == 1) |
| 1610 |
env->spr[SPR_DSISR] = 0x06000000;
|
| 1611 |
else
|
| 1612 |
env->spr[SPR_DSISR] = 0x04000000;
|
| 1613 |
break;
|
| 1614 |
case ACCESS_EXT:
|
| 1615 |
/* eciwx or ecowx */
|
| 1616 |
env->exception_index = POWERPC_EXCP_DSI; |
| 1617 |
env->error_code = 0;
|
| 1618 |
env->spr[SPR_DAR] = address; |
| 1619 |
if (rw == 1) |
| 1620 |
env->spr[SPR_DSISR] = 0x06100000;
|
| 1621 |
else
|
| 1622 |
env->spr[SPR_DSISR] = 0x04100000;
|
| 1623 |
break;
|
| 1624 |
default:
|
| 1625 |
printf("DSI: invalid exception (%d)\n", ret);
|
| 1626 |
env->exception_index = POWERPC_EXCP_PROGRAM; |
| 1627 |
env->error_code = |
| 1628 |
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; |
| 1629 |
env->spr[SPR_DAR] = address; |
| 1630 |
break;
|
| 1631 |
} |
| 1632 |
break;
|
| 1633 |
#if defined(TARGET_PPC64)
|
| 1634 |
case -5: |
| 1635 |
/* No match in segment table */
|
| 1636 |
if (env->mmu_model == POWERPC_MMU_620) {
|
| 1637 |
env->exception_index = POWERPC_EXCP_DSI; |
| 1638 |
env->error_code = 0;
|
| 1639 |
env->spr[SPR_DAR] = address; |
| 1640 |
/* XXX: this might be incorrect */
|
| 1641 |
if (rw == 1) |
| 1642 |
env->spr[SPR_DSISR] = 0x42000000;
|
| 1643 |
else
|
| 1644 |
env->spr[SPR_DSISR] = 0x40000000;
|
| 1645 |
} else {
|
| 1646 |
env->exception_index = POWERPC_EXCP_DSEG; |
| 1647 |
env->error_code = 0;
|
| 1648 |
env->spr[SPR_DAR] = address; |
| 1649 |
} |
| 1650 |
break;
|
| 1651 |
#endif
|
| 1652 |
} |
| 1653 |
} |
| 1654 |
#if 0
|
| 1655 |
printf("%s: set exception to %d %02x\n", __func__,
|
| 1656 |
env->exception, env->error_code);
|
| 1657 |
#endif
|
| 1658 |
ret = 1;
|
| 1659 |
} |
| 1660 |
|
| 1661 |
return ret;
|
| 1662 |
} |
| 1663 |
|
| 1664 |
/*****************************************************************************/
|
| 1665 |
/* BATs management */
|
| 1666 |
#if !defined(FLUSH_ALL_TLBS)
|
| 1667 |
static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, |
| 1668 |
target_ulong mask) |
| 1669 |
{
|
| 1670 |
target_ulong base, end, page; |
| 1671 |
|
| 1672 |
base = BATu & ~0x0001FFFF;
|
| 1673 |
end = base + mask + 0x00020000;
|
| 1674 |
LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " (" |
| 1675 |
TARGET_FMT_lx ")\n", base, end, mask);
|
| 1676 |
for (page = base; page != end; page += TARGET_PAGE_SIZE)
|
| 1677 |
tlb_flush_page(env, page); |
| 1678 |
LOG_BATS("Flush done\n");
|
| 1679 |
} |
| 1680 |
#endif
|
| 1681 |
|
| 1682 |
static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr, |
| 1683 |
target_ulong value) |
| 1684 |
{
|
| 1685 |
LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID, |
| 1686 |
nr, ul == 0 ? 'u' : 'l', value, env->nip); |
| 1687 |
} |
| 1688 |
|
| 1689 |
void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
| 1690 |
{
|
| 1691 |
target_ulong mask; |
| 1692 |
|
| 1693 |
dump_store_bat(env, 'I', 0, nr, value); |
| 1694 |
if (env->IBAT[0][nr] != value) { |
| 1695 |
mask = (value << 15) & 0x0FFE0000UL; |
| 1696 |
#if !defined(FLUSH_ALL_TLBS)
|
| 1697 |
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
| 1698 |
#endif
|
| 1699 |
/* When storing valid upper BAT, mask BEPI and BRPN
|
| 1700 |
* and invalidate all TLBs covered by this BAT
|
| 1701 |
*/
|
| 1702 |
mask = (value << 15) & 0x0FFE0000UL; |
| 1703 |
env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
| 1704 |
(value & ~0x0001FFFFUL & ~mask);
|
| 1705 |
env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | |
| 1706 |
(env->IBAT[1][nr] & ~0x0001FFFF & ~mask); |
| 1707 |
#if !defined(FLUSH_ALL_TLBS)
|
| 1708 |
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
| 1709 |
#else
|
| 1710 |
tlb_flush(env, 1);
|
| 1711 |
#endif
|
| 1712 |
} |
| 1713 |
} |
| 1714 |
|
| 1715 |
void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
| 1716 |
{
|
| 1717 |
dump_store_bat(env, 'I', 1, nr, value); |
| 1718 |
env->IBAT[1][nr] = value;
|
| 1719 |
} |
| 1720 |
|
| 1721 |
void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
| 1722 |
{
|
| 1723 |
target_ulong mask; |
| 1724 |
|
| 1725 |
dump_store_bat(env, 'D', 0, nr, value); |
| 1726 |
if (env->DBAT[0][nr] != value) { |
| 1727 |
/* When storing valid upper BAT, mask BEPI and BRPN
|
| 1728 |
* and invalidate all TLBs covered by this BAT
|
| 1729 |
*/
|
| 1730 |
mask = (value << 15) & 0x0FFE0000UL; |
| 1731 |
#if !defined(FLUSH_ALL_TLBS)
|
| 1732 |
do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
| 1733 |
#endif
|
| 1734 |
mask = (value << 15) & 0x0FFE0000UL; |
| 1735 |
env->DBAT[0][nr] = (value & 0x00001FFFUL) | |
| 1736 |
(value & ~0x0001FFFFUL & ~mask);
|
| 1737 |
env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | |
| 1738 |
(env->DBAT[1][nr] & ~0x0001FFFF & ~mask); |
| 1739 |
#if !defined(FLUSH_ALL_TLBS)
|
| 1740 |
do_invalidate_BAT(env, env->DBAT[0][nr], mask);
|
| 1741 |
#else
|
| 1742 |
tlb_flush(env, 1);
|
| 1743 |
#endif
|
| 1744 |
} |
| 1745 |
} |
| 1746 |
|
| 1747 |
void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
| 1748 |
{
|
| 1749 |
dump_store_bat(env, 'D', 1, nr, value); |
| 1750 |
env->DBAT[1][nr] = value;
|
| 1751 |
} |
| 1752 |
|
| 1753 |
void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value) |
| 1754 |
{
|
| 1755 |
target_ulong mask; |
| 1756 |
#if defined(FLUSH_ALL_TLBS)
|
| 1757 |
int do_inval;
|
| 1758 |
#endif
|
| 1759 |
|
| 1760 |
dump_store_bat(env, 'I', 0, nr, value); |
| 1761 |
if (env->IBAT[0][nr] != value) { |
| 1762 |
#if defined(FLUSH_ALL_TLBS)
|
| 1763 |
do_inval = 0;
|
| 1764 |
#endif
|
| 1765 |
mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; |
| 1766 |
if (env->IBAT[1][nr] & 0x40) { |
| 1767 |
/* Invalidate BAT only if it is valid */
|
| 1768 |
#if !defined(FLUSH_ALL_TLBS)
|
| 1769 |
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
| 1770 |
#else
|
| 1771 |
do_inval = 1;
|
| 1772 |
#endif
|
| 1773 |
} |
| 1774 |
/* When storing valid upper BAT, mask BEPI and BRPN
|
| 1775 |
* and invalidate all TLBs covered by this BAT
|
| 1776 |
*/
|
| 1777 |
env->IBAT[0][nr] = (value & 0x00001FFFUL) | |
| 1778 |
(value & ~0x0001FFFFUL & ~mask);
|
| 1779 |
env->DBAT[0][nr] = env->IBAT[0][nr]; |
| 1780 |
if (env->IBAT[1][nr] & 0x40) { |
| 1781 |
#if !defined(FLUSH_ALL_TLBS)
|
| 1782 |
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
| 1783 |
#else
|
| 1784 |
do_inval = 1;
|
| 1785 |
#endif
|
| 1786 |
} |
| 1787 |
#if defined(FLUSH_ALL_TLBS)
|
| 1788 |
if (do_inval)
|
| 1789 |
tlb_flush(env, 1);
|
| 1790 |
#endif
|
| 1791 |
} |
| 1792 |
} |
| 1793 |
|
| 1794 |
void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value) |
| 1795 |
{
|
| 1796 |
target_ulong mask; |
| 1797 |
#if defined(FLUSH_ALL_TLBS)
|
| 1798 |
int do_inval;
|
| 1799 |
#endif
|
| 1800 |
|
| 1801 |
dump_store_bat(env, 'I', 1, nr, value); |
| 1802 |
if (env->IBAT[1][nr] != value) { |
| 1803 |
#if defined(FLUSH_ALL_TLBS)
|
| 1804 |
do_inval = 0;
|
| 1805 |
#endif
|
| 1806 |
if (env->IBAT[1][nr] & 0x40) { |
| 1807 |
#if !defined(FLUSH_ALL_TLBS)
|
| 1808 |
mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; |
| 1809 |
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
| 1810 |
#else
|
| 1811 |
do_inval = 1;
|
| 1812 |
#endif
|
| 1813 |
} |
| 1814 |
if (value & 0x40) { |
| 1815 |
#if !defined(FLUSH_ALL_TLBS)
|
| 1816 |
mask = (value << 17) & 0x0FFE0000UL; |
| 1817 |
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
|
| 1818 |
#else
|
| 1819 |
do_inval = 1;
|
| 1820 |
#endif
|
| 1821 |
} |
| 1822 |
env->IBAT[1][nr] = value;
|
| 1823 |
env->DBAT[1][nr] = value;
|
| 1824 |
#if defined(FLUSH_ALL_TLBS)
|
| 1825 |
if (do_inval)
|
| 1826 |
tlb_flush(env, 1);
|
| 1827 |
#endif
|
| 1828 |
} |
| 1829 |
} |
| 1830 |
|
| 1831 |
/*****************************************************************************/
|
| 1832 |
/* TLB management */
|
| 1833 |
void ppc_tlb_invalidate_all (CPUPPCState *env)
|
| 1834 |
{
|
| 1835 |
switch (env->mmu_model) {
|
| 1836 |
case POWERPC_MMU_SOFT_6xx:
|
| 1837 |
case POWERPC_MMU_SOFT_74xx:
|
| 1838 |
ppc6xx_tlb_invalidate_all(env); |
| 1839 |
break;
|
| 1840 |
case POWERPC_MMU_SOFT_4xx:
|
| 1841 |
case POWERPC_MMU_SOFT_4xx_Z:
|
| 1842 |
ppc4xx_tlb_invalidate_all(env); |
| 1843 |
break;
|
| 1844 |
case POWERPC_MMU_REAL:
|
| 1845 |
cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
| 1846 |
break;
|
| 1847 |
case POWERPC_MMU_MPC8xx:
|
| 1848 |
/* XXX: TODO */
|
| 1849 |
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
| 1850 |
break;
|
| 1851 |
case POWERPC_MMU_BOOKE:
|
| 1852 |
/* XXX: TODO */
|
| 1853 |
cpu_abort(env, "BookE MMU model is not implemented\n");
|
| 1854 |
break;
|
| 1855 |
case POWERPC_MMU_BOOKE_FSL:
|
| 1856 |
/* XXX: TODO */
|
| 1857 |
if (!kvm_enabled())
|
| 1858 |
cpu_abort(env, "BookE MMU model is not implemented\n");
|
| 1859 |
break;
|
| 1860 |
case POWERPC_MMU_32B:
|
| 1861 |
case POWERPC_MMU_601:
|
| 1862 |
#if defined(TARGET_PPC64)
|
| 1863 |
case POWERPC_MMU_620:
|
| 1864 |
case POWERPC_MMU_64B:
|
| 1865 |
#endif /* defined(TARGET_PPC64) */ |
| 1866 |
tlb_flush(env, 1);
|
| 1867 |
break;
|
| 1868 |
default:
|
| 1869 |
/* XXX: TODO */
|
| 1870 |
cpu_abort(env, "Unknown MMU model\n");
|
| 1871 |
break;
|
| 1872 |
} |
| 1873 |
} |
| 1874 |
|
| 1875 |
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
|
| 1876 |
{
|
| 1877 |
#if !defined(FLUSH_ALL_TLBS)
|
| 1878 |
addr &= TARGET_PAGE_MASK; |
| 1879 |
switch (env->mmu_model) {
|
| 1880 |
case POWERPC_MMU_SOFT_6xx:
|
| 1881 |
case POWERPC_MMU_SOFT_74xx:
|
| 1882 |
ppc6xx_tlb_invalidate_virt(env, addr, 0);
|
| 1883 |
if (env->id_tlbs == 1) |
| 1884 |
ppc6xx_tlb_invalidate_virt(env, addr, 1);
|
| 1885 |
break;
|
| 1886 |
case POWERPC_MMU_SOFT_4xx:
|
| 1887 |
case POWERPC_MMU_SOFT_4xx_Z:
|
| 1888 |
ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); |
| 1889 |
break;
|
| 1890 |
case POWERPC_MMU_REAL:
|
| 1891 |
cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
|
| 1892 |
break;
|
| 1893 |
case POWERPC_MMU_MPC8xx:
|
| 1894 |
/* XXX: TODO */
|
| 1895 |
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
|
| 1896 |
break;
|
| 1897 |
case POWERPC_MMU_BOOKE:
|
| 1898 |
/* XXX: TODO */
|
| 1899 |
cpu_abort(env, "BookE MMU model is not implemented\n");
|
| 1900 |
break;
|
| 1901 |
case POWERPC_MMU_BOOKE_FSL:
|
| 1902 |
/* XXX: TODO */
|
| 1903 |
cpu_abort(env, "BookE FSL MMU model is not implemented\n");
|
| 1904 |
break;
|
| 1905 |
case POWERPC_MMU_32B:
|
| 1906 |
case POWERPC_MMU_601:
|
| 1907 |
/* tlbie invalidate TLBs for all segments */
|
| 1908 |
addr &= ~((target_ulong)-1ULL << 28); |
| 1909 |
/* XXX: this case should be optimized,
|
| 1910 |
* giving a mask to tlb_flush_page
|
| 1911 |
*/
|
| 1912 |
tlb_flush_page(env, addr | (0x0 << 28)); |
| 1913 |
tlb_flush_page(env, addr | (0x1 << 28)); |
| 1914 |
tlb_flush_page(env, addr | (0x2 << 28)); |
| 1915 |
tlb_flush_page(env, addr | (0x3 << 28)); |
| 1916 |
tlb_flush_page(env, addr | (0x4 << 28)); |
| 1917 |
tlb_flush_page(env, addr | (0x5 << 28)); |
| 1918 |
tlb_flush_page(env, addr | (0x6 << 28)); |
| 1919 |
tlb_flush_page(env, addr | (0x7 << 28)); |
| 1920 |
tlb_flush_page(env, addr | (0x8 << 28)); |
| 1921 |
tlb_flush_page(env, addr | (0x9 << 28)); |
| 1922 |
tlb_flush_page(env, addr | (0xA << 28)); |
| 1923 |
tlb_flush_page(env, addr | (0xB << 28)); |
| 1924 |
tlb_flush_page(env, addr | (0xC << 28)); |
| 1925 |
tlb_flush_page(env, addr | (0xD << 28)); |
| 1926 |
tlb_flush_page(env, addr | (0xE << 28)); |
| 1927 |
tlb_flush_page(env, addr | (0xF << 28)); |
| 1928 |
break;
|
| 1929 |
#if defined(TARGET_PPC64)
|
| 1930 |
case POWERPC_MMU_620:
|
| 1931 |
case POWERPC_MMU_64B:
|
| 1932 |
/* tlbie invalidate TLBs for all segments */
|
| 1933 |
/* XXX: given the fact that there are too many segments to invalidate,
|
| 1934 |
* and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
|
| 1935 |
* we just invalidate all TLBs
|
| 1936 |
*/
|
| 1937 |
tlb_flush(env, 1);
|
| 1938 |
break;
|
| 1939 |
#endif /* defined(TARGET_PPC64) */ |
| 1940 |
default:
|
| 1941 |
/* XXX: TODO */
|
| 1942 |
cpu_abort(env, "Unknown MMU model\n");
|
| 1943 |
break;
|
| 1944 |
} |
| 1945 |
#else
|
| 1946 |
ppc_tlb_invalidate_all(env); |
| 1947 |
#endif
|
| 1948 |
} |
| 1949 |
|
| 1950 |
/*****************************************************************************/
|
| 1951 |
/* Special registers manipulation */
|
| 1952 |
#if defined(TARGET_PPC64)
|
| 1953 |
void ppc_store_asr (CPUPPCState *env, target_ulong value)
|
| 1954 |
{
|
| 1955 |
if (env->asr != value) {
|
| 1956 |
env->asr = value; |
| 1957 |
tlb_flush(env, 1);
|
| 1958 |
} |
| 1959 |
} |
| 1960 |
#endif
|
| 1961 |
|
| 1962 |
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
|
| 1963 |
{
|
| 1964 |
LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value); |
| 1965 |
if (env->sdr1 != value) {
|
| 1966 |
/* XXX: for PowerPC 64, should check that the HTABSIZE value
|
| 1967 |
* is <= 28
|
| 1968 |
*/
|
| 1969 |
env->sdr1 = value; |
| 1970 |
tlb_flush(env, 1);
|
| 1971 |
} |
| 1972 |
} |
| 1973 |
|
| 1974 |
#if defined(TARGET_PPC64)
|
| 1975 |
target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr)
|
| 1976 |
{
|
| 1977 |
// XXX
|
| 1978 |
return 0; |
| 1979 |
} |
| 1980 |
#endif
|
| 1981 |
|
| 1982 |
void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
| 1983 |
{
|
| 1984 |
LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, |
| 1985 |
srnum, value, env->sr[srnum]); |
| 1986 |
#if defined(TARGET_PPC64)
|
| 1987 |
if (env->mmu_model & POWERPC_MMU_64) {
|
| 1988 |
uint64_t rb = 0, rs = 0; |
| 1989 |
|
| 1990 |
/* ESID = srnum */
|
| 1991 |
rb |= ((uint32_t)srnum & 0xf) << 28; |
| 1992 |
/* Set the valid bit */
|
| 1993 |
rb |= 1 << 27; |
| 1994 |
/* Index = ESID */
|
| 1995 |
rb |= (uint32_t)srnum; |
| 1996 |
|
| 1997 |
/* VSID = VSID */
|
| 1998 |
rs |= (value & 0xfffffff) << 12; |
| 1999 |
/* flags = flags */
|
| 2000 |
rs |= ((value >> 27) & 0xf) << 9; |
| 2001 |
|
| 2002 |
ppc_store_slb(env, rb, rs); |
| 2003 |
} else
|
| 2004 |
#endif
|
| 2005 |
if (env->sr[srnum] != value) {
|
| 2006 |
env->sr[srnum] = value; |
| 2007 |
/* Invalidating 256MB of virtual memory in 4kB pages is way longer than
|
| 2008 |
flusing the whole TLB. */
|
| 2009 |
#if !defined(FLUSH_ALL_TLBS) && 0 |
| 2010 |
{
|
| 2011 |
target_ulong page, end; |
| 2012 |
/* Invalidate 256 MB of virtual memory */
|
| 2013 |
page = (16 << 20) * srnum; |
| 2014 |
end = page + (16 << 20); |
| 2015 |
for (; page != end; page += TARGET_PAGE_SIZE)
|
| 2016 |
tlb_flush_page(env, page); |
| 2017 |
} |
| 2018 |
#else
|
| 2019 |
tlb_flush(env, 1);
|
| 2020 |
#endif
|
| 2021 |
} |
| 2022 |
} |
| 2023 |
#endif /* !defined (CONFIG_USER_ONLY) */ |
| 2024 |
|
| 2025 |
/* GDBstub can read and write MSR... */
|
| 2026 |
void ppc_store_msr (CPUPPCState *env, target_ulong value)
|
| 2027 |
{
|
| 2028 |
hreg_store_msr(env, value, 0);
|
| 2029 |
} |
| 2030 |
|
| 2031 |
/*****************************************************************************/
|
| 2032 |
/* Exception processing */
|
| 2033 |
#if defined (CONFIG_USER_ONLY)
|
| 2034 |
void do_interrupt (CPUState *env)
|
| 2035 |
{
|
| 2036 |
env->exception_index = POWERPC_EXCP_NONE; |
| 2037 |
env->error_code = 0;
|
| 2038 |
} |
| 2039 |
|
| 2040 |
void ppc_hw_interrupt (CPUState *env)
|
| 2041 |
{
|
| 2042 |
env->exception_index = POWERPC_EXCP_NONE; |
| 2043 |
env->error_code = 0;
|
| 2044 |
} |
| 2045 |
#else /* defined (CONFIG_USER_ONLY) */ |
| 2046 |
static inline void dump_syscall(CPUState *env) |
| 2047 |
{
|
| 2048 |
qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64 |
| 2049 |
" r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64 |
| 2050 |
" nip=" TARGET_FMT_lx "\n", |
| 2051 |
ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), |
| 2052 |
ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5), |
| 2053 |
ppc_dump_gpr(env, 6), env->nip);
|
| 2054 |
} |
| 2055 |
|
| 2056 |
/* Note that this function should be greatly optimized
|
| 2057 |
* when called with a constant excp, from ppc_hw_interrupt
|
| 2058 |
*/
|
| 2059 |
static inline void powerpc_excp(CPUState *env, int excp_model, int excp) |
| 2060 |
{
|
| 2061 |
target_ulong msr, new_msr, vector; |
| 2062 |
int srr0, srr1, asrr0, asrr1;
|
| 2063 |
int lpes0, lpes1, lev;
|
| 2064 |
|
| 2065 |
if (0) { |
| 2066 |
/* XXX: find a suitable condition to enable the hypervisor mode */
|
| 2067 |
lpes0 = (env->spr[SPR_LPCR] >> 1) & 1; |
| 2068 |
lpes1 = (env->spr[SPR_LPCR] >> 2) & 1; |
| 2069 |
} else {
|
| 2070 |
/* Those values ensure we won't enter the hypervisor mode */
|
| 2071 |
lpes0 = 0;
|
| 2072 |
lpes1 = 1;
|
| 2073 |
} |
| 2074 |
|
| 2075 |
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
|
| 2076 |
" => %08x (%02x)\n", env->nip, excp, env->error_code);
|
| 2077 |
msr = env->msr; |
| 2078 |
new_msr = msr; |
| 2079 |
srr0 = SPR_SRR0; |
| 2080 |
srr1 = SPR_SRR1; |
| 2081 |
asrr0 = -1;
|
| 2082 |
asrr1 = -1;
|
| 2083 |
switch (excp) {
|
| 2084 |
case POWERPC_EXCP_NONE:
|
| 2085 |
/* Should never happen */
|
| 2086 |
return;
|
| 2087 |
case POWERPC_EXCP_CRITICAL: /* Critical input */ |
| 2088 |
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
| 2089 |
switch (excp_model) {
|
| 2090 |
case POWERPC_EXCP_40x:
|
| 2091 |
srr0 = SPR_40x_SRR2; |
| 2092 |
srr1 = SPR_40x_SRR3; |
| 2093 |
break;
|
| 2094 |
case POWERPC_EXCP_BOOKE:
|
| 2095 |
srr0 = SPR_BOOKE_CSRR0; |
| 2096 |
srr1 = SPR_BOOKE_CSRR1; |
| 2097 |
break;
|
| 2098 |
case POWERPC_EXCP_G2:
|
| 2099 |
break;
|
| 2100 |
default:
|
| 2101 |
goto excp_invalid;
|
| 2102 |
} |
| 2103 |
goto store_next;
|
| 2104 |
case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
| 2105 |
if (msr_me == 0) { |
| 2106 |
/* Machine check exception is not enabled.
|
| 2107 |
* Enter checkstop state.
|
| 2108 |
*/
|
| 2109 |
if (qemu_log_enabled()) {
|
| 2110 |
qemu_log("Machine check while not allowed. "
|
| 2111 |
"Entering checkstop state\n");
|
| 2112 |
} else {
|
| 2113 |
fprintf(stderr, "Machine check while not allowed. "
|
| 2114 |
"Entering checkstop state\n");
|
| 2115 |
} |
| 2116 |
env->halted = 1;
|
| 2117 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
| 2118 |
} |
| 2119 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2120 |
new_msr &= ~((target_ulong)1 << MSR_ME);
|
| 2121 |
if (0) { |
| 2122 |
/* XXX: find a suitable condition to enable the hypervisor mode */
|
| 2123 |
new_msr |= (target_ulong)MSR_HVB; |
| 2124 |
} |
| 2125 |
/* XXX: should also have something loaded in DAR / DSISR */
|
| 2126 |
switch (excp_model) {
|
| 2127 |
case POWERPC_EXCP_40x:
|
| 2128 |
srr0 = SPR_40x_SRR2; |
| 2129 |
srr1 = SPR_40x_SRR3; |
| 2130 |
break;
|
| 2131 |
case POWERPC_EXCP_BOOKE:
|
| 2132 |
srr0 = SPR_BOOKE_MCSRR0; |
| 2133 |
srr1 = SPR_BOOKE_MCSRR1; |
| 2134 |
asrr0 = SPR_BOOKE_CSRR0; |
| 2135 |
asrr1 = SPR_BOOKE_CSRR1; |
| 2136 |
break;
|
| 2137 |
default:
|
| 2138 |
break;
|
| 2139 |
} |
| 2140 |
goto store_next;
|
| 2141 |
case POWERPC_EXCP_DSI: /* Data storage exception */ |
| 2142 |
LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx |
| 2143 |
"\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
| 2144 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2145 |
if (lpes1 == 0) |
| 2146 |
new_msr |= (target_ulong)MSR_HVB; |
| 2147 |
goto store_next;
|
| 2148 |
case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
| 2149 |
LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx |
| 2150 |
"\n", msr, env->nip);
|
| 2151 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2152 |
if (lpes1 == 0) |
| 2153 |
new_msr |= (target_ulong)MSR_HVB; |
| 2154 |
msr |= env->error_code; |
| 2155 |
goto store_next;
|
| 2156 |
case POWERPC_EXCP_EXTERNAL: /* External input */ |
| 2157 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2158 |
if (lpes0 == 1) |
| 2159 |
new_msr |= (target_ulong)MSR_HVB; |
| 2160 |
goto store_next;
|
| 2161 |
case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
| 2162 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2163 |
if (lpes1 == 0) |
| 2164 |
new_msr |= (target_ulong)MSR_HVB; |
| 2165 |
/* XXX: this is false */
|
| 2166 |
/* Get rS/rD and rA from faulting opcode */
|
| 2167 |
env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; |
| 2168 |
goto store_current;
|
| 2169 |
case POWERPC_EXCP_PROGRAM: /* Program exception */ |
| 2170 |
switch (env->error_code & ~0xF) { |
| 2171 |
case POWERPC_EXCP_FP:
|
| 2172 |
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { |
| 2173 |
LOG_EXCP("Ignore floating point exception\n");
|
| 2174 |
env->exception_index = POWERPC_EXCP_NONE; |
| 2175 |
env->error_code = 0;
|
| 2176 |
return;
|
| 2177 |
} |
| 2178 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2179 |
if (lpes1 == 0) |
| 2180 |
new_msr |= (target_ulong)MSR_HVB; |
| 2181 |
msr |= 0x00100000;
|
| 2182 |
if (msr_fe0 == msr_fe1)
|
| 2183 |
goto store_next;
|
| 2184 |
msr |= 0x00010000;
|
| 2185 |
break;
|
| 2186 |
case POWERPC_EXCP_INVAL:
|
| 2187 |
LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip); |
| 2188 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2189 |
if (lpes1 == 0) |
| 2190 |
new_msr |= (target_ulong)MSR_HVB; |
| 2191 |
msr |= 0x00080000;
|
| 2192 |
break;
|
| 2193 |
case POWERPC_EXCP_PRIV:
|
| 2194 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2195 |
if (lpes1 == 0) |
| 2196 |
new_msr |= (target_ulong)MSR_HVB; |
| 2197 |
msr |= 0x00040000;
|
| 2198 |
break;
|
| 2199 |
case POWERPC_EXCP_TRAP:
|
| 2200 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2201 |
if (lpes1 == 0) |
| 2202 |
new_msr |= (target_ulong)MSR_HVB; |
| 2203 |
msr |= 0x00020000;
|
| 2204 |
break;
|
| 2205 |
default:
|
| 2206 |
/* Should never occur */
|
| 2207 |
cpu_abort(env, "Invalid program exception %d. Aborting\n",
|
| 2208 |
env->error_code); |
| 2209 |
break;
|
| 2210 |
} |
| 2211 |
goto store_current;
|
| 2212 |
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
| 2213 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2214 |
if (lpes1 == 0) |
| 2215 |
new_msr |= (target_ulong)MSR_HVB; |
| 2216 |
goto store_current;
|
| 2217 |
case POWERPC_EXCP_SYSCALL: /* System call exception */ |
| 2218 |
/* NOTE: this is a temporary hack to support graphics OSI
|
| 2219 |
calls from the MOL driver */
|
| 2220 |
/* XXX: To be removed */
|
| 2221 |
if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
| 2222 |
env->osi_call) {
|
| 2223 |
if (env->osi_call(env) != 0) { |
| 2224 |
env->exception_index = POWERPC_EXCP_NONE; |
| 2225 |
env->error_code = 0;
|
| 2226 |
return;
|
| 2227 |
} |
| 2228 |
} |
| 2229 |
dump_syscall(env); |
| 2230 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2231 |
lev = env->error_code; |
| 2232 |
if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
| 2233 |
new_msr |= (target_ulong)MSR_HVB; |
| 2234 |
goto store_next;
|
| 2235 |
case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
| 2236 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2237 |
goto store_current;
|
| 2238 |
case POWERPC_EXCP_DECR: /* Decrementer exception */ |
| 2239 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2240 |
if (lpes1 == 0) |
| 2241 |
new_msr |= (target_ulong)MSR_HVB; |
| 2242 |
goto store_next;
|
| 2243 |
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
| 2244 |
/* FIT on 4xx */
|
| 2245 |
LOG_EXCP("FIT exception\n");
|
| 2246 |
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
| 2247 |
goto store_next;
|
| 2248 |
case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
| 2249 |
LOG_EXCP("WDT exception\n");
|
| 2250 |
switch (excp_model) {
|
| 2251 |
case POWERPC_EXCP_BOOKE:
|
| 2252 |
srr0 = SPR_BOOKE_CSRR0; |
| 2253 |
srr1 = SPR_BOOKE_CSRR1; |
| 2254 |
break;
|
| 2255 |
default:
|
| 2256 |
break;
|
| 2257 |
} |
| 2258 |
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
| 2259 |
goto store_next;
|
| 2260 |
case POWERPC_EXCP_DTLB: /* Data TLB error */ |
| 2261 |
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
| 2262 |
goto store_next;
|
| 2263 |
case POWERPC_EXCP_ITLB: /* Instruction TLB error */ |
| 2264 |
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
| 2265 |
goto store_next;
|
| 2266 |
case POWERPC_EXCP_DEBUG: /* Debug interrupt */ |
| 2267 |
switch (excp_model) {
|
| 2268 |
case POWERPC_EXCP_BOOKE:
|
| 2269 |
srr0 = SPR_BOOKE_DSRR0; |
| 2270 |
srr1 = SPR_BOOKE_DSRR1; |
| 2271 |
asrr0 = SPR_BOOKE_CSRR0; |
| 2272 |
asrr1 = SPR_BOOKE_CSRR1; |
| 2273 |
break;
|
| 2274 |
default:
|
| 2275 |
break;
|
| 2276 |
} |
| 2277 |
/* XXX: TODO */
|
| 2278 |
cpu_abort(env, "Debug exception is not implemented yet !\n");
|
| 2279 |
goto store_next;
|
| 2280 |
case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
| 2281 |
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
| 2282 |
goto store_current;
|
| 2283 |
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ |
| 2284 |
/* XXX: TODO */
|
| 2285 |
cpu_abort(env, "Embedded floating point data exception "
|
| 2286 |
"is not implemented yet !\n");
|
| 2287 |
goto store_next;
|
| 2288 |
case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
| 2289 |
/* XXX: TODO */
|
| 2290 |
cpu_abort(env, "Embedded floating point round exception "
|
| 2291 |
"is not implemented yet !\n");
|
| 2292 |
goto store_next;
|
| 2293 |
case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
| 2294 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2295 |
/* XXX: TODO */
|
| 2296 |
cpu_abort(env, |
| 2297 |
"Performance counter exception is not implemented yet !\n");
|
| 2298 |
goto store_next;
|
| 2299 |
case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
| 2300 |
/* XXX: TODO */
|
| 2301 |
cpu_abort(env, |
| 2302 |
"Embedded doorbell interrupt is not implemented yet !\n");
|
| 2303 |
goto store_next;
|
| 2304 |
case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
| 2305 |
switch (excp_model) {
|
| 2306 |
case POWERPC_EXCP_BOOKE:
|
| 2307 |
srr0 = SPR_BOOKE_CSRR0; |
| 2308 |
srr1 = SPR_BOOKE_CSRR1; |
| 2309 |
break;
|
| 2310 |
default:
|
| 2311 |
break;
|
| 2312 |
} |
| 2313 |
/* XXX: TODO */
|
| 2314 |
cpu_abort(env, "Embedded doorbell critical interrupt "
|
| 2315 |
"is not implemented yet !\n");
|
| 2316 |
goto store_next;
|
| 2317 |
case POWERPC_EXCP_RESET: /* System reset exception */ |
| 2318 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2319 |
if (0) { |
| 2320 |
/* XXX: find a suitable condition to enable the hypervisor mode */
|
| 2321 |
new_msr |= (target_ulong)MSR_HVB; |
| 2322 |
} |
| 2323 |
goto store_next;
|
| 2324 |
case POWERPC_EXCP_DSEG: /* Data segment exception */ |
| 2325 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2326 |
if (lpes1 == 0) |
| 2327 |
new_msr |= (target_ulong)MSR_HVB; |
| 2328 |
goto store_next;
|
| 2329 |
case POWERPC_EXCP_ISEG: /* Instruction segment exception */ |
| 2330 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2331 |
if (lpes1 == 0) |
| 2332 |
new_msr |= (target_ulong)MSR_HVB; |
| 2333 |
goto store_next;
|
| 2334 |
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
| 2335 |
srr0 = SPR_HSRR0; |
| 2336 |
srr1 = SPR_HSRR1; |
| 2337 |
new_msr |= (target_ulong)MSR_HVB; |
| 2338 |
goto store_next;
|
| 2339 |
case POWERPC_EXCP_TRACE: /* Trace exception */ |
| 2340 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2341 |
if (lpes1 == 0) |
| 2342 |
new_msr |= (target_ulong)MSR_HVB; |
| 2343 |
goto store_next;
|
| 2344 |
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
| 2345 |
srr0 = SPR_HSRR0; |
| 2346 |
srr1 = SPR_HSRR1; |
| 2347 |
new_msr |= (target_ulong)MSR_HVB; |
| 2348 |
goto store_next;
|
| 2349 |
case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ |
| 2350 |
srr0 = SPR_HSRR0; |
| 2351 |
srr1 = SPR_HSRR1; |
| 2352 |
new_msr |= (target_ulong)MSR_HVB; |
| 2353 |
goto store_next;
|
| 2354 |
case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
| 2355 |
srr0 = SPR_HSRR0; |
| 2356 |
srr1 = SPR_HSRR1; |
| 2357 |
new_msr |= (target_ulong)MSR_HVB; |
| 2358 |
goto store_next;
|
| 2359 |
case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ |
| 2360 |
srr0 = SPR_HSRR0; |
| 2361 |
srr1 = SPR_HSRR1; |
| 2362 |
new_msr |= (target_ulong)MSR_HVB; |
| 2363 |
goto store_next;
|
| 2364 |
case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
| 2365 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2366 |
if (lpes1 == 0) |
| 2367 |
new_msr |= (target_ulong)MSR_HVB; |
| 2368 |
goto store_current;
|
| 2369 |
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ |
| 2370 |
LOG_EXCP("PIT exception\n");
|
| 2371 |
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
| 2372 |
goto store_next;
|
| 2373 |
case POWERPC_EXCP_IO: /* IO error exception */ |
| 2374 |
/* XXX: TODO */
|
| 2375 |
cpu_abort(env, "601 IO error exception is not implemented yet !\n");
|
| 2376 |
goto store_next;
|
| 2377 |
case POWERPC_EXCP_RUNM: /* Run mode exception */ |
| 2378 |
/* XXX: TODO */
|
| 2379 |
cpu_abort(env, "601 run mode exception is not implemented yet !\n");
|
| 2380 |
goto store_next;
|
| 2381 |
case POWERPC_EXCP_EMUL: /* Emulation trap exception */ |
| 2382 |
/* XXX: TODO */
|
| 2383 |
cpu_abort(env, "602 emulation trap exception "
|
| 2384 |
"is not implemented yet !\n");
|
| 2385 |
goto store_next;
|
| 2386 |
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ |
| 2387 |
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
| 2388 |
if (lpes1 == 0) /* XXX: check this */ |
| 2389 |
new_msr |= (target_ulong)MSR_HVB; |
| 2390 |
switch (excp_model) {
|
| 2391 |
case POWERPC_EXCP_602:
|
| 2392 |
case POWERPC_EXCP_603:
|
| 2393 |
case POWERPC_EXCP_603E:
|
| 2394 |
case POWERPC_EXCP_G2:
|
| 2395 |
goto tlb_miss_tgpr;
|
| 2396 |
case POWERPC_EXCP_7x5:
|
| 2397 |
goto tlb_miss;
|
| 2398 |
case POWERPC_EXCP_74xx:
|
| 2399 |
goto tlb_miss_74xx;
|
| 2400 |
default:
|
| 2401 |
cpu_abort(env, "Invalid instruction TLB miss exception\n");
|
| 2402 |
break;
|
| 2403 |
} |
| 2404 |
break;
|
| 2405 |
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ |
| 2406 |
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
| 2407 |
if (lpes1 == 0) /* XXX: check this */ |
| 2408 |
new_msr |= (target_ulong)MSR_HVB; |
| 2409 |
switch (excp_model) {
|
| 2410 |
case POWERPC_EXCP_602:
|
| 2411 |
case POWERPC_EXCP_603:
|
| 2412 |
case POWERPC_EXCP_603E:
|
| 2413 |
case POWERPC_EXCP_G2:
|
| 2414 |
goto tlb_miss_tgpr;
|
| 2415 |
case POWERPC_EXCP_7x5:
|
| 2416 |
goto tlb_miss;
|
| 2417 |
case POWERPC_EXCP_74xx:
|
| 2418 |
goto tlb_miss_74xx;
|
| 2419 |
default:
|
| 2420 |
cpu_abort(env, "Invalid data load TLB miss exception\n");
|
| 2421 |
break;
|
| 2422 |
} |
| 2423 |
break;
|
| 2424 |
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ |
| 2425 |
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
| 2426 |
if (lpes1 == 0) /* XXX: check this */ |
| 2427 |
new_msr |= (target_ulong)MSR_HVB; |
| 2428 |
switch (excp_model) {
|
| 2429 |
case POWERPC_EXCP_602:
|
| 2430 |
case POWERPC_EXCP_603:
|
| 2431 |
case POWERPC_EXCP_603E:
|
| 2432 |
case POWERPC_EXCP_G2:
|
| 2433 |
tlb_miss_tgpr:
|
| 2434 |
/* Swap temporary saved registers with GPRs */
|
| 2435 |
if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { |
| 2436 |
new_msr |= (target_ulong)1 << MSR_TGPR;
|
| 2437 |
hreg_swap_gpr_tgpr(env); |
| 2438 |
} |
| 2439 |
goto tlb_miss;
|
| 2440 |
case POWERPC_EXCP_7x5:
|
| 2441 |
tlb_miss:
|
| 2442 |
#if defined (DEBUG_SOFTWARE_TLB)
|
| 2443 |
if (qemu_log_enabled()) {
|
| 2444 |
const char *es; |
| 2445 |
target_ulong *miss, *cmp; |
| 2446 |
int en;
|
| 2447 |
if (excp == POWERPC_EXCP_IFTLB) {
|
| 2448 |
es = "I";
|
| 2449 |
en = 'I';
|
| 2450 |
miss = &env->spr[SPR_IMISS]; |
| 2451 |
cmp = &env->spr[SPR_ICMP]; |
| 2452 |
} else {
|
| 2453 |
if (excp == POWERPC_EXCP_DLTLB)
|
| 2454 |
es = "DL";
|
| 2455 |
else
|
| 2456 |
es = "DS";
|
| 2457 |
en = 'D';
|
| 2458 |
miss = &env->spr[SPR_DMISS]; |
| 2459 |
cmp = &env->spr[SPR_DCMP]; |
| 2460 |
} |
| 2461 |
qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " |
| 2462 |
TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 " |
| 2463 |
TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
|
| 2464 |
env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
| 2465 |
env->error_code); |
| 2466 |
} |
| 2467 |
#endif
|
| 2468 |
msr |= env->crf[0] << 28; |
| 2469 |
msr |= env->error_code; /* key, D/I, S/L bits */
|
| 2470 |
/* Set way using a LRU mechanism */
|
| 2471 |
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
| 2472 |
break;
|
| 2473 |
case POWERPC_EXCP_74xx:
|
| 2474 |
tlb_miss_74xx:
|
| 2475 |
#if defined (DEBUG_SOFTWARE_TLB)
|
| 2476 |
if (qemu_log_enabled()) {
|
| 2477 |
const char *es; |
| 2478 |
target_ulong *miss, *cmp; |
| 2479 |
int en;
|
| 2480 |
if (excp == POWERPC_EXCP_IFTLB) {
|
| 2481 |
es = "I";
|
| 2482 |
en = 'I';
|
| 2483 |
miss = &env->spr[SPR_TLBMISS]; |
| 2484 |
cmp = &env->spr[SPR_PTEHI]; |
| 2485 |
} else {
|
| 2486 |
if (excp == POWERPC_EXCP_DLTLB)
|
| 2487 |
es = "DL";
|
| 2488 |
else
|
| 2489 |
es = "DS";
|
| 2490 |
en = 'D';
|
| 2491 |
miss = &env->spr[SPR_TLBMISS]; |
| 2492 |
cmp = &env->spr[SPR_PTEHI]; |
| 2493 |
} |
| 2494 |
qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " |
| 2495 |
TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
|
| 2496 |
env->error_code); |
| 2497 |
} |
| 2498 |
#endif
|
| 2499 |
msr |= env->error_code; /* key bit */
|
| 2500 |
break;
|
| 2501 |
default:
|
| 2502 |
cpu_abort(env, "Invalid data store TLB miss exception\n");
|
| 2503 |
break;
|
| 2504 |
} |
| 2505 |
goto store_next;
|
| 2506 |
case POWERPC_EXCP_FPA: /* Floating-point assist exception */ |
| 2507 |
/* XXX: TODO */
|
| 2508 |
cpu_abort(env, "Floating point assist exception "
|
| 2509 |
"is not implemented yet !\n");
|
| 2510 |
goto store_next;
|
| 2511 |
case POWERPC_EXCP_DABR: /* Data address breakpoint */ |
| 2512 |
/* XXX: TODO */
|
| 2513 |
cpu_abort(env, "DABR exception is not implemented yet !\n");
|
| 2514 |
goto store_next;
|
| 2515 |
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
| 2516 |
/* XXX: TODO */
|
| 2517 |
cpu_abort(env, "IABR exception is not implemented yet !\n");
|
| 2518 |
goto store_next;
|
| 2519 |
case POWERPC_EXCP_SMI: /* System management interrupt */ |
| 2520 |
/* XXX: TODO */
|
| 2521 |
cpu_abort(env, "SMI exception is not implemented yet !\n");
|
| 2522 |
goto store_next;
|
| 2523 |
case POWERPC_EXCP_THERM: /* Thermal interrupt */ |
| 2524 |
/* XXX: TODO */
|
| 2525 |
cpu_abort(env, "Thermal management exception "
|
| 2526 |
"is not implemented yet !\n");
|
| 2527 |
goto store_next;
|
| 2528 |
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ |
| 2529 |
new_msr &= ~((target_ulong)1 << MSR_RI);
|
| 2530 |
if (lpes1 == 0) |
| 2531 |
new_msr |= (target_ulong)MSR_HVB; |
| 2532 |
/* XXX: TODO */
|
| 2533 |
cpu_abort(env, |
| 2534 |
"Performance counter exception is not implemented yet !\n");
|
| 2535 |
goto store_next;
|
| 2536 |
case POWERPC_EXCP_VPUA: /* Vector assist exception */ |
| 2537 |
/* XXX: TODO */
|
| 2538 |
cpu_abort(env, "VPU assist exception is not implemented yet !\n");
|
| 2539 |
goto store_next;
|
| 2540 |
case POWERPC_EXCP_SOFTP: /* Soft patch exception */ |
| 2541 |
/* XXX: TODO */
|
| 2542 |
cpu_abort(env, |
| 2543 |
"970 soft-patch exception is not implemented yet !\n");
|
| 2544 |
goto store_next;
|
| 2545 |
case POWERPC_EXCP_MAINT: /* Maintenance exception */ |
| 2546 |
/* XXX: TODO */
|
| 2547 |
cpu_abort(env, |
| 2548 |
"970 maintenance exception is not implemented yet !\n");
|
| 2549 |
goto store_next;
|
| 2550 |
case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ |
| 2551 |
/* XXX: TODO */
|
| 2552 |
cpu_abort(env, "Maskable external exception "
|
| 2553 |
"is not implemented yet !\n");
|
| 2554 |
goto store_next;
|
| 2555 |
case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ |
| 2556 |
/* XXX: TODO */
|
| 2557 |
cpu_abort(env, "Non maskable external exception "
|
| 2558 |
"is not implemented yet !\n");
|
| 2559 |
goto store_next;
|
| 2560 |
default:
|
| 2561 |
excp_invalid:
|
| 2562 |
cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
|
| 2563 |
break;
|
| 2564 |
store_current:
|
| 2565 |
/* save current instruction location */
|
| 2566 |
env->spr[srr0] = env->nip - 4;
|
| 2567 |
break;
|
| 2568 |
store_next:
|
| 2569 |
/* save next instruction location */
|
| 2570 |
env->spr[srr0] = env->nip; |
| 2571 |
break;
|
| 2572 |
} |
| 2573 |
/* Save MSR */
|
| 2574 |
env->spr[srr1] = msr; |
| 2575 |
/* If any alternate SRR register are defined, duplicate saved values */
|
| 2576 |
if (asrr0 != -1) |
| 2577 |
env->spr[asrr0] = env->spr[srr0]; |
| 2578 |
if (asrr1 != -1) |
| 2579 |
env->spr[asrr1] = env->spr[srr1]; |
| 2580 |
/* If we disactivated any translation, flush TLBs */
|
| 2581 |
if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) |
| 2582 |
tlb_flush(env, 1);
|
| 2583 |
/* reload MSR with correct bits */
|
| 2584 |
new_msr &= ~((target_ulong)1 << MSR_EE);
|
| 2585 |
new_msr &= ~((target_ulong)1 << MSR_PR);
|
| 2586 |
new_msr &= ~((target_ulong)1 << MSR_FP);
|
| 2587 |
new_msr &= ~((target_ulong)1 << MSR_FE0);
|
| 2588 |
new_msr &= ~((target_ulong)1 << MSR_SE);
|
| 2589 |
new_msr &= ~((target_ulong)1 << MSR_BE);
|
| 2590 |
new_msr &= ~((target_ulong)1 << MSR_FE1);
|
| 2591 |
new_msr &= ~((target_ulong)1 << MSR_IR);
|
| 2592 |
new_msr &= ~((target_ulong)1 << MSR_DR);
|
| 2593 |
#if 0 /* Fix this: not on all targets */
|
| 2594 |
new_msr &= ~((target_ulong)1 << MSR_PMM);
|
| 2595 |
#endif
|
| 2596 |
new_msr &= ~((target_ulong)1 << MSR_LE);
|
| 2597 |
if (msr_ile)
|
| 2598 |
new_msr |= (target_ulong)1 << MSR_LE;
|
| 2599 |
else
|
| 2600 |
new_msr &= ~((target_ulong)1 << MSR_LE);
|
| 2601 |
/* Jump to handler */
|
| 2602 |
vector = env->excp_vectors[excp]; |
| 2603 |
if (vector == (target_ulong)-1ULL) { |
| 2604 |
cpu_abort(env, "Raised an exception without defined vector %d\n",
|
| 2605 |
excp); |
| 2606 |
} |
| 2607 |
vector |= env->excp_prefix; |
| 2608 |
#if defined(TARGET_PPC64)
|
| 2609 |
if (excp_model == POWERPC_EXCP_BOOKE) {
|
| 2610 |
if (!msr_icm) {
|
| 2611 |
new_msr &= ~((target_ulong)1 << MSR_CM);
|
| 2612 |
vector = (uint32_t)vector; |
| 2613 |
} else {
|
| 2614 |
new_msr |= (target_ulong)1 << MSR_CM;
|
| 2615 |
} |
| 2616 |
} else {
|
| 2617 |
if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
|
| 2618 |
new_msr &= ~((target_ulong)1 << MSR_SF);
|
| 2619 |
vector = (uint32_t)vector; |
| 2620 |
} else {
|
| 2621 |
new_msr |= (target_ulong)1 << MSR_SF;
|
| 2622 |
} |
| 2623 |
} |
| 2624 |
#endif
|
| 2625 |
/* XXX: we don't use hreg_store_msr here as already have treated
|
| 2626 |
* any special case that could occur. Just store MSR and update hflags
|
| 2627 |
*/
|
| 2628 |
env->msr = new_msr & env->msr_mask; |
| 2629 |
hreg_compute_hflags(env); |
| 2630 |
env->nip = vector; |
| 2631 |
/* Reset exception state */
|
| 2632 |
env->exception_index = POWERPC_EXCP_NONE; |
| 2633 |
env->error_code = 0;
|
| 2634 |
} |
| 2635 |
|
| 2636 |
void do_interrupt (CPUState *env)
|
| 2637 |
{
|
| 2638 |
powerpc_excp(env, env->excp_model, env->exception_index); |
| 2639 |
} |
| 2640 |
|
| 2641 |
void ppc_hw_interrupt (CPUPPCState *env)
|
| 2642 |
{
|
| 2643 |
int hdice;
|
| 2644 |
|
| 2645 |
#if 0
|
| 2646 |
qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
|
| 2647 |
__func__, env, env->pending_interrupts,
|
| 2648 |
env->interrupt_request, (int)msr_me, (int)msr_ee);
|
| 2649 |
#endif
|
| 2650 |
/* External reset */
|
| 2651 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
| 2652 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
|
| 2653 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); |
| 2654 |
return;
|
| 2655 |
} |
| 2656 |
/* Machine check exception */
|
| 2657 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { |
| 2658 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
|
| 2659 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); |
| 2660 |
return;
|
| 2661 |
} |
| 2662 |
#if 0 /* TODO */
|
| 2663 |
/* External debug exception */
|
| 2664 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
|
| 2665 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
|
| 2666 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
|
| 2667 |
return;
|
| 2668 |
}
|
| 2669 |
#endif
|
| 2670 |
if (0) { |
| 2671 |
/* XXX: find a suitable condition to enable the hypervisor mode */
|
| 2672 |
hdice = env->spr[SPR_LPCR] & 1;
|
| 2673 |
} else {
|
| 2674 |
hdice = 0;
|
| 2675 |
} |
| 2676 |
if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) { |
| 2677 |
/* Hypervisor decrementer exception */
|
| 2678 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { |
| 2679 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
|
| 2680 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); |
| 2681 |
return;
|
| 2682 |
} |
| 2683 |
} |
| 2684 |
if (msr_ce != 0) { |
| 2685 |
/* External critical interrupt */
|
| 2686 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { |
| 2687 |
/* Taking a critical external interrupt does not clear the external
|
| 2688 |
* critical interrupt status
|
| 2689 |
*/
|
| 2690 |
#if 0
|
| 2691 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
|
| 2692 |
#endif
|
| 2693 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); |
| 2694 |
return;
|
| 2695 |
} |
| 2696 |
} |
| 2697 |
if (msr_ee != 0) { |
| 2698 |
/* Watchdog timer on embedded PowerPC */
|
| 2699 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { |
| 2700 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
|
| 2701 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); |
| 2702 |
return;
|
| 2703 |
} |
| 2704 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { |
| 2705 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
|
| 2706 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); |
| 2707 |
return;
|
| 2708 |
} |
| 2709 |
/* Fixed interval timer on embedded PowerPC */
|
| 2710 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { |
| 2711 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
|
| 2712 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); |
| 2713 |
return;
|
| 2714 |
} |
| 2715 |
/* Programmable interval timer on embedded PowerPC */
|
| 2716 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { |
| 2717 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
|
| 2718 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); |
| 2719 |
return;
|
| 2720 |
} |
| 2721 |
/* Decrementer exception */
|
| 2722 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { |
| 2723 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
|
| 2724 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); |
| 2725 |
return;
|
| 2726 |
} |
| 2727 |
/* External interrupt */
|
| 2728 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
| 2729 |
/* Taking an external interrupt does not clear the external
|
| 2730 |
* interrupt status
|
| 2731 |
*/
|
| 2732 |
#if 0
|
| 2733 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
|
| 2734 |
#endif
|
| 2735 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
| 2736 |
return;
|
| 2737 |
} |
| 2738 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
| 2739 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
|
| 2740 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); |
| 2741 |
return;
|
| 2742 |
} |
| 2743 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
| 2744 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
|
| 2745 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); |
| 2746 |
return;
|
| 2747 |
} |
| 2748 |
/* Thermal interrupt */
|
| 2749 |
if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { |
| 2750 |
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
|
| 2751 |
powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); |
| 2752 |
return;
|
| 2753 |
} |
| 2754 |
} |
| 2755 |
} |
| 2756 |
#endif /* !CONFIG_USER_ONLY */ |
| 2757 |
|
| 2758 |
void cpu_dump_rfi (target_ulong RA, target_ulong msr)
|
| 2759 |
{
|
| 2760 |
qemu_log("Return from exception at " TARGET_FMT_lx " with flags " |
| 2761 |
TARGET_FMT_lx "\n", RA, msr);
|
| 2762 |
} |
| 2763 |
|
| 2764 |
void cpu_reset(CPUPPCState *env)
|
| 2765 |
{
|
| 2766 |
target_ulong msr; |
| 2767 |
|
| 2768 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
| 2769 |
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
| 2770 |
log_cpu_state(env, 0);
|
| 2771 |
} |
| 2772 |
|
| 2773 |
msr = (target_ulong)0;
|
| 2774 |
if (0) { |
| 2775 |
/* XXX: find a suitable condition to enable the hypervisor mode */
|
| 2776 |
msr |= (target_ulong)MSR_HVB; |
| 2777 |
} |
| 2778 |
msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ |
| 2779 |
msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ |
| 2780 |
msr |= (target_ulong)1 << MSR_EP;
|
| 2781 |
#if defined (DO_SINGLE_STEP) && 0 |
| 2782 |
/* Single step trace mode */
|
| 2783 |
msr |= (target_ulong)1 << MSR_SE;
|
| 2784 |
msr |= (target_ulong)1 << MSR_BE;
|
| 2785 |
#endif
|
| 2786 |
#if defined(CONFIG_USER_ONLY)
|
| 2787 |
msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ |
| 2788 |
msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ |
| 2789 |
msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ |
| 2790 |
msr |= (target_ulong)1 << MSR_PR;
|
| 2791 |
#else
|
| 2792 |
env->excp_prefix = env->hreset_excp_prefix; |
| 2793 |
env->nip = env->hreset_vector | env->excp_prefix; |
| 2794 |
if (env->mmu_model != POWERPC_MMU_REAL)
|
| 2795 |
ppc_tlb_invalidate_all(env); |
| 2796 |
#endif
|
| 2797 |
env->msr = msr & env->msr_mask; |
| 2798 |
#if defined(TARGET_PPC64)
|
| 2799 |
if (env->mmu_model & POWERPC_MMU_64)
|
| 2800 |
env->msr |= (1ULL << MSR_SF);
|
| 2801 |
#endif
|
| 2802 |
hreg_compute_hflags(env); |
| 2803 |
env->reserve_addr = (target_ulong)-1ULL;
|
| 2804 |
/* Be sure no exception or interrupt is pending */
|
| 2805 |
env->pending_interrupts = 0;
|
| 2806 |
env->exception_index = POWERPC_EXCP_NONE; |
| 2807 |
env->error_code = 0;
|
| 2808 |
/* Flush all TLBs */
|
| 2809 |
tlb_flush(env, 1);
|
| 2810 |
} |
| 2811 |
|
| 2812 |
CPUPPCState *cpu_ppc_init (const char *cpu_model) |
| 2813 |
{
|
| 2814 |
CPUPPCState *env; |
| 2815 |
const ppc_def_t *def;
|
| 2816 |
|
| 2817 |
def = cpu_ppc_find_by_name(cpu_model); |
| 2818 |
if (!def)
|
| 2819 |
return NULL; |
| 2820 |
|
| 2821 |
env = qemu_mallocz(sizeof(CPUPPCState));
|
| 2822 |
cpu_exec_init(env); |
| 2823 |
ppc_translate_init(); |
| 2824 |
env->cpu_model_str = cpu_model; |
| 2825 |
cpu_ppc_register_internal(env, def); |
| 2826 |
|
| 2827 |
qemu_init_vcpu(env); |
| 2828 |
|
| 2829 |
return env;
|
| 2830 |
} |
| 2831 |
|
| 2832 |
void cpu_ppc_close (CPUPPCState *env)
|
| 2833 |
{
|
| 2834 |
/* Should also remove all opcode tables... */
|
| 2835 |
qemu_free(env); |
| 2836 |
} |