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root / target-sparc @ c3d420ea

Name Size
TODO 2.2 kB
cpu.h 18.7 kB
exec.h 686 Bytes
helper.c 49 kB
helper.h 4.6 kB
machine.c 6 kB
op_helper.c 114 kB
translate.c 189.5 kB

Latest revisions

# Date Author Comment
da7ed379 05/30/2010 12:22 am Artyom Tarasenko

sparc32 SuperSPARC MMU Breakpoint Action register (SS-20 OBP fix)

SuperSPARC MMU Breakpoint Action register is used by OBP at boot

The patch allows booting Solaris and some other OS with
SPARCStation-20 OBP.

Signed-off-by: Artyom Tarasenko <>...
03ae77d6 05/29/2010 01:20 pm Blue Swirl

sparc64: fix user emulator build

Accesses with _nucleus prefix are not available when building user
emulators:
CC sparc64-linux-user/op_helper.o
cc1: warnings being treated as errors
/src/qemu/target-sparc/op_helper.c: In function 'helper_ldda_asi':...
54a3c0f0 05/29/2010 10:26 am Igor V. Kovalenko

sparc64: fix 128-bit atomic load from nucleus context v1

- change 128-bit atomic loads to reference nucleus context
v0->v1: dropped disassembler change
Signed-off-by: Igor V. Kovalenko <>
Signed-off-by: Blue Swirl <>
664a65b0 05/22/2010 03:52 pm Igor V. Kovalenko

sparc64: flush translations on mmu context change

- two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers
using value of DMMU primary and secondary context registers, so we need to
flush softmmu translations when context registers are changed...
9fd1ae3a 05/22/2010 03:51 pm Igor V. Kovalenko

sparc64: fix mmu context at trap levels above zero

- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero
- cpu_get_tb_cpu_state: store trap level and primary context in flags
this allows to restart code translation when address translation is changed...
e2129586 05/22/2010 03:50 pm Igor V. Kovalenko

sparc64: fix dump_mmu to look for global bit in tte value instead of tag

Signed-off-by: Igor V. Kovalenko <>
Signed-off-by: Blue Swirl <>
2aae2b8e 05/22/2010 03:48 pm Igor V. Kovalenko

sparc64: fix pstate privilege bits

- refactor code to handle hpstate only if available for current cpu
- conditionally set hypervisor bit in hpstate register
- reorder softmmu indices so user accessable ones go first, translation context
macros supervisor() and hypervisor() adjusted as well...
b8e9fc06 05/22/2010 03:34 pm Igor V. Kovalenko

sparc64: generate data access exception on RW violation

- separate PRIV and PROT handling
- DPRINTF_MMU macro to clean up debug code
- dump mmu_idx, trap level and mmu context registers
along with address translation values

Signed-off-by: Igor V. Kovalenko <>...
0bfcd599 05/22/2010 11:02 am Blue Swirl

Fix %lld or %llx printf format use

Signed-off-by: Blue Swirl <>
70c48285 05/20/2010 10:58 pm Richard Henderson

target-sparc: Inline some generation of carry for ADDX/SUBX.

Computing carry is trivial for some inputs. By avoiding an
external function call, we generate near-optimal code for
the common cases of add+addx (double-word arithmetic) and
cmp+addx (a setcc pattern)....

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