Revision c4374bb7 target-microblaze/cpu.h
b/target-microblaze/cpu.h | ||
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#define PVR0_USE_ICACHE_MASK 0x02000000 |
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#define PVR0_USE_DCACHE_MASK 0x01000000 |
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#define PVR0_USE_MMU 0x00800000 /* new */ |
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#define PVR0_USE_BTC 0x00400000 |
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#define PVR0_ENDI 0x00200000 |
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#define PVR0_FAULT 0x00100000 |
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#define PVR0_VERSION_MASK 0x0000FF00 |
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#define PVR0_USER1_MASK 0x000000FF |
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... | ... | |
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#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 |
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#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 |
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#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 |
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#define PVR5_DCACHE_WRITEBACK_MASK 0x00004000 |
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/* ICache base address PVR mask */ |
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#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF |
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