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1
/*
2
 * QEMU PPC PREP hardware System Emulator
3
 *
4
 * Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
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 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
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 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24
#include "vl.h"
25

    
26
//#define HARD_DEBUG_PPC_IO
27
//#define DEBUG_PPC_IO
28

    
29
/* SMP is not enabled, for now */
30
#define MAX_CPUS 1
31

    
32
#define BIOS_FILENAME "ppc_rom.bin"
33
#define KERNEL_LOAD_ADDR 0x01000000
34
#define INITRD_LOAD_ADDR 0x01800000
35

    
36
extern int loglevel;
37
extern FILE *logfile;
38

    
39
#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
40
#define DEBUG_PPC_IO
41
#endif
42

    
43
#if defined (HARD_DEBUG_PPC_IO)
44
#define PPC_IO_DPRINTF(fmt, args...)                     \
45
do {                                                     \
46
    if (loglevel & CPU_LOG_IOPORT) {                     \
47
        fprintf(logfile, "%s: " fmt, __func__ , ##args); \
48
    } else {                                             \
49
        printf("%s : " fmt, __func__ , ##args);          \
50
    }                                                    \
51
} while (0)
52
#elif defined (DEBUG_PPC_IO)
53
#define PPC_IO_DPRINTF(fmt, args...)                     \
54
do {                                                     \
55
    if (loglevel & CPU_LOG_IOPORT) {                     \
56
        fprintf(logfile, "%s: " fmt, __func__ , ##args); \
57
    }                                                    \
58
} while (0)
59
#else
60
#define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
61
#endif
62

    
63
/* Constants for devices init */
64
static const int ide_iobase[2] = { 0x1f0, 0x170 };
65
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
66
static const int ide_irq[2] = { 13, 13 };
67

    
68
#define NE2000_NB_MAX 6
69

    
70
static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
71
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
72

    
73
//static PITState *pit;
74

    
75
/* ISA IO ports bridge */
76
#define PPC_IO_BASE 0x80000000
77

    
78
/* Speaker port 0x61 */
79
int speaker_data_on;
80
int dummy_refresh_clock;
81

    
82
static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
83
{
84
#if 0
85
    speaker_data_on = (val >> 1) & 1;
86
    pit_set_gate(pit, 2, val & 1);
87
#endif
88
}
89

    
90
static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
91
{
92
#if 0
93
    int out;
94
    out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
95
    dummy_refresh_clock ^= 1;
96
    return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
97
        (dummy_refresh_clock << 4);
98
#endif
99
    return 0;
100
}
101

    
102
/* PCI intack register */
103
/* Read-only register (?) */
104
static void _PPC_intack_write (void *opaque,
105
                               target_phys_addr_t addr, uint32_t value)
106
{
107
    //    printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
108
}
109

    
110
static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
111
{
112
    uint32_t retval = 0;
113

    
114
    if (addr == 0xBFFFFFF0)
115
        retval = pic_intack_read(isa_pic);
116
    //   printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
117

    
118
    return retval;
119
}
120

    
121
static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
122
{
123
    return _PPC_intack_read(addr);
124
}
125

    
126
static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
127
{
128
#ifdef TARGET_WORDS_BIGENDIAN
129
    return bswap16(_PPC_intack_read(addr));
130
#else
131
    return _PPC_intack_read(addr);
132
#endif
133
}
134

    
135
static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
136
{
137
#ifdef TARGET_WORDS_BIGENDIAN
138
    return bswap32(_PPC_intack_read(addr));
139
#else
140
    return _PPC_intack_read(addr);
141
#endif
142
}
143

    
144
static CPUWriteMemoryFunc *PPC_intack_write[] = {
145
    &_PPC_intack_write,
146
    &_PPC_intack_write,
147
    &_PPC_intack_write,
148
};
149

    
150
static CPUReadMemoryFunc *PPC_intack_read[] = {
151
    &PPC_intack_readb,
152
    &PPC_intack_readw,
153
    &PPC_intack_readl,
154
};
155

    
156
/* PowerPC control and status registers */
157
#if 0 // Not used
158
static struct {
159
    /* IDs */
160
    uint32_t veni_devi;
161
    uint32_t revi;
162
    /* Control and status */
163
    uint32_t gcsr;
164
    uint32_t xcfr;
165
    uint32_t ct32;
166
    uint32_t mcsr;
167
    /* General purpose registers */
168
    uint32_t gprg[6];
169
    /* Exceptions */
170
    uint32_t feen;
171
    uint32_t fest;
172
    uint32_t fema;
173
    uint32_t fecl;
174
    uint32_t eeen;
175
    uint32_t eest;
176
    uint32_t eecl;
177
    uint32_t eeint;
178
    uint32_t eemck0;
179
    uint32_t eemck1;
180
    /* Error diagnostic */
181
} XCSR;
182

183
static void PPC_XCSR_writeb (void *opaque,
184
                             target_phys_addr_t addr, uint32_t value)
185
{
186
    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
187
}
188

189
static void PPC_XCSR_writew (void *opaque,
190
                             target_phys_addr_t addr, uint32_t value)
191
{
192
#ifdef TARGET_WORDS_BIGENDIAN
193
    value = bswap16(value);
194
#endif
195
    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
196
}
197

    
198
static void PPC_XCSR_writel (void *opaque,
199
                             target_phys_addr_t addr, uint32_t value)
200
{
201
#ifdef TARGET_WORDS_BIGENDIAN
202
    value = bswap32(value);
203
#endif
204
    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
205
}
206

    
207
static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
208
{
209
    uint32_t retval = 0;
210

    
211
    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
212

    
213
    return retval;
214
}
215

    
216
static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
217
{
218
    uint32_t retval = 0;
219

    
220
    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
221
#ifdef TARGET_WORDS_BIGENDIAN
222
    retval = bswap16(retval);
223
#endif
224

    
225
    return retval;
226
}
227

    
228
static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
229
{
230
    uint32_t retval = 0;
231

    
232
    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
233
#ifdef TARGET_WORDS_BIGENDIAN
234
    retval = bswap32(retval);
235
#endif
236

    
237
    return retval;
238
}
239

    
240
static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
241
    &PPC_XCSR_writeb,
242
    &PPC_XCSR_writew,
243
    &PPC_XCSR_writel,
244
};
245

    
246
static CPUReadMemoryFunc *PPC_XCSR_read[] = {
247
    &PPC_XCSR_readb,
248
    &PPC_XCSR_readw,
249
    &PPC_XCSR_readl,
250
};
251
#endif
252

    
253
/* Fake super-io ports for PREP platform (Intel 82378ZB) */
254
typedef struct sysctrl_t {
255
    qemu_irq reset_irq;
256
    m48t59_t *nvram;
257
    uint8_t state;
258
    uint8_t syscontrol;
259
    uint8_t fake_io[2];
260
    int contiguous_map;
261
    int endian;
262
} sysctrl_t;
263

    
264
enum {
265
    STATE_HARDFILE = 0x01,
266
};
267

    
268
static sysctrl_t *sysctrl;
269

    
270
static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
271
{
272
    sysctrl_t *sysctrl = opaque;
273

    
274
    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
275
    sysctrl->fake_io[addr - 0x0398] = val;
276
}
277

    
278
static uint32_t PREP_io_read (void *opaque, uint32_t addr)
279
{
280
    sysctrl_t *sysctrl = opaque;
281

    
282
    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
283
                   sysctrl->fake_io[addr - 0x0398]);
284
    return sysctrl->fake_io[addr - 0x0398];
285
}
286

    
287
static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
288
{
289
    sysctrl_t *sysctrl = opaque;
290

    
291
    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
292
    switch (addr) {
293
    case 0x0092:
294
        /* Special port 92 */
295
        /* Check soft reset asked */
296
        if (val & 0x01) {
297
            qemu_irq_raise(sysctrl->reset_irq);
298
        } else {
299
            qemu_irq_lower(sysctrl->reset_irq);
300
        }
301
        /* Check LE mode */
302
        if (val & 0x02) {
303
            sysctrl->endian = 1;
304
        } else {
305
            sysctrl->endian = 0;
306
        }
307
        break;
308
    case 0x0800:
309
        /* Motorola CPU configuration register : read-only */
310
        break;
311
    case 0x0802:
312
        /* Motorola base module feature register : read-only */
313
        break;
314
    case 0x0803:
315
        /* Motorola base module status register : read-only */
316
        break;
317
    case 0x0808:
318
        /* Hardfile light register */
319
        if (val & 1)
320
            sysctrl->state |= STATE_HARDFILE;
321
        else
322
            sysctrl->state &= ~STATE_HARDFILE;
323
        break;
324
    case 0x0810:
325
        /* Password protect 1 register */
326
        if (sysctrl->nvram != NULL)
327
            m48t59_toggle_lock(sysctrl->nvram, 1);
328
        break;
329
    case 0x0812:
330
        /* Password protect 2 register */
331
        if (sysctrl->nvram != NULL)
332
            m48t59_toggle_lock(sysctrl->nvram, 2);
333
        break;
334
    case 0x0814:
335
        /* L2 invalidate register */
336
        //        tlb_flush(first_cpu, 1);
337
        break;
338
    case 0x081C:
339
        /* system control register */
340
        sysctrl->syscontrol = val & 0x0F;
341
        break;
342
    case 0x0850:
343
        /* I/O map type register */
344
        sysctrl->contiguous_map = val & 0x01;
345
        break;
346
    default:
347
        printf("ERROR: unaffected IO port write: %04lx => %02x\n",
348
               (long)addr, val);
349
        break;
350
    }
351
}
352

    
353
static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
354
{
355
    sysctrl_t *sysctrl = opaque;
356
    uint32_t retval = 0xFF;
357

    
358
    switch (addr) {
359
    case 0x0092:
360
        /* Special port 92 */
361
        retval = 0x00;
362
        break;
363
    case 0x0800:
364
        /* Motorola CPU configuration register */
365
        retval = 0xEF; /* MPC750 */
366
        break;
367
    case 0x0802:
368
        /* Motorola Base module feature register */
369
        retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
370
        break;
371
    case 0x0803:
372
        /* Motorola base module status register */
373
        retval = 0xE0; /* Standard MPC750 */
374
        break;
375
    case 0x080C:
376
        /* Equipment present register:
377
         *  no L2 cache
378
         *  no upgrade processor
379
         *  no cards in PCI slots
380
         *  SCSI fuse is bad
381
         */
382
        retval = 0x3C;
383
        break;
384
    case 0x0810:
385
        /* Motorola base module extended feature register */
386
        retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
387
        break;
388
    case 0x0814:
389
        /* L2 invalidate: don't care */
390
        break;
391
    case 0x0818:
392
        /* Keylock */
393
        retval = 0x00;
394
        break;
395
    case 0x081C:
396
        /* system control register
397
         * 7 - 6 / 1 - 0: L2 cache enable
398
         */
399
        retval = sysctrl->syscontrol;
400
        break;
401
    case 0x0823:
402
        /* */
403
        retval = 0x03; /* no L2 cache */
404
        break;
405
    case 0x0850:
406
        /* I/O map type register */
407
        retval = sysctrl->contiguous_map;
408
        break;
409
    default:
410
        printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
411
        break;
412
    }
413
    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);
414

    
415
    return retval;
416
}
417

    
418
static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
419
                                                         target_phys_addr_t
420
                                                         addr)
421
{
422
    if (sysctrl->contiguous_map == 0) {
423
        /* 64 KB contiguous space for IOs */
424
        addr &= 0xFFFF;
425
    } else {
426
        /* 8 MB non-contiguous space for IOs */
427
        addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
428
    }
429

    
430
    return addr;
431
}
432

    
433
static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
434
                                uint32_t value)
435
{
436
    sysctrl_t *sysctrl = opaque;
437

    
438
    addr = prep_IO_address(sysctrl, addr);
439
    cpu_outb(NULL, addr, value);
440
}
441

    
442
static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
443
{
444
    sysctrl_t *sysctrl = opaque;
445
    uint32_t ret;
446

    
447
    addr = prep_IO_address(sysctrl, addr);
448
    ret = cpu_inb(NULL, addr);
449

    
450
    return ret;
451
}
452

    
453
static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
454
                                uint32_t value)
455
{
456
    sysctrl_t *sysctrl = opaque;
457

    
458
    addr = prep_IO_address(sysctrl, addr);
459
#ifdef TARGET_WORDS_BIGENDIAN
460
    value = bswap16(value);
461
#endif
462
    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
463
    cpu_outw(NULL, addr, value);
464
}
465

    
466
static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
467
{
468
    sysctrl_t *sysctrl = opaque;
469
    uint32_t ret;
470

    
471
    addr = prep_IO_address(sysctrl, addr);
472
    ret = cpu_inw(NULL, addr);
473
#ifdef TARGET_WORDS_BIGENDIAN
474
    ret = bswap16(ret);
475
#endif
476
    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
477

    
478
    return ret;
479
}
480

    
481
static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
482
                                uint32_t value)
483
{
484
    sysctrl_t *sysctrl = opaque;
485

    
486
    addr = prep_IO_address(sysctrl, addr);
487
#ifdef TARGET_WORDS_BIGENDIAN
488
    value = bswap32(value);
489
#endif
490
    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
491
    cpu_outl(NULL, addr, value);
492
}
493

    
494
static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
495
{
496
    sysctrl_t *sysctrl = opaque;
497
    uint32_t ret;
498

    
499
    addr = prep_IO_address(sysctrl, addr);
500
    ret = cpu_inl(NULL, addr);
501
#ifdef TARGET_WORDS_BIGENDIAN
502
    ret = bswap32(ret);
503
#endif
504
    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
505

    
506
    return ret;
507
}
508

    
509
CPUWriteMemoryFunc *PPC_prep_io_write[] = {
510
    &PPC_prep_io_writeb,
511
    &PPC_prep_io_writew,
512
    &PPC_prep_io_writel,
513
};
514

    
515
CPUReadMemoryFunc *PPC_prep_io_read[] = {
516
    &PPC_prep_io_readb,
517
    &PPC_prep_io_readw,
518
    &PPC_prep_io_readl,
519
};
520

    
521
#define NVRAM_SIZE        0x2000
522

    
523
/* PowerPC PREP hardware initialisation */
524
static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
525
                           DisplayState *ds, const char **fd_filename,
526
                           int snapshot, const char *kernel_filename,
527
                           const char *kernel_cmdline,
528
                           const char *initrd_filename,
529
                           const char *cpu_model)
530
{
531
    CPUState *env, *envs[MAX_CPUS];
532
    char buf[1024];
533
    nvram_t nvram;
534
    m48t59_t *m48t59;
535
    int PPC_io_memory;
536
    int linux_boot, i, nb_nics1, bios_size;
537
    unsigned long bios_offset;
538
    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
539
    ppc_def_t *def;
540
    PCIBus *pci_bus;
541
    qemu_irq *i8259;
542

    
543
    sysctrl = qemu_mallocz(sizeof(sysctrl_t));
544
    if (sysctrl == NULL)
545
        return;
546

    
547
    linux_boot = (kernel_filename != NULL);
548

    
549
    /* init CPUs */
550
    env = cpu_init();
551
    if (cpu_model == NULL)
552
        cpu_model = "default";
553
    ppc_find_by_name(cpu_model, &def);
554
    if (def == NULL) {
555
        cpu_abort(env, "Unable to find PowerPC CPU definition\n");
556
    }
557
    for (i = 0; i < smp_cpus; i++) {
558
        cpu_ppc_register(env, def);
559
        cpu_ppc_reset(env);
560
        /* Set time-base frequency to 100 Mhz */
561
        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
562
        qemu_register_reset(&cpu_ppc_reset, env);
563
        register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
564
        envs[i] = env;
565
    }
566

    
567
    /* allocate RAM */
568
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
569

    
570
    /* allocate and load BIOS */
571
    bios_offset = ram_size + vga_ram_size;
572
    if (bios_name == NULL)
573
        bios_name = BIOS_FILENAME;
574
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
575
    bios_size = load_image(buf, phys_ram_base + bios_offset);
576
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
577
        cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
578
        exit(1);
579
    }
580
    if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
581
        cpu_abort(env, "PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
582
    }
583
    bios_size = (bios_size + 0xfff) & ~0xfff;
584
    cpu_register_physical_memory((uint32_t)(-bios_size),
585
                                 bios_size, bios_offset | IO_MEM_ROM);
586

    
587
    if (linux_boot) {
588
        kernel_base = KERNEL_LOAD_ADDR;
589
        /* now we can load the kernel */
590
        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
591
        if (kernel_size < 0) {
592
            cpu_abort(env, "qemu: could not load kernel '%s'\n",
593
                      kernel_filename);
594
            exit(1);
595
        }
596
        /* load initrd */
597
        if (initrd_filename) {
598
            initrd_base = INITRD_LOAD_ADDR;
599
            initrd_size = load_image(initrd_filename,
600
                                     phys_ram_base + initrd_base);
601
            if (initrd_size < 0) {
602
                cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
603
                          initrd_filename);
604
                exit(1);
605
            }
606
        } else {
607
            initrd_base = 0;
608
            initrd_size = 0;
609
        }
610
        boot_device = 'm';
611
    } else {
612
        kernel_base = 0;
613
        kernel_size = 0;
614
        initrd_base = 0;
615
        initrd_size = 0;
616
    }
617

    
618
    isa_mem_base = 0xc0000000;
619
    if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
620
        cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
621
        exit(1);
622
    }
623
    i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
624
    pci_bus = pci_prep_init(i8259);
625
    //    pci_bus = i440fx_init();
626
    /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
627
    PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
628
                                           PPC_prep_io_write, sysctrl);
629
    cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
630

    
631
    /* init basic PC hardware */
632
    pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
633
                 vga_ram_size, 0, 0);
634
    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
635
    //    pit = pit_init(0x40, i8259[0]);
636
    rtc_init(0x70, i8259[8]);
637

    
638
    serial_init(0x3f8, i8259[4], serial_hds[0]);
639
    nb_nics1 = nb_nics;
640
    if (nb_nics1 > NE2000_NB_MAX)
641
        nb_nics1 = NE2000_NB_MAX;
642
    for(i = 0; i < nb_nics1; i++) {
643
        if (nd_table[i].model == NULL
644
            || strcmp(nd_table[i].model, "ne2k_isa") == 0) {
645
            isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
646
        } else {
647
            pci_nic_init(pci_bus, &nd_table[i], -1);
648
        }
649
    }
650

    
651
    for(i = 0; i < 2; i++) {
652
        isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
653
                     bs_table[2 * i], bs_table[2 * i + 1]);
654
    }
655
    i8042_init(i8259[1], i8259[12], 0x60);
656
    DMA_init(1);
657
    //    AUD_init();
658
    //    SB16_init();
659

    
660
    fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table);
661

    
662
    /* Register speaker port */
663
    register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
664
    register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
665
    /* Register fake IO ports for PREP */
666
    sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
667
    register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
668
    register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
669
    /* System control ports */
670
    register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
671
    register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
672
    register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
673
    register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
674
    /* PCI intack location */
675
    PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
676
                                           PPC_intack_write, NULL);
677
    cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
678
    /* PowerPC control and status register group */
679
#if 0
680
    PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
681
                                           NULL);
682
    cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
683
#endif
684

    
685
    if (usb_enabled) {
686
        usb_ohci_init_pci(pci_bus, 3, -1);
687
    }
688

    
689
    m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
690
    if (m48t59 == NULL)
691
        return;
692
    sysctrl->nvram = m48t59;
693

    
694
    /* Initialise NVRAM */
695
    nvram.opaque = m48t59;
696
    nvram.read_fn = &m48t59_read;
697
    nvram.write_fn = &m48t59_write;
698
    PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
699
                         kernel_base, kernel_size,
700
                         kernel_cmdline,
701
                         initrd_base, initrd_size,
702
                         /* XXX: need an option to load a NVRAM image */
703
                         0,
704
                         graphic_width, graphic_height, graphic_depth);
705

    
706
    /* Special port to get debug messages from Open-Firmware */
707
    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
708
}
709

    
710
QEMUMachine prep_machine = {
711
    "prep",
712
    "PowerPC PREP platform",
713
    ppc_prep_init,
714
};