Revision c48fcb47 target-sparc/helper.c
b/target-sparc/helper.c | ||
---|---|---|
30 | 30 |
|
31 | 31 |
//#define DEBUG_MMU |
32 | 32 |
|
33 |
typedef struct sparc_def_t sparc_def_t; |
|
34 |
|
|
35 |
struct sparc_def_t { |
|
36 |
const unsigned char *name; |
|
37 |
target_ulong iu_version; |
|
38 |
uint32_t fpu_version; |
|
39 |
uint32_t mmu_version; |
|
40 |
uint32_t mmu_bm; |
|
41 |
uint32_t mmu_ctpr_mask; |
|
42 |
uint32_t mmu_cxr_mask; |
|
43 |
uint32_t mmu_sfsr_mask; |
|
44 |
uint32_t mmu_trcr_mask; |
|
45 |
}; |
|
46 |
|
|
47 |
static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name); |
|
48 |
|
|
33 | 49 |
/* Sparc MMU emulation */ |
34 | 50 |
|
35 | 51 |
/* thread support */ |
... | ... | |
98 | 114 |
} |
99 | 115 |
}; |
100 | 116 |
|
101 |
int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
|
|
102 |
int *access_index, target_ulong address, int rw,
|
|
103 |
int mmu_idx) |
|
117 |
static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
|
|
118 |
int *prot, int *access_index,
|
|
119 |
target_ulong address, int rw, int mmu_idx)
|
|
104 | 120 |
{ |
105 | 121 |
int access_perms = 0; |
106 | 122 |
target_phys_addr_t pde_ptr; |
... | ... | |
483 | 499 |
return 1; |
484 | 500 |
} |
485 | 501 |
|
486 |
int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
|
|
487 |
int *access_index, target_ulong address, int rw,
|
|
488 |
int mmu_idx) |
|
502 |
static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
|
|
503 |
int *prot, int *access_index,
|
|
504 |
target_ulong address, int rw, int mmu_idx)
|
|
489 | 505 |
{ |
490 | 506 |
int is_user = mmu_idx == MMU_USER_IDX; |
491 | 507 |
|
... | ... | |
593 | 609 |
#endif /* TARGET_SPARC64 */ |
594 | 610 |
#endif /* !CONFIG_USER_ONLY */ |
595 | 611 |
|
612 |
|
|
613 |
#if defined(CONFIG_USER_ONLY) |
|
614 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
|
615 |
{ |
|
616 |
return addr; |
|
617 |
} |
|
618 |
|
|
619 |
#else |
|
620 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
|
621 |
{ |
|
622 |
target_phys_addr_t phys_addr; |
|
623 |
int prot, access_index; |
|
624 |
|
|
625 |
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
|
626 |
MMU_KERNEL_IDX) != 0) |
|
627 |
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, |
|
628 |
0, MMU_KERNEL_IDX) != 0) |
|
629 |
return -1; |
|
630 |
if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED) |
|
631 |
return -1; |
|
632 |
return phys_addr; |
|
633 |
} |
|
634 |
#endif |
|
635 |
|
|
596 | 636 |
void memcpy32(target_ulong *dst, const target_ulong *src) |
597 | 637 |
{ |
598 | 638 |
dst[0] = src[0]; |
... | ... | |
605 | 645 |
dst[7] = src[7]; |
606 | 646 |
} |
607 | 647 |
|
648 |
void helper_flush(target_ulong addr) |
|
649 |
{ |
|
650 |
addr &= ~7; |
|
651 |
tb_invalidate_page_range(addr, addr + 8); |
|
652 |
} |
|
653 |
|
|
654 |
void cpu_reset(CPUSPARCState *env) |
|
655 |
{ |
|
656 |
tlb_flush(env, 1); |
|
657 |
env->cwp = 0; |
|
658 |
env->wim = 1; |
|
659 |
env->regwptr = env->regbase + (env->cwp * 16); |
|
660 |
#if defined(CONFIG_USER_ONLY) |
|
661 |
env->user_mode_only = 1; |
|
662 |
#ifdef TARGET_SPARC64 |
|
663 |
env->cleanwin = NWINDOWS - 2; |
|
664 |
env->cansave = NWINDOWS - 2; |
|
665 |
env->pstate = PS_RMO | PS_PEF | PS_IE; |
|
666 |
env->asi = 0x82; // Primary no-fault |
|
667 |
#endif |
|
668 |
#else |
|
669 |
env->psret = 0; |
|
670 |
env->psrs = 1; |
|
671 |
env->psrps = 1; |
|
672 |
#ifdef TARGET_SPARC64 |
|
673 |
env->pstate = PS_PRIV; |
|
674 |
env->hpstate = HS_PRIV; |
|
675 |
env->pc = 0x1fff0000000ULL; |
|
676 |
env->tsptr = &env->ts[env->tl]; |
|
677 |
#else |
|
678 |
env->pc = 0; |
|
679 |
env->mmuregs[0] &= ~(MMU_E | MMU_NF); |
|
680 |
env->mmuregs[0] |= env->mmu_bm; |
|
681 |
#endif |
|
682 |
env->npc = env->pc + 4; |
|
683 |
#endif |
|
684 |
} |
|
685 |
|
|
686 |
CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
|
687 |
{ |
|
688 |
CPUSPARCState *env; |
|
689 |
const sparc_def_t *def; |
|
690 |
|
|
691 |
def = cpu_sparc_find_by_name(cpu_model); |
|
692 |
if (!def) |
|
693 |
return NULL; |
|
694 |
|
|
695 |
env = qemu_mallocz(sizeof(CPUSPARCState)); |
|
696 |
if (!env) |
|
697 |
return NULL; |
|
698 |
cpu_exec_init(env); |
|
699 |
env->cpu_model_str = cpu_model; |
|
700 |
env->version = def->iu_version; |
|
701 |
env->fsr = def->fpu_version; |
|
702 |
#if !defined(TARGET_SPARC64) |
|
703 |
env->mmu_bm = def->mmu_bm; |
|
704 |
env->mmu_ctpr_mask = def->mmu_ctpr_mask; |
|
705 |
env->mmu_cxr_mask = def->mmu_cxr_mask; |
|
706 |
env->mmu_sfsr_mask = def->mmu_sfsr_mask; |
|
707 |
env->mmu_trcr_mask = def->mmu_trcr_mask; |
|
708 |
env->mmuregs[0] |= def->mmu_version; |
|
709 |
cpu_sparc_set_id(env, 0); |
|
710 |
#endif |
|
711 |
|
|
712 |
gen_intermediate_code_init(env); |
|
713 |
|
|
714 |
cpu_reset(env); |
|
715 |
|
|
716 |
return env; |
|
717 |
} |
|
718 |
|
|
719 |
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
|
720 |
{ |
|
721 |
#if !defined(TARGET_SPARC64) |
|
722 |
env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
|
723 |
#endif |
|
724 |
} |
|
725 |
|
|
726 |
static const sparc_def_t sparc_defs[] = { |
|
727 |
#ifdef TARGET_SPARC64 |
|
728 |
{ |
|
729 |
.name = "Fujitsu Sparc64", |
|
730 |
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) |
|
731 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
732 |
.fpu_version = 0x00000000, |
|
733 |
.mmu_version = 0, |
|
734 |
}, |
|
735 |
{ |
|
736 |
.name = "Fujitsu Sparc64 III", |
|
737 |
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) |
|
738 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
739 |
.fpu_version = 0x00000000, |
|
740 |
.mmu_version = 0, |
|
741 |
}, |
|
742 |
{ |
|
743 |
.name = "Fujitsu Sparc64 IV", |
|
744 |
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) |
|
745 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
746 |
.fpu_version = 0x00000000, |
|
747 |
.mmu_version = 0, |
|
748 |
}, |
|
749 |
{ |
|
750 |
.name = "Fujitsu Sparc64 V", |
|
751 |
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) |
|
752 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
753 |
.fpu_version = 0x00000000, |
|
754 |
.mmu_version = 0, |
|
755 |
}, |
|
756 |
{ |
|
757 |
.name = "TI UltraSparc I", |
|
758 |
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
|
759 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
760 |
.fpu_version = 0x00000000, |
|
761 |
.mmu_version = 0, |
|
762 |
}, |
|
763 |
{ |
|
764 |
.name = "TI UltraSparc II", |
|
765 |
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) |
|
766 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
767 |
.fpu_version = 0x00000000, |
|
768 |
.mmu_version = 0, |
|
769 |
}, |
|
770 |
{ |
|
771 |
.name = "TI UltraSparc IIi", |
|
772 |
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) |
|
773 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
774 |
.fpu_version = 0x00000000, |
|
775 |
.mmu_version = 0, |
|
776 |
}, |
|
777 |
{ |
|
778 |
.name = "TI UltraSparc IIe", |
|
779 |
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) |
|
780 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
781 |
.fpu_version = 0x00000000, |
|
782 |
.mmu_version = 0, |
|
783 |
}, |
|
784 |
{ |
|
785 |
.name = "Sun UltraSparc III", |
|
786 |
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) |
|
787 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
788 |
.fpu_version = 0x00000000, |
|
789 |
.mmu_version = 0, |
|
790 |
}, |
|
791 |
{ |
|
792 |
.name = "Sun UltraSparc III Cu", |
|
793 |
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) |
|
794 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
795 |
.fpu_version = 0x00000000, |
|
796 |
.mmu_version = 0, |
|
797 |
}, |
|
798 |
{ |
|
799 |
.name = "Sun UltraSparc IIIi", |
|
800 |
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) |
|
801 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
802 |
.fpu_version = 0x00000000, |
|
803 |
.mmu_version = 0, |
|
804 |
}, |
|
805 |
{ |
|
806 |
.name = "Sun UltraSparc IV", |
|
807 |
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) |
|
808 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
809 |
.fpu_version = 0x00000000, |
|
810 |
.mmu_version = 0, |
|
811 |
}, |
|
812 |
{ |
|
813 |
.name = "Sun UltraSparc IV+", |
|
814 |
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) |
|
815 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
816 |
.fpu_version = 0x00000000, |
|
817 |
.mmu_version = 0, |
|
818 |
}, |
|
819 |
{ |
|
820 |
.name = "Sun UltraSparc IIIi+", |
|
821 |
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) |
|
822 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
823 |
.fpu_version = 0x00000000, |
|
824 |
.mmu_version = 0, |
|
825 |
}, |
|
826 |
{ |
|
827 |
.name = "NEC UltraSparc I", |
|
828 |
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
|
829 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
|
830 |
.fpu_version = 0x00000000, |
|
831 |
.mmu_version = 0, |
|
832 |
}, |
|
833 |
#else |
|
834 |
{ |
|
835 |
.name = "Fujitsu MB86900", |
|
836 |
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
|
837 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
|
838 |
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
|
839 |
.mmu_bm = 0x00004000, |
|
840 |
.mmu_ctpr_mask = 0x007ffff0, |
|
841 |
.mmu_cxr_mask = 0x0000003f, |
|
842 |
.mmu_sfsr_mask = 0xffffffff, |
|
843 |
.mmu_trcr_mask = 0xffffffff, |
|
844 |
}, |
|
845 |
{ |
|
846 |
.name = "Fujitsu MB86904", |
|
847 |
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
|
848 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
|
849 |
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
|
850 |
.mmu_bm = 0x00004000, |
|
851 |
.mmu_ctpr_mask = 0x00ffffc0, |
|
852 |
.mmu_cxr_mask = 0x000000ff, |
|
853 |
.mmu_sfsr_mask = 0x00016fff, |
|
854 |
.mmu_trcr_mask = 0x00ffffff, |
|
855 |
}, |
|
856 |
{ |
|
857 |
.name = "Fujitsu MB86907", |
|
858 |
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
|
859 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
|
860 |
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
|
861 |
.mmu_bm = 0x00004000, |
|
862 |
.mmu_ctpr_mask = 0xffffffc0, |
|
863 |
.mmu_cxr_mask = 0x000000ff, |
|
864 |
.mmu_sfsr_mask = 0x00016fff, |
|
865 |
.mmu_trcr_mask = 0xffffffff, |
|
866 |
}, |
|
867 |
{ |
|
868 |
.name = "LSI L64811", |
|
869 |
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
|
870 |
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
|
871 |
.mmu_version = 0x10 << 24, |
|
872 |
.mmu_bm = 0x00004000, |
|
873 |
.mmu_ctpr_mask = 0x007ffff0, |
|
874 |
.mmu_cxr_mask = 0x0000003f, |
|
875 |
.mmu_sfsr_mask = 0xffffffff, |
|
876 |
.mmu_trcr_mask = 0xffffffff, |
|
877 |
}, |
|
878 |
{ |
|
879 |
.name = "Cypress CY7C601", |
|
880 |
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
|
881 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
|
882 |
.mmu_version = 0x10 << 24, |
|
883 |
.mmu_bm = 0x00004000, |
|
884 |
.mmu_ctpr_mask = 0x007ffff0, |
|
885 |
.mmu_cxr_mask = 0x0000003f, |
|
886 |
.mmu_sfsr_mask = 0xffffffff, |
|
887 |
.mmu_trcr_mask = 0xffffffff, |
|
888 |
}, |
|
889 |
{ |
|
890 |
.name = "Cypress CY7C611", |
|
891 |
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
|
892 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
|
893 |
.mmu_version = 0x10 << 24, |
|
894 |
.mmu_bm = 0x00004000, |
|
895 |
.mmu_ctpr_mask = 0x007ffff0, |
|
896 |
.mmu_cxr_mask = 0x0000003f, |
|
897 |
.mmu_sfsr_mask = 0xffffffff, |
|
898 |
.mmu_trcr_mask = 0xffffffff, |
|
899 |
}, |
|
900 |
{ |
|
901 |
.name = "TI SuperSparc II", |
|
902 |
.iu_version = 0x40000000, |
|
903 |
.fpu_version = 0 << 17, |
|
904 |
.mmu_version = 0x04000000, |
|
905 |
.mmu_bm = 0x00002000, |
|
906 |
.mmu_ctpr_mask = 0xffffffc0, |
|
907 |
.mmu_cxr_mask = 0x0000ffff, |
|
908 |
.mmu_sfsr_mask = 0xffffffff, |
|
909 |
.mmu_trcr_mask = 0xffffffff, |
|
910 |
}, |
|
911 |
{ |
|
912 |
.name = "TI MicroSparc I", |
|
913 |
.iu_version = 0x41000000, |
|
914 |
.fpu_version = 4 << 17, |
|
915 |
.mmu_version = 0x41000000, |
|
916 |
.mmu_bm = 0x00004000, |
|
917 |
.mmu_ctpr_mask = 0x007ffff0, |
|
918 |
.mmu_cxr_mask = 0x0000003f, |
|
919 |
.mmu_sfsr_mask = 0x00016fff, |
|
920 |
.mmu_trcr_mask = 0x0000003f, |
|
921 |
}, |
|
922 |
{ |
|
923 |
.name = "TI MicroSparc II", |
|
924 |
.iu_version = 0x42000000, |
|
925 |
.fpu_version = 4 << 17, |
|
926 |
.mmu_version = 0x02000000, |
|
927 |
.mmu_bm = 0x00004000, |
|
928 |
.mmu_ctpr_mask = 0x00ffffc0, |
|
929 |
.mmu_cxr_mask = 0x000000ff, |
|
930 |
.mmu_sfsr_mask = 0x00016fff, |
|
931 |
.mmu_trcr_mask = 0x00ffffff, |
|
932 |
}, |
|
933 |
{ |
|
934 |
.name = "TI MicroSparc IIep", |
|
935 |
.iu_version = 0x42000000, |
|
936 |
.fpu_version = 4 << 17, |
|
937 |
.mmu_version = 0x04000000, |
|
938 |
.mmu_bm = 0x00004000, |
|
939 |
.mmu_ctpr_mask = 0x00ffffc0, |
|
940 |
.mmu_cxr_mask = 0x000000ff, |
|
941 |
.mmu_sfsr_mask = 0x00016bff, |
|
942 |
.mmu_trcr_mask = 0x00ffffff, |
|
943 |
}, |
|
944 |
{ |
|
945 |
.name = "TI SuperSparc 51", |
|
946 |
.iu_version = 0x43000000, |
|
947 |
.fpu_version = 0 << 17, |
|
948 |
.mmu_version = 0x04000000, |
|
949 |
.mmu_bm = 0x00002000, |
|
950 |
.mmu_ctpr_mask = 0xffffffc0, |
|
951 |
.mmu_cxr_mask = 0x0000ffff, |
|
952 |
.mmu_sfsr_mask = 0xffffffff, |
|
953 |
.mmu_trcr_mask = 0xffffffff, |
|
954 |
}, |
|
955 |
{ |
|
956 |
.name = "TI SuperSparc 61", |
|
957 |
.iu_version = 0x44000000, |
|
958 |
.fpu_version = 0 << 17, |
|
959 |
.mmu_version = 0x04000000, |
|
960 |
.mmu_bm = 0x00002000, |
|
961 |
.mmu_ctpr_mask = 0xffffffc0, |
|
962 |
.mmu_cxr_mask = 0x0000ffff, |
|
963 |
.mmu_sfsr_mask = 0xffffffff, |
|
964 |
.mmu_trcr_mask = 0xffffffff, |
|
965 |
}, |
|
966 |
{ |
|
967 |
.name = "Ross RT625", |
|
968 |
.iu_version = 0x1e000000, |
|
969 |
.fpu_version = 1 << 17, |
|
970 |
.mmu_version = 0x1e000000, |
|
971 |
.mmu_bm = 0x00004000, |
|
972 |
.mmu_ctpr_mask = 0x007ffff0, |
|
973 |
.mmu_cxr_mask = 0x0000003f, |
|
974 |
.mmu_sfsr_mask = 0xffffffff, |
|
975 |
.mmu_trcr_mask = 0xffffffff, |
|
976 |
}, |
|
977 |
{ |
|
978 |
.name = "Ross RT620", |
|
979 |
.iu_version = 0x1f000000, |
|
980 |
.fpu_version = 1 << 17, |
|
981 |
.mmu_version = 0x1f000000, |
|
982 |
.mmu_bm = 0x00004000, |
|
983 |
.mmu_ctpr_mask = 0x007ffff0, |
|
984 |
.mmu_cxr_mask = 0x0000003f, |
|
985 |
.mmu_sfsr_mask = 0xffffffff, |
|
986 |
.mmu_trcr_mask = 0xffffffff, |
|
987 |
}, |
|
988 |
{ |
|
989 |
.name = "BIT B5010", |
|
990 |
.iu_version = 0x20000000, |
|
991 |
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
|
992 |
.mmu_version = 0x20000000, |
|
993 |
.mmu_bm = 0x00004000, |
|
994 |
.mmu_ctpr_mask = 0x007ffff0, |
|
995 |
.mmu_cxr_mask = 0x0000003f, |
|
996 |
.mmu_sfsr_mask = 0xffffffff, |
|
997 |
.mmu_trcr_mask = 0xffffffff, |
|
998 |
}, |
|
999 |
{ |
|
1000 |
.name = "Matsushita MN10501", |
|
1001 |
.iu_version = 0x50000000, |
|
1002 |
.fpu_version = 0 << 17, |
|
1003 |
.mmu_version = 0x50000000, |
|
1004 |
.mmu_bm = 0x00004000, |
|
1005 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1006 |
.mmu_cxr_mask = 0x0000003f, |
|
1007 |
.mmu_sfsr_mask = 0xffffffff, |
|
1008 |
.mmu_trcr_mask = 0xffffffff, |
|
1009 |
}, |
|
1010 |
{ |
|
1011 |
.name = "Weitek W8601", |
|
1012 |
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
|
1013 |
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
|
1014 |
.mmu_version = 0x10 << 24, |
|
1015 |
.mmu_bm = 0x00004000, |
|
1016 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1017 |
.mmu_cxr_mask = 0x0000003f, |
|
1018 |
.mmu_sfsr_mask = 0xffffffff, |
|
1019 |
.mmu_trcr_mask = 0xffffffff, |
|
1020 |
}, |
|
1021 |
{ |
|
1022 |
.name = "LEON2", |
|
1023 |
.iu_version = 0xf2000000, |
|
1024 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
|
1025 |
.mmu_version = 0xf2000000, |
|
1026 |
.mmu_bm = 0x00004000, |
|
1027 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1028 |
.mmu_cxr_mask = 0x0000003f, |
|
1029 |
.mmu_sfsr_mask = 0xffffffff, |
|
1030 |
.mmu_trcr_mask = 0xffffffff, |
|
1031 |
}, |
|
1032 |
{ |
|
1033 |
.name = "LEON3", |
|
1034 |
.iu_version = 0xf3000000, |
|
1035 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
|
1036 |
.mmu_version = 0xf3000000, |
|
1037 |
.mmu_bm = 0x00004000, |
|
1038 |
.mmu_ctpr_mask = 0x007ffff0, |
|
1039 |
.mmu_cxr_mask = 0x0000003f, |
|
1040 |
.mmu_sfsr_mask = 0xffffffff, |
|
1041 |
.mmu_trcr_mask = 0xffffffff, |
|
1042 |
}, |
|
1043 |
#endif |
|
1044 |
}; |
|
1045 |
|
|
1046 |
static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name) |
|
1047 |
{ |
|
1048 |
unsigned int i; |
|
1049 |
|
|
1050 |
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
|
1051 |
if (strcasecmp(name, sparc_defs[i].name) == 0) { |
|
1052 |
return &sparc_defs[i]; |
|
1053 |
} |
|
1054 |
} |
|
1055 |
return NULL; |
|
1056 |
} |
|
1057 |
|
|
1058 |
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
|
1059 |
{ |
|
1060 |
unsigned int i; |
|
1061 |
|
|
1062 |
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
|
1063 |
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n", |
|
1064 |
sparc_defs[i].name, |
|
1065 |
sparc_defs[i].iu_version, |
|
1066 |
sparc_defs[i].fpu_version, |
|
1067 |
sparc_defs[i].mmu_version); |
|
1068 |
} |
|
1069 |
} |
|
1070 |
|
|
1071 |
#define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
|
1072 |
|
|
1073 |
void cpu_dump_state(CPUState *env, FILE *f, |
|
1074 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
|
1075 |
int flags) |
|
1076 |
{ |
|
1077 |
int i, x; |
|
1078 |
|
|
1079 |
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
|
1080 |
cpu_fprintf(f, "General Registers:\n"); |
|
1081 |
for (i = 0; i < 4; i++) |
|
1082 |
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
|
1083 |
cpu_fprintf(f, "\n"); |
|
1084 |
for (; i < 8; i++) |
|
1085 |
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
|
1086 |
cpu_fprintf(f, "\nCurrent Register Window:\n"); |
|
1087 |
for (x = 0; x < 3; x++) { |
|
1088 |
for (i = 0; i < 4; i++) |
|
1089 |
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
|
1090 |
(x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
|
1091 |
env->regwptr[i + x * 8]); |
|
1092 |
cpu_fprintf(f, "\n"); |
|
1093 |
for (; i < 8; i++) |
|
1094 |
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
|
1095 |
(x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
|
1096 |
env->regwptr[i + x * 8]); |
|
1097 |
cpu_fprintf(f, "\n"); |
|
1098 |
} |
|
1099 |
cpu_fprintf(f, "\nFloating Point Registers:\n"); |
|
1100 |
for (i = 0; i < 32; i++) { |
|
1101 |
if ((i & 3) == 0) |
|
1102 |
cpu_fprintf(f, "%%f%02d:", i); |
|
1103 |
cpu_fprintf(f, " %016lf", env->fpr[i]); |
|
1104 |
if ((i & 3) == 3) |
|
1105 |
cpu_fprintf(f, "\n"); |
|
1106 |
} |
|
1107 |
#ifdef TARGET_SPARC64 |
|
1108 |
cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n", |
|
1109 |
env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
|
1110 |
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n", |
|
1111 |
env->cansave, env->canrestore, env->otherwin, env->wstate, |
|
1112 |
env->cleanwin, NWINDOWS - 1 - env->cwp); |
|
1113 |
#else |
|
1114 |
cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env), |
|
1115 |
GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
|
1116 |
GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
|
1117 |
env->psrs?'S':'-', env->psrps?'P':'-', |
|
1118 |
env->psret?'E':'-', env->wim); |
|
1119 |
#endif |
|
1120 |
cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env)); |
|
1121 |
} |
|
1122 |
|
|
608 | 1123 |
#ifdef TARGET_SPARC64 |
609 | 1124 |
#if !defined(CONFIG_USER_ONLY) |
610 | 1125 |
#include "qemu-common.h" |
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