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/*
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* sparc helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include <assert.h> |
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|
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#include "cpu.h" |
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#include "exec-all.h" |
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|
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//#define DEBUG_MMU
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|
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typedef struct sparc_def_t sparc_def_t; |
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|
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struct sparc_def_t {
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const unsigned char *name; |
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target_ulong iu_version; |
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uint32_t fpu_version; |
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uint32_t mmu_version; |
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uint32_t mmu_bm; |
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uint32_t mmu_ctpr_mask; |
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uint32_t mmu_cxr_mask; |
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uint32_t mmu_sfsr_mask; |
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uint32_t mmu_trcr_mask; |
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}; |
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|
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static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name); |
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|
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/* Sparc MMU emulation */
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|
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/* thread support */
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|
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
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|
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void cpu_lock(void) |
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{
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spin_lock(&global_cpu_lock); |
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} |
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|
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void cpu_unlock(void) |
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{
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spin_unlock(&global_cpu_lock); |
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} |
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|
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#if defined(CONFIG_USER_ONLY)
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|
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int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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|
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#else
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|
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#ifndef TARGET_SPARC64
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/*
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* Sparc V8 Reference MMU (SRMMU)
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*/
|
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static const int access_table[8][8] = { |
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{ 0, 0, 0, 0, 2, 0, 3, 3 },
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{ 0, 0, 0, 0, 2, 0, 0, 0 },
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{ 2, 2, 0, 0, 0, 2, 3, 3 },
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{ 2, 2, 0, 0, 0, 2, 0, 0 },
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{ 2, 0, 2, 0, 2, 2, 3, 3 },
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{ 2, 0, 2, 0, 2, 0, 2, 0 },
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{ 2, 2, 2, 0, 2, 2, 3, 3 },
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{ 2, 2, 2, 0, 2, 2, 2, 0 }
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}; |
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|
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static const int perm_table[2][8] = { |
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{
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC |
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}, |
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{
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ, |
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0,
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0,
|
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} |
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}; |
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|
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static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
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int *prot, int *access_index, |
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target_ulong address, int rw, int mmu_idx) |
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{
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int access_perms = 0; |
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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target_ulong virt_addr; |
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int error_code = 0, is_dirty, is_user; |
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unsigned long page_offset; |
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|
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is_user = mmu_idx == MMU_USER_IDX; |
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virt_addr = address & TARGET_PAGE_MASK; |
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|
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
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// Boot mode: instruction fetches are taken from PROM
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if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) { |
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*physical = env->prom_addr | (address & 0x7ffffULL);
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*prot = PAGE_READ | PAGE_EXEC; |
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return 0; |
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} |
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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return 0; |
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} |
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|
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
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*physical = 0xffffffffffff0000ULL;
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|
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
|
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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|
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/* Ctx pde */
|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return 1 << 2; |
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case 2: /* L0 PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 4 << 2; |
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case 1: /* L0 PDE */ |
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (1 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (1 << 8) | (4 << 2); |
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case 1: /* L1 PDE */ |
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (2 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (2 << 8) | (4 << 2); |
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case 1: /* L2 PDE */ |
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (3 << 8) | (1 << 2); |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return (3 << 8) | (4 << 2); |
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case 2: /* L3 PTE */ |
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virt_addr = address & TARGET_PAGE_MASK; |
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page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
|
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} |
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break;
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case 2: /* L2 PTE */ |
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virt_addr = address & ~0x3ffff;
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page_offset = address & 0x3ffff;
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} |
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break;
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case 2: /* L1 PTE */ |
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virt_addr = address & ~0xffffff;
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page_offset = address & 0xffffff;
|
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} |
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} |
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|
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK; |
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if (is_dirty)
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pde |= PG_MODIFIED_MASK; |
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stl_phys_notdirty(pde_ptr, pde); |
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} |
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
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error_code = access_table[*access_index][access_perms]; |
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if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
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return error_code;
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|
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/* the page can be put in the TLB */
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*prot = perm_table[is_user][access_perms]; |
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if (!(pde & PG_MODIFIED_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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*prot &= ~PAGE_WRITE; |
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} |
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|
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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} |
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|
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/* Perform address translation */
|
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{
|
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target_phys_addr_t paddr; |
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target_ulong vaddr; |
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int error_code = 0, prot, ret = 0, access_index; |
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|
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); |
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if (error_code == 0) { |
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vaddr = address & TARGET_PAGE_MASK; |
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paddr &= TARGET_PAGE_MASK; |
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#ifdef DEBUG_MMU
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printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
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TARGET_FMT_lx "\n", address, paddr, vaddr);
|
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#endif
|
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
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return ret;
|
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} |
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|
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if (env->mmuregs[3]) /* Fault status register */ |
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
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env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
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env->mmuregs[4] = address; /* Fault address register */ |
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|
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
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// No fault mode: if a mapping is available, just override
|
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// permissions. If no mapping is available, redirect accesses to
|
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// neverland. Fake/overridden mappings will be flushed when
|
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// switching to normal mode.
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vaddr = address & TARGET_PAGE_MASK; |
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
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return ret;
|
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} else {
|
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
|
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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} |
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|
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target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
|
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{
|
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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|
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/* Context base + context number */
|
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pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
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(env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
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default:
|
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case 0: /* Invalid */ |
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case 2: /* PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 0; |
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case 1: /* L1 PDE */ |
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if (mmulev == 3) |
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return pde;
|
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
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default:
|
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case 0: /* Invalid */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L1 PTE */ |
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return pde;
|
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case 1: /* L2 PDE */ |
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if (mmulev == 2) |
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return pde;
|
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
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default:
|
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case 0: /* Invalid */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L2 PTE */ |
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return pde;
|
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case 1: /* L3 PDE */ |
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if (mmulev == 1) |
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return pde;
|
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
| 324 |
|
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switch (pde & PTE_ENTRYTYPE_MASK) {
|
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default:
|
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case 0: /* Invalid */ |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L3 PTE */ |
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return pde;
|
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} |
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} |
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} |
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} |
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return 0; |
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} |
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|
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#ifdef DEBUG_MMU
|
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void dump_mmu(CPUState *env)
|
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{
|
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target_ulong va, va1, va2; |
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unsigned int n, m, o; |
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target_phys_addr_t pde_ptr, pa; |
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uint32_t pde; |
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|
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printf("MMU dump:\n");
|
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
| 350 |
pde = ldl_phys(pde_ptr); |
| 351 |
printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
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(target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); |
| 353 |
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
| 354 |
pde = mmu_probe(env, va, 2);
|
| 355 |
if (pde) {
|
| 356 |
pa = cpu_get_phys_page_debug(env, va); |
| 357 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
| 358 |
" PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
| 359 |
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
| 360 |
pde = mmu_probe(env, va1, 1);
|
| 361 |
if (pde) {
|
| 362 |
pa = cpu_get_phys_page_debug(env, va1); |
| 363 |
printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
| 364 |
" PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
| 365 |
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
| 366 |
pde = mmu_probe(env, va2, 0);
|
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if (pde) {
|
| 368 |
pa = cpu_get_phys_page_debug(env, va2); |
| 369 |
printf(" VA: " TARGET_FMT_lx ", PA: " |
| 370 |
TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
| 371 |
va2, pa, pde); |
| 372 |
} |
| 373 |
} |
| 374 |
} |
| 375 |
} |
| 376 |
} |
| 377 |
} |
| 378 |
printf("MMU dump ends\n");
|
| 379 |
} |
| 380 |
#endif /* DEBUG_MMU */ |
| 381 |
|
| 382 |
#else /* !TARGET_SPARC64 */ |
| 383 |
/*
|
| 384 |
* UltraSparc IIi I/DMMUs
|
| 385 |
*/
|
| 386 |
static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot, |
| 387 |
int *access_index, target_ulong address, int rw, |
| 388 |
int is_user)
|
| 389 |
{
|
| 390 |
target_ulong mask; |
| 391 |
unsigned int i; |
| 392 |
|
| 393 |
if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
| 394 |
*physical = address; |
| 395 |
*prot = PAGE_READ | PAGE_WRITE; |
| 396 |
return 0; |
| 397 |
} |
| 398 |
|
| 399 |
for (i = 0; i < 64; i++) { |
| 400 |
switch ((env->dtlb_tte[i] >> 61) & 3) { |
| 401 |
default:
|
| 402 |
case 0x0: // 8k |
| 403 |
mask = 0xffffffffffffe000ULL;
|
| 404 |
break;
|
| 405 |
case 0x1: // 64k |
| 406 |
mask = 0xffffffffffff0000ULL;
|
| 407 |
break;
|
| 408 |
case 0x2: // 512k |
| 409 |
mask = 0xfffffffffff80000ULL;
|
| 410 |
break;
|
| 411 |
case 0x3: // 4M |
| 412 |
mask = 0xffffffffffc00000ULL;
|
| 413 |
break;
|
| 414 |
} |
| 415 |
// ctx match, vaddr match?
|
| 416 |
if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
| 417 |
(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
|
| 418 |
// valid, access ok?
|
| 419 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 || |
| 420 |
((env->dtlb_tte[i] & 0x4) && is_user) ||
|
| 421 |
(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { |
| 422 |
if (env->dmmuregs[3]) /* Fault status register */ |
| 423 |
env->dmmuregs[3] = 2; /* overflow (not read before another fault) */ |
| 424 |
env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
| 425 |
env->dmmuregs[4] = address; /* Fault address register */ |
| 426 |
env->exception_index = TT_DFAULT; |
| 427 |
#ifdef DEBUG_MMU
|
| 428 |
printf("DFAULT at 0x%" PRIx64 "\n", address); |
| 429 |
#endif
|
| 430 |
return 1; |
| 431 |
} |
| 432 |
*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
| 433 |
*prot = PAGE_READ; |
| 434 |
if (env->dtlb_tte[i] & 0x2) |
| 435 |
*prot |= PAGE_WRITE; |
| 436 |
return 0; |
| 437 |
} |
| 438 |
} |
| 439 |
#ifdef DEBUG_MMU
|
| 440 |
printf("DMISS at 0x%" PRIx64 "\n", address); |
| 441 |
#endif
|
| 442 |
env->exception_index = TT_DMISS; |
| 443 |
return 1; |
| 444 |
} |
| 445 |
|
| 446 |
static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot, |
| 447 |
int *access_index, target_ulong address, int rw, |
| 448 |
int is_user)
|
| 449 |
{
|
| 450 |
target_ulong mask; |
| 451 |
unsigned int i; |
| 452 |
|
| 453 |
if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ |
| 454 |
*physical = address; |
| 455 |
*prot = PAGE_EXEC; |
| 456 |
return 0; |
| 457 |
} |
| 458 |
|
| 459 |
for (i = 0; i < 64; i++) { |
| 460 |
switch ((env->itlb_tte[i] >> 61) & 3) { |
| 461 |
default:
|
| 462 |
case 0x0: // 8k |
| 463 |
mask = 0xffffffffffffe000ULL;
|
| 464 |
break;
|
| 465 |
case 0x1: // 64k |
| 466 |
mask = 0xffffffffffff0000ULL;
|
| 467 |
break;
|
| 468 |
case 0x2: // 512k |
| 469 |
mask = 0xfffffffffff80000ULL;
|
| 470 |
break;
|
| 471 |
case 0x3: // 4M |
| 472 |
mask = 0xffffffffffc00000ULL;
|
| 473 |
break;
|
| 474 |
} |
| 475 |
// ctx match, vaddr match?
|
| 476 |
if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
| 477 |
(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
|
| 478 |
// valid, access ok?
|
| 479 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 || |
| 480 |
((env->itlb_tte[i] & 0x4) && is_user)) {
|
| 481 |
if (env->immuregs[3]) /* Fault status register */ |
| 482 |
env->immuregs[3] = 2; /* overflow (not read before another fault) */ |
| 483 |
env->immuregs[3] |= (is_user << 3) | 1; |
| 484 |
env->exception_index = TT_TFAULT; |
| 485 |
#ifdef DEBUG_MMU
|
| 486 |
printf("TFAULT at 0x%" PRIx64 "\n", address); |
| 487 |
#endif
|
| 488 |
return 1; |
| 489 |
} |
| 490 |
*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL); |
| 491 |
*prot = PAGE_EXEC; |
| 492 |
return 0; |
| 493 |
} |
| 494 |
} |
| 495 |
#ifdef DEBUG_MMU
|
| 496 |
printf("TMISS at 0x%" PRIx64 "\n", address); |
| 497 |
#endif
|
| 498 |
env->exception_index = TT_TMISS; |
| 499 |
return 1; |
| 500 |
} |
| 501 |
|
| 502 |
static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
| 503 |
int *prot, int *access_index, |
| 504 |
target_ulong address, int rw, int mmu_idx) |
| 505 |
{
|
| 506 |
int is_user = mmu_idx == MMU_USER_IDX;
|
| 507 |
|
| 508 |
if (rw == 2) |
| 509 |
return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
|
| 510 |
else
|
| 511 |
return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
|
| 512 |
} |
| 513 |
|
| 514 |
/* Perform address translation */
|
| 515 |
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 516 |
int mmu_idx, int is_softmmu) |
| 517 |
{
|
| 518 |
target_ulong virt_addr, vaddr; |
| 519 |
target_phys_addr_t paddr; |
| 520 |
int error_code = 0, prot, ret = 0, access_index; |
| 521 |
|
| 522 |
error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx); |
| 523 |
if (error_code == 0) { |
| 524 |
virt_addr = address & TARGET_PAGE_MASK; |
| 525 |
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
|
| 526 |
#ifdef DEBUG_MMU
|
| 527 |
printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr); |
| 528 |
#endif
|
| 529 |
ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
| 530 |
return ret;
|
| 531 |
} |
| 532 |
// XXX
|
| 533 |
return 1; |
| 534 |
} |
| 535 |
|
| 536 |
#ifdef DEBUG_MMU
|
| 537 |
void dump_mmu(CPUState *env)
|
| 538 |
{
|
| 539 |
unsigned int i; |
| 540 |
const char *mask; |
| 541 |
|
| 542 |
printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]); |
| 543 |
if ((env->lsu & DMMU_E) == 0) { |
| 544 |
printf("DMMU disabled\n");
|
| 545 |
} else {
|
| 546 |
printf("DMMU dump:\n");
|
| 547 |
for (i = 0; i < 64; i++) { |
| 548 |
switch ((env->dtlb_tte[i] >> 61) & 3) { |
| 549 |
default:
|
| 550 |
case 0x0: |
| 551 |
mask = " 8k";
|
| 552 |
break;
|
| 553 |
case 0x1: |
| 554 |
mask = " 64k";
|
| 555 |
break;
|
| 556 |
case 0x2: |
| 557 |
mask = "512k";
|
| 558 |
break;
|
| 559 |
case 0x3: |
| 560 |
mask = " 4M";
|
| 561 |
break;
|
| 562 |
} |
| 563 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { |
| 564 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n", |
| 565 |
env->dtlb_tag[i] & ~0x1fffULL,
|
| 566 |
env->dtlb_tte[i] & 0x1ffffffe000ULL,
|
| 567 |
mask, |
| 568 |
env->dtlb_tte[i] & 0x4? "priv": "user", |
| 569 |
env->dtlb_tte[i] & 0x2? "RW": "RO", |
| 570 |
env->dtlb_tte[i] & 0x40? "locked": "unlocked", |
| 571 |
env->dtlb_tag[i] & 0x1fffULL);
|
| 572 |
} |
| 573 |
} |
| 574 |
} |
| 575 |
if ((env->lsu & IMMU_E) == 0) { |
| 576 |
printf("IMMU disabled\n");
|
| 577 |
} else {
|
| 578 |
printf("IMMU dump:\n");
|
| 579 |
for (i = 0; i < 64; i++) { |
| 580 |
switch ((env->itlb_tte[i] >> 61) & 3) { |
| 581 |
default:
|
| 582 |
case 0x0: |
| 583 |
mask = " 8k";
|
| 584 |
break;
|
| 585 |
case 0x1: |
| 586 |
mask = " 64k";
|
| 587 |
break;
|
| 588 |
case 0x2: |
| 589 |
mask = "512k";
|
| 590 |
break;
|
| 591 |
case 0x3: |
| 592 |
mask = " 4M";
|
| 593 |
break;
|
| 594 |
} |
| 595 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { |
| 596 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n", |
| 597 |
env->itlb_tag[i] & ~0x1fffULL,
|
| 598 |
env->itlb_tte[i] & 0x1ffffffe000ULL,
|
| 599 |
mask, |
| 600 |
env->itlb_tte[i] & 0x4? "priv": "user", |
| 601 |
env->itlb_tte[i] & 0x40? "locked": "unlocked", |
| 602 |
env->itlb_tag[i] & 0x1fffULL);
|
| 603 |
} |
| 604 |
} |
| 605 |
} |
| 606 |
} |
| 607 |
#endif /* DEBUG_MMU */ |
| 608 |
|
| 609 |
#endif /* TARGET_SPARC64 */ |
| 610 |
#endif /* !CONFIG_USER_ONLY */ |
| 611 |
|
| 612 |
|
| 613 |
#if defined(CONFIG_USER_ONLY)
|
| 614 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
| 615 |
{
|
| 616 |
return addr;
|
| 617 |
} |
| 618 |
|
| 619 |
#else
|
| 620 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
| 621 |
{
|
| 622 |
target_phys_addr_t phys_addr; |
| 623 |
int prot, access_index;
|
| 624 |
|
| 625 |
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
| 626 |
MMU_KERNEL_IDX) != 0)
|
| 627 |
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
|
| 628 |
0, MMU_KERNEL_IDX) != 0) |
| 629 |
return -1; |
| 630 |
if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
| 631 |
return -1; |
| 632 |
return phys_addr;
|
| 633 |
} |
| 634 |
#endif
|
| 635 |
|
| 636 |
void memcpy32(target_ulong *dst, const target_ulong *src) |
| 637 |
{
|
| 638 |
dst[0] = src[0]; |
| 639 |
dst[1] = src[1]; |
| 640 |
dst[2] = src[2]; |
| 641 |
dst[3] = src[3]; |
| 642 |
dst[4] = src[4]; |
| 643 |
dst[5] = src[5]; |
| 644 |
dst[6] = src[6]; |
| 645 |
dst[7] = src[7]; |
| 646 |
} |
| 647 |
|
| 648 |
void helper_flush(target_ulong addr)
|
| 649 |
{
|
| 650 |
addr &= ~7;
|
| 651 |
tb_invalidate_page_range(addr, addr + 8);
|
| 652 |
} |
| 653 |
|
| 654 |
void cpu_reset(CPUSPARCState *env)
|
| 655 |
{
|
| 656 |
tlb_flush(env, 1);
|
| 657 |
env->cwp = 0;
|
| 658 |
env->wim = 1;
|
| 659 |
env->regwptr = env->regbase + (env->cwp * 16);
|
| 660 |
#if defined(CONFIG_USER_ONLY)
|
| 661 |
env->user_mode_only = 1;
|
| 662 |
#ifdef TARGET_SPARC64
|
| 663 |
env->cleanwin = NWINDOWS - 2;
|
| 664 |
env->cansave = NWINDOWS - 2;
|
| 665 |
env->pstate = PS_RMO | PS_PEF | PS_IE; |
| 666 |
env->asi = 0x82; // Primary no-fault |
| 667 |
#endif
|
| 668 |
#else
|
| 669 |
env->psret = 0;
|
| 670 |
env->psrs = 1;
|
| 671 |
env->psrps = 1;
|
| 672 |
#ifdef TARGET_SPARC64
|
| 673 |
env->pstate = PS_PRIV; |
| 674 |
env->hpstate = HS_PRIV; |
| 675 |
env->pc = 0x1fff0000000ULL;
|
| 676 |
env->tsptr = &env->ts[env->tl]; |
| 677 |
#else
|
| 678 |
env->pc = 0;
|
| 679 |
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
| 680 |
env->mmuregs[0] |= env->mmu_bm;
|
| 681 |
#endif
|
| 682 |
env->npc = env->pc + 4;
|
| 683 |
#endif
|
| 684 |
} |
| 685 |
|
| 686 |
CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
| 687 |
{
|
| 688 |
CPUSPARCState *env; |
| 689 |
const sparc_def_t *def;
|
| 690 |
|
| 691 |
def = cpu_sparc_find_by_name(cpu_model); |
| 692 |
if (!def)
|
| 693 |
return NULL; |
| 694 |
|
| 695 |
env = qemu_mallocz(sizeof(CPUSPARCState));
|
| 696 |
if (!env)
|
| 697 |
return NULL; |
| 698 |
cpu_exec_init(env); |
| 699 |
env->cpu_model_str = cpu_model; |
| 700 |
env->version = def->iu_version; |
| 701 |
env->fsr = def->fpu_version; |
| 702 |
#if !defined(TARGET_SPARC64)
|
| 703 |
env->mmu_bm = def->mmu_bm; |
| 704 |
env->mmu_ctpr_mask = def->mmu_ctpr_mask; |
| 705 |
env->mmu_cxr_mask = def->mmu_cxr_mask; |
| 706 |
env->mmu_sfsr_mask = def->mmu_sfsr_mask; |
| 707 |
env->mmu_trcr_mask = def->mmu_trcr_mask; |
| 708 |
env->mmuregs[0] |= def->mmu_version;
|
| 709 |
cpu_sparc_set_id(env, 0);
|
| 710 |
#endif
|
| 711 |
|
| 712 |
gen_intermediate_code_init(env); |
| 713 |
|
| 714 |
cpu_reset(env); |
| 715 |
|
| 716 |
return env;
|
| 717 |
} |
| 718 |
|
| 719 |
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
| 720 |
{
|
| 721 |
#if !defined(TARGET_SPARC64)
|
| 722 |
env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
| 723 |
#endif
|
| 724 |
} |
| 725 |
|
| 726 |
static const sparc_def_t sparc_defs[] = { |
| 727 |
#ifdef TARGET_SPARC64
|
| 728 |
{
|
| 729 |
.name = "Fujitsu Sparc64",
|
| 730 |
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24) |
| 731 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 732 |
.fpu_version = 0x00000000,
|
| 733 |
.mmu_version = 0,
|
| 734 |
}, |
| 735 |
{
|
| 736 |
.name = "Fujitsu Sparc64 III",
|
| 737 |
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24) |
| 738 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 739 |
.fpu_version = 0x00000000,
|
| 740 |
.mmu_version = 0,
|
| 741 |
}, |
| 742 |
{
|
| 743 |
.name = "Fujitsu Sparc64 IV",
|
| 744 |
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24) |
| 745 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 746 |
.fpu_version = 0x00000000,
|
| 747 |
.mmu_version = 0,
|
| 748 |
}, |
| 749 |
{
|
| 750 |
.name = "Fujitsu Sparc64 V",
|
| 751 |
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24) |
| 752 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 753 |
.fpu_version = 0x00000000,
|
| 754 |
.mmu_version = 0,
|
| 755 |
}, |
| 756 |
{
|
| 757 |
.name = "TI UltraSparc I",
|
| 758 |
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
| 759 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 760 |
.fpu_version = 0x00000000,
|
| 761 |
.mmu_version = 0,
|
| 762 |
}, |
| 763 |
{
|
| 764 |
.name = "TI UltraSparc II",
|
| 765 |
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24) |
| 766 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 767 |
.fpu_version = 0x00000000,
|
| 768 |
.mmu_version = 0,
|
| 769 |
}, |
| 770 |
{
|
| 771 |
.name = "TI UltraSparc IIi",
|
| 772 |
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24) |
| 773 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 774 |
.fpu_version = 0x00000000,
|
| 775 |
.mmu_version = 0,
|
| 776 |
}, |
| 777 |
{
|
| 778 |
.name = "TI UltraSparc IIe",
|
| 779 |
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24) |
| 780 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 781 |
.fpu_version = 0x00000000,
|
| 782 |
.mmu_version = 0,
|
| 783 |
}, |
| 784 |
{
|
| 785 |
.name = "Sun UltraSparc III",
|
| 786 |
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24) |
| 787 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 788 |
.fpu_version = 0x00000000,
|
| 789 |
.mmu_version = 0,
|
| 790 |
}, |
| 791 |
{
|
| 792 |
.name = "Sun UltraSparc III Cu",
|
| 793 |
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24) |
| 794 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 795 |
.fpu_version = 0x00000000,
|
| 796 |
.mmu_version = 0,
|
| 797 |
}, |
| 798 |
{
|
| 799 |
.name = "Sun UltraSparc IIIi",
|
| 800 |
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24) |
| 801 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 802 |
.fpu_version = 0x00000000,
|
| 803 |
.mmu_version = 0,
|
| 804 |
}, |
| 805 |
{
|
| 806 |
.name = "Sun UltraSparc IV",
|
| 807 |
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24) |
| 808 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 809 |
.fpu_version = 0x00000000,
|
| 810 |
.mmu_version = 0,
|
| 811 |
}, |
| 812 |
{
|
| 813 |
.name = "Sun UltraSparc IV+",
|
| 814 |
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24) |
| 815 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 816 |
.fpu_version = 0x00000000,
|
| 817 |
.mmu_version = 0,
|
| 818 |
}, |
| 819 |
{
|
| 820 |
.name = "Sun UltraSparc IIIi+",
|
| 821 |
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24) |
| 822 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 823 |
.fpu_version = 0x00000000,
|
| 824 |
.mmu_version = 0,
|
| 825 |
}, |
| 826 |
{
|
| 827 |
.name = "NEC UltraSparc I",
|
| 828 |
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24) |
| 829 |
| (MAXTL << 8) | (NWINDOWS - 1)), |
| 830 |
.fpu_version = 0x00000000,
|
| 831 |
.mmu_version = 0,
|
| 832 |
}, |
| 833 |
#else
|
| 834 |
{
|
| 835 |
.name = "Fujitsu MB86900",
|
| 836 |
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
| 837 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
| 838 |
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
| 839 |
.mmu_bm = 0x00004000,
|
| 840 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 841 |
.mmu_cxr_mask = 0x0000003f,
|
| 842 |
.mmu_sfsr_mask = 0xffffffff,
|
| 843 |
.mmu_trcr_mask = 0xffffffff,
|
| 844 |
}, |
| 845 |
{
|
| 846 |
.name = "Fujitsu MB86904",
|
| 847 |
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
| 848 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
| 849 |
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
| 850 |
.mmu_bm = 0x00004000,
|
| 851 |
.mmu_ctpr_mask = 0x00ffffc0,
|
| 852 |
.mmu_cxr_mask = 0x000000ff,
|
| 853 |
.mmu_sfsr_mask = 0x00016fff,
|
| 854 |
.mmu_trcr_mask = 0x00ffffff,
|
| 855 |
}, |
| 856 |
{
|
| 857 |
.name = "Fujitsu MB86907",
|
| 858 |
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
| 859 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
| 860 |
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
| 861 |
.mmu_bm = 0x00004000,
|
| 862 |
.mmu_ctpr_mask = 0xffffffc0,
|
| 863 |
.mmu_cxr_mask = 0x000000ff,
|
| 864 |
.mmu_sfsr_mask = 0x00016fff,
|
| 865 |
.mmu_trcr_mask = 0xffffffff,
|
| 866 |
}, |
| 867 |
{
|
| 868 |
.name = "LSI L64811",
|
| 869 |
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
| 870 |
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
| 871 |
.mmu_version = 0x10 << 24, |
| 872 |
.mmu_bm = 0x00004000,
|
| 873 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 874 |
.mmu_cxr_mask = 0x0000003f,
|
| 875 |
.mmu_sfsr_mask = 0xffffffff,
|
| 876 |
.mmu_trcr_mask = 0xffffffff,
|
| 877 |
}, |
| 878 |
{
|
| 879 |
.name = "Cypress CY7C601",
|
| 880 |
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
| 881 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
| 882 |
.mmu_version = 0x10 << 24, |
| 883 |
.mmu_bm = 0x00004000,
|
| 884 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 885 |
.mmu_cxr_mask = 0x0000003f,
|
| 886 |
.mmu_sfsr_mask = 0xffffffff,
|
| 887 |
.mmu_trcr_mask = 0xffffffff,
|
| 888 |
}, |
| 889 |
{
|
| 890 |
.name = "Cypress CY7C611",
|
| 891 |
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
| 892 |
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
| 893 |
.mmu_version = 0x10 << 24, |
| 894 |
.mmu_bm = 0x00004000,
|
| 895 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 896 |
.mmu_cxr_mask = 0x0000003f,
|
| 897 |
.mmu_sfsr_mask = 0xffffffff,
|
| 898 |
.mmu_trcr_mask = 0xffffffff,
|
| 899 |
}, |
| 900 |
{
|
| 901 |
.name = "TI SuperSparc II",
|
| 902 |
.iu_version = 0x40000000,
|
| 903 |
.fpu_version = 0 << 17, |
| 904 |
.mmu_version = 0x04000000,
|
| 905 |
.mmu_bm = 0x00002000,
|
| 906 |
.mmu_ctpr_mask = 0xffffffc0,
|
| 907 |
.mmu_cxr_mask = 0x0000ffff,
|
| 908 |
.mmu_sfsr_mask = 0xffffffff,
|
| 909 |
.mmu_trcr_mask = 0xffffffff,
|
| 910 |
}, |
| 911 |
{
|
| 912 |
.name = "TI MicroSparc I",
|
| 913 |
.iu_version = 0x41000000,
|
| 914 |
.fpu_version = 4 << 17, |
| 915 |
.mmu_version = 0x41000000,
|
| 916 |
.mmu_bm = 0x00004000,
|
| 917 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 918 |
.mmu_cxr_mask = 0x0000003f,
|
| 919 |
.mmu_sfsr_mask = 0x00016fff,
|
| 920 |
.mmu_trcr_mask = 0x0000003f,
|
| 921 |
}, |
| 922 |
{
|
| 923 |
.name = "TI MicroSparc II",
|
| 924 |
.iu_version = 0x42000000,
|
| 925 |
.fpu_version = 4 << 17, |
| 926 |
.mmu_version = 0x02000000,
|
| 927 |
.mmu_bm = 0x00004000,
|
| 928 |
.mmu_ctpr_mask = 0x00ffffc0,
|
| 929 |
.mmu_cxr_mask = 0x000000ff,
|
| 930 |
.mmu_sfsr_mask = 0x00016fff,
|
| 931 |
.mmu_trcr_mask = 0x00ffffff,
|
| 932 |
}, |
| 933 |
{
|
| 934 |
.name = "TI MicroSparc IIep",
|
| 935 |
.iu_version = 0x42000000,
|
| 936 |
.fpu_version = 4 << 17, |
| 937 |
.mmu_version = 0x04000000,
|
| 938 |
.mmu_bm = 0x00004000,
|
| 939 |
.mmu_ctpr_mask = 0x00ffffc0,
|
| 940 |
.mmu_cxr_mask = 0x000000ff,
|
| 941 |
.mmu_sfsr_mask = 0x00016bff,
|
| 942 |
.mmu_trcr_mask = 0x00ffffff,
|
| 943 |
}, |
| 944 |
{
|
| 945 |
.name = "TI SuperSparc 51",
|
| 946 |
.iu_version = 0x43000000,
|
| 947 |
.fpu_version = 0 << 17, |
| 948 |
.mmu_version = 0x04000000,
|
| 949 |
.mmu_bm = 0x00002000,
|
| 950 |
.mmu_ctpr_mask = 0xffffffc0,
|
| 951 |
.mmu_cxr_mask = 0x0000ffff,
|
| 952 |
.mmu_sfsr_mask = 0xffffffff,
|
| 953 |
.mmu_trcr_mask = 0xffffffff,
|
| 954 |
}, |
| 955 |
{
|
| 956 |
.name = "TI SuperSparc 61",
|
| 957 |
.iu_version = 0x44000000,
|
| 958 |
.fpu_version = 0 << 17, |
| 959 |
.mmu_version = 0x04000000,
|
| 960 |
.mmu_bm = 0x00002000,
|
| 961 |
.mmu_ctpr_mask = 0xffffffc0,
|
| 962 |
.mmu_cxr_mask = 0x0000ffff,
|
| 963 |
.mmu_sfsr_mask = 0xffffffff,
|
| 964 |
.mmu_trcr_mask = 0xffffffff,
|
| 965 |
}, |
| 966 |
{
|
| 967 |
.name = "Ross RT625",
|
| 968 |
.iu_version = 0x1e000000,
|
| 969 |
.fpu_version = 1 << 17, |
| 970 |
.mmu_version = 0x1e000000,
|
| 971 |
.mmu_bm = 0x00004000,
|
| 972 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 973 |
.mmu_cxr_mask = 0x0000003f,
|
| 974 |
.mmu_sfsr_mask = 0xffffffff,
|
| 975 |
.mmu_trcr_mask = 0xffffffff,
|
| 976 |
}, |
| 977 |
{
|
| 978 |
.name = "Ross RT620",
|
| 979 |
.iu_version = 0x1f000000,
|
| 980 |
.fpu_version = 1 << 17, |
| 981 |
.mmu_version = 0x1f000000,
|
| 982 |
.mmu_bm = 0x00004000,
|
| 983 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 984 |
.mmu_cxr_mask = 0x0000003f,
|
| 985 |
.mmu_sfsr_mask = 0xffffffff,
|
| 986 |
.mmu_trcr_mask = 0xffffffff,
|
| 987 |
}, |
| 988 |
{
|
| 989 |
.name = "BIT B5010",
|
| 990 |
.iu_version = 0x20000000,
|
| 991 |
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
| 992 |
.mmu_version = 0x20000000,
|
| 993 |
.mmu_bm = 0x00004000,
|
| 994 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 995 |
.mmu_cxr_mask = 0x0000003f,
|
| 996 |
.mmu_sfsr_mask = 0xffffffff,
|
| 997 |
.mmu_trcr_mask = 0xffffffff,
|
| 998 |
}, |
| 999 |
{
|
| 1000 |
.name = "Matsushita MN10501",
|
| 1001 |
.iu_version = 0x50000000,
|
| 1002 |
.fpu_version = 0 << 17, |
| 1003 |
.mmu_version = 0x50000000,
|
| 1004 |
.mmu_bm = 0x00004000,
|
| 1005 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 1006 |
.mmu_cxr_mask = 0x0000003f,
|
| 1007 |
.mmu_sfsr_mask = 0xffffffff,
|
| 1008 |
.mmu_trcr_mask = 0xffffffff,
|
| 1009 |
}, |
| 1010 |
{
|
| 1011 |
.name = "Weitek W8601",
|
| 1012 |
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
| 1013 |
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
| 1014 |
.mmu_version = 0x10 << 24, |
| 1015 |
.mmu_bm = 0x00004000,
|
| 1016 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 1017 |
.mmu_cxr_mask = 0x0000003f,
|
| 1018 |
.mmu_sfsr_mask = 0xffffffff,
|
| 1019 |
.mmu_trcr_mask = 0xffffffff,
|
| 1020 |
}, |
| 1021 |
{
|
| 1022 |
.name = "LEON2",
|
| 1023 |
.iu_version = 0xf2000000,
|
| 1024 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
| 1025 |
.mmu_version = 0xf2000000,
|
| 1026 |
.mmu_bm = 0x00004000,
|
| 1027 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 1028 |
.mmu_cxr_mask = 0x0000003f,
|
| 1029 |
.mmu_sfsr_mask = 0xffffffff,
|
| 1030 |
.mmu_trcr_mask = 0xffffffff,
|
| 1031 |
}, |
| 1032 |
{
|
| 1033 |
.name = "LEON3",
|
| 1034 |
.iu_version = 0xf3000000,
|
| 1035 |
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
| 1036 |
.mmu_version = 0xf3000000,
|
| 1037 |
.mmu_bm = 0x00004000,
|
| 1038 |
.mmu_ctpr_mask = 0x007ffff0,
|
| 1039 |
.mmu_cxr_mask = 0x0000003f,
|
| 1040 |
.mmu_sfsr_mask = 0xffffffff,
|
| 1041 |
.mmu_trcr_mask = 0xffffffff,
|
| 1042 |
}, |
| 1043 |
#endif
|
| 1044 |
}; |
| 1045 |
|
| 1046 |
static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name) |
| 1047 |
{
|
| 1048 |
unsigned int i; |
| 1049 |
|
| 1050 |
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
| 1051 |
if (strcasecmp(name, sparc_defs[i].name) == 0) { |
| 1052 |
return &sparc_defs[i];
|
| 1053 |
} |
| 1054 |
} |
| 1055 |
return NULL; |
| 1056 |
} |
| 1057 |
|
| 1058 |
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
| 1059 |
{
|
| 1060 |
unsigned int i; |
| 1061 |
|
| 1062 |
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) { |
| 1063 |
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n", |
| 1064 |
sparc_defs[i].name, |
| 1065 |
sparc_defs[i].iu_version, |
| 1066 |
sparc_defs[i].fpu_version, |
| 1067 |
sparc_defs[i].mmu_version); |
| 1068 |
} |
| 1069 |
} |
| 1070 |
|
| 1071 |
#define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
| 1072 |
|
| 1073 |
void cpu_dump_state(CPUState *env, FILE *f,
|
| 1074 |
int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
| 1075 |
int flags)
|
| 1076 |
{
|
| 1077 |
int i, x;
|
| 1078 |
|
| 1079 |
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); |
| 1080 |
cpu_fprintf(f, "General Registers:\n");
|
| 1081 |
for (i = 0; i < 4; i++) |
| 1082 |
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
| 1083 |
cpu_fprintf(f, "\n");
|
| 1084 |
for (; i < 8; i++) |
| 1085 |
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
| 1086 |
cpu_fprintf(f, "\nCurrent Register Window:\n");
|
| 1087 |
for (x = 0; x < 3; x++) { |
| 1088 |
for (i = 0; i < 4; i++) |
| 1089 |
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
| 1090 |
(x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
| 1091 |
env->regwptr[i + x * 8]);
|
| 1092 |
cpu_fprintf(f, "\n");
|
| 1093 |
for (; i < 8; i++) |
| 1094 |
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
| 1095 |
(x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
| 1096 |
env->regwptr[i + x * 8]);
|
| 1097 |
cpu_fprintf(f, "\n");
|
| 1098 |
} |
| 1099 |
cpu_fprintf(f, "\nFloating Point Registers:\n");
|
| 1100 |
for (i = 0; i < 32; i++) { |
| 1101 |
if ((i & 3) == 0) |
| 1102 |
cpu_fprintf(f, "%%f%02d:", i);
|
| 1103 |
cpu_fprintf(f, " %016lf", env->fpr[i]);
|
| 1104 |
if ((i & 3) == 3) |
| 1105 |
cpu_fprintf(f, "\n");
|
| 1106 |
} |
| 1107 |
#ifdef TARGET_SPARC64
|
| 1108 |
cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
|
| 1109 |
env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
| 1110 |
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
|
| 1111 |
env->cansave, env->canrestore, env->otherwin, env->wstate, |
| 1112 |
env->cleanwin, NWINDOWS - 1 - env->cwp);
|
| 1113 |
#else
|
| 1114 |
cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
|
| 1115 |
GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
| 1116 |
GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
| 1117 |
env->psrs?'S':'-', env->psrps?'P':'-', |
| 1118 |
env->psret?'E':'-', env->wim); |
| 1119 |
#endif
|
| 1120 |
cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
|
| 1121 |
} |
| 1122 |
|
| 1123 |
#ifdef TARGET_SPARC64
|
| 1124 |
#if !defined(CONFIG_USER_ONLY)
|
| 1125 |
#include "qemu-common.h" |
| 1126 |
#include "hw/irq.h" |
| 1127 |
#include "qemu-timer.h" |
| 1128 |
#endif
|
| 1129 |
|
| 1130 |
void helper_tick_set_count(void *opaque, uint64_t count) |
| 1131 |
{
|
| 1132 |
#if !defined(CONFIG_USER_ONLY)
|
| 1133 |
ptimer_set_count(opaque, -count); |
| 1134 |
#endif
|
| 1135 |
} |
| 1136 |
|
| 1137 |
uint64_t helper_tick_get_count(void *opaque)
|
| 1138 |
{
|
| 1139 |
#if !defined(CONFIG_USER_ONLY)
|
| 1140 |
return -ptimer_get_count(opaque);
|
| 1141 |
#else
|
| 1142 |
return 0; |
| 1143 |
#endif
|
| 1144 |
} |
| 1145 |
|
| 1146 |
void helper_tick_set_limit(void *opaque, uint64_t limit) |
| 1147 |
{
|
| 1148 |
#if !defined(CONFIG_USER_ONLY)
|
| 1149 |
ptimer_set_limit(opaque, -limit, 0);
|
| 1150 |
#endif
|
| 1151 |
} |
| 1152 |
#endif
|