Revision c4f8e211 hw/usb-ehci.c

b/hw/usb-ehci.c
719 719
    int rwc;
720 720
    USBDevice *dev = s->ports[port].dev;
721 721

  
722
    DPRINTF("port_status_write: "
723
            "PORTSC (port %d) curr %08X new %08X rw-clear %08X rw %08X\n",
724
            port, *portsc, val, (val & PORTSC_RWC_MASK), val & PORTSC_RO_MASK);
725

  
726 722
    rwc = val & PORTSC_RWC_MASK;
727 723
    val &= PORTSC_RO_MASK;
728 724

  
......
744 740
        }
745 741

  
746 742
        if (s->ports[port].dev) {
747
            DPRINTF("port_status_write: "
748
                    "Device was connected before reset, clearing CSC bit\n");
749 743
            *portsc &= ~PORTSC_CSC;
750 744
        }
751 745

  
......
760 754

  
761 755
    *portsc &= ~PORTSC_RO_MASK;
762 756
    *portsc |= val;
763
    DPRINTF("port_status_write: Port %d status set to 0x%08x\n", port, *portsc);
764 757
}
765 758

  
766 759
static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
767 760
{
768 761
    EHCIState *s = ptr;
762
    uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
763
    uint32_t old = *mmio;
769 764
    int i;
770 765

  
771
    trace_usb_ehci_mmio_writel(addr, addr2str(addr), val,
772
                               *(uint32_t *)(&s->mmio[addr]));
766
    trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
773 767

  
774 768
    /* Only aligned reads are allowed on OHCI */
775 769
    if (addr & 3) {
......
780 774

  
781 775
    if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
782 776
        handle_port_status_write(s, (addr-PORTSC)/4, val);
777
        trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
783 778
        return;
784 779
    }
785 780

  
......
858 853
        break;
859 854
    }
860 855

  
861
    *(uint32_t *)(&s->mmio[addr]) = val;
856
    *mmio = val;
857
    trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
862 858
}
863 859

  
864 860

  

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