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/*
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* ARM micro operations
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2005 CodeSourcery, LLC
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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#define REGNAME r0
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#define REG (env->regs[0]) |
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#include "op_template.h" |
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#define REGNAME r1
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#define REG (env->regs[1]) |
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#include "op_template.h" |
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#define REGNAME r2
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#define REG (env->regs[2]) |
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#include "op_template.h" |
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#define REGNAME r3
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#define REG (env->regs[3]) |
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#include "op_template.h" |
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#define REGNAME r4
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#define REG (env->regs[4]) |
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#include "op_template.h" |
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#define REGNAME r5
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#define REG (env->regs[5]) |
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#include "op_template.h" |
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#define REGNAME r6
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#define REG (env->regs[6]) |
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#include "op_template.h" |
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#define REGNAME r7
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#define REG (env->regs[7]) |
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#include "op_template.h" |
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#define REGNAME r8
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#define REG (env->regs[8]) |
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#include "op_template.h" |
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#define REGNAME r9
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#define REG (env->regs[9]) |
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#include "op_template.h" |
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#define REGNAME r10
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#define REG (env->regs[10]) |
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#include "op_template.h" |
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#define REGNAME r11
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#define REG (env->regs[11]) |
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#include "op_template.h" |
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#define REGNAME r12
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#define REG (env->regs[12]) |
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#include "op_template.h" |
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#define REGNAME r13
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#define REG (env->regs[13]) |
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#include "op_template.h" |
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#define REGNAME r14
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#define REG (env->regs[14]) |
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#include "op_template.h" |
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#define REGNAME r15
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#define REG (env->regs[15]) |
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#define SET_REG(x) REG = x & ~(uint32_t)1 |
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#include "op_template.h" |
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void OPPROTO op_bx_T0(void) |
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{ |
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env->regs[15] = T0 & ~(uint32_t)1; |
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env->thumb = (T0 & 1) != 0; |
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} |
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void OPPROTO op_movl_T0_0(void) |
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{ |
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T0 = 0;
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} |
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void OPPROTO op_movl_T0_im(void) |
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{ |
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T0 = PARAM1; |
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} |
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void OPPROTO op_movl_T1_im(void) |
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{ |
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T1 = PARAM1; |
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} |
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void OPPROTO op_mov_CF_T1(void) |
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{ |
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env->CF = ((uint32_t)T1) >> 31;
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} |
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void OPPROTO op_movl_T2_im(void) |
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{ |
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T2 = PARAM1; |
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} |
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void OPPROTO op_addl_T1_im(void) |
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{ |
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T1 += PARAM1; |
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} |
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void OPPROTO op_addl_T1_T2(void) |
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{ |
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T1 += T2; |
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} |
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void OPPROTO op_subl_T1_T2(void) |
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{ |
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T1 -= T2; |
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} |
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void OPPROTO op_addl_T0_T1(void) |
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{ |
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T0 += T1; |
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} |
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void OPPROTO op_addl_T0_T1_cc(void) |
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{ |
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unsigned int src1; |
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src1 = T0; |
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T0 += T1; |
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env->NZF = T0; |
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env->CF = T0 < src1; |
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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} |
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void OPPROTO op_adcl_T0_T1(void) |
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{ |
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T0 += T1 + env->CF; |
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} |
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void OPPROTO op_adcl_T0_T1_cc(void) |
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{ |
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unsigned int src1; |
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src1 = T0; |
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if (!env->CF) {
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T0 += T1; |
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env->CF = T0 < src1; |
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} else {
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T0 += T1 + 1;
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env->CF = T0 <= src1; |
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} |
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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env->NZF = T0; |
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FORCE_RET(); |
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} |
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#define OPSUB(sub, sbc, res, T0, T1) \
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\ |
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void OPPROTO op_ ## sub ## l_T0_T1(void) \ |
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{ \ |
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res = T0 - T1; \ |
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} \ |
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\ |
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void OPPROTO op_ ## sub ## l_T0_T1_cc(void) \ |
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{ \ |
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unsigned int src1; \ |
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src1 = T0; \ |
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T0 -= T1; \ |
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env->NZF = T0; \ |
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env->CF = src1 >= T1; \ |
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env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
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res = T0; \ |
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} \ |
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\ |
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void OPPROTO op_ ## sbc ## l_T0_T1(void) \ |
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{ \ |
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res = T0 - T1 + env->CF - 1; \
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} \ |
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\ |
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void OPPROTO op_ ## sbc ## l_T0_T1_cc(void) \ |
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{ \ |
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unsigned int src1; \ |
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src1 = T0; \ |
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if (!env->CF) { \
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T0 = T0 - T1 - 1; \
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env->CF = src1 > T1; \ |
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} else { \
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T0 = T0 - T1; \ |
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env->CF = src1 >= T1; \ |
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} \ |
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env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
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env->NZF = T0; \ |
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res = T0; \ |
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FORCE_RET(); \ |
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} |
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OPSUB(sub, sbc, T0, T0, T1) |
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OPSUB(rsb, rsc, T0, T1, T0) |
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void OPPROTO op_andl_T0_T1(void) |
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{ |
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T0 &= T1; |
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} |
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void OPPROTO op_xorl_T0_T1(void) |
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{ |
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T0 ^= T1; |
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} |
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void OPPROTO op_orl_T0_T1(void) |
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{ |
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T0 |= T1; |
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} |
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void OPPROTO op_bicl_T0_T1(void) |
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{ |
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T0 &= ~T1; |
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} |
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void OPPROTO op_notl_T1(void) |
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{ |
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T1 = ~T1; |
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} |
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void OPPROTO op_logic_T0_cc(void) |
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{ |
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env->NZF = T0; |
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} |
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void OPPROTO op_logic_T1_cc(void) |
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{ |
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env->NZF = T1; |
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} |
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#define EIP (env->regs[15]) |
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void OPPROTO op_test_eq(void) |
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{ |
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if (env->NZF == 0) |
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GOTO_LABEL_PARAM(1);;
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FORCE_RET(); |
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} |
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void OPPROTO op_test_ne(void) |
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{ |
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if (env->NZF != 0) |
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GOTO_LABEL_PARAM(1);;
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FORCE_RET(); |
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} |
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void OPPROTO op_test_cs(void) |
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{ |
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if (env->CF != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_cc(void) |
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{ |
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if (env->CF == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_mi(void) |
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{ |
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if ((env->NZF & 0x80000000) != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_pl(void) |
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{ |
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if ((env->NZF & 0x80000000) == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_vs(void) |
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{ |
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if ((env->VF & 0x80000000) != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_vc(void) |
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{ |
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if ((env->VF & 0x80000000) == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_hi(void) |
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{ |
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if (env->CF != 0 && env->NZF != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_ls(void) |
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{ |
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if (env->CF == 0 || env->NZF == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_ge(void) |
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{ |
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if (((env->VF ^ env->NZF) & 0x80000000) == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_lt(void) |
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{ |
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if (((env->VF ^ env->NZF) & 0x80000000) != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_gt(void) |
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{ |
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if (env->NZF != 0 && ((env->VF ^ env->NZF) & 0x80000000) == 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_le(void) |
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{ |
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if (env->NZF == 0 || ((env->VF ^ env->NZF) & 0x80000000) != 0) |
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GOTO_LABEL_PARAM(1);
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FORCE_RET(); |
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} |
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void OPPROTO op_goto_tb0(void) |
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{ |
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GOTO_TB(op_goto_tb0, PARAM1, 0);
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} |
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void OPPROTO op_goto_tb1(void) |
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{ |
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GOTO_TB(op_goto_tb1, PARAM1, 1);
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} |
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void OPPROTO op_exit_tb(void) |
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{ |
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EXIT_TB(); |
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} |
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void OPPROTO op_movl_T0_psr(void) |
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{ |
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T0 = compute_cpsr(); |
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} |
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/* NOTE: N = 1 and Z = 1 cannot be stored currently */
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void OPPROTO op_movl_psr_T0(void) |
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{ |
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unsigned int psr; |
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psr = T0; |
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env->CF = (psr >> 29) & 1; |
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env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
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env->VF = (psr << 3) & 0x80000000; |
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/* for user mode we do not update other state info */
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} |
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void OPPROTO op_mul_T0_T1(void) |
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{ |
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T0 = T0 * T1; |
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} |
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/* 64 bit unsigned mul */
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void OPPROTO op_mull_T0_T1(void) |
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{ |
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uint64_t res; |
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res = (uint64_t)T0 * (uint64_t)T1; |
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T1 = res >> 32;
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T0 = res; |
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} |
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/* 64 bit signed mul */
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void OPPROTO op_imull_T0_T1(void) |
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{ |
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uint64_t res; |
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res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
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T1 = res >> 32;
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T0 = res; |
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} |
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/* 48 bit signed mul, top 32 bits */
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void OPPROTO op_imulw_T0_T1(void) |
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{ |
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uint64_t res; |
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res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
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T0 = res >> 16;
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} |
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void OPPROTO op_addq_T0_T1(void) |
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{ |
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uint64_t res; |
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res = ((uint64_t)T1 << 32) | T0;
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res += ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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T1 = res >> 32;
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T0 = res; |
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} |
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void OPPROTO op_addq_lo_T0_T1(void) |
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{ |
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uint64_t res; |
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res = ((uint64_t)T1 << 32) | T0;
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res += (uint64_t)(env->regs[PARAM1]); |
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T1 = res >> 32;
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T0 = res; |
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} |
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void OPPROTO op_logicq_cc(void) |
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{ |
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env->NZF = (T1 & 0x80000000) | ((T0 | T1) != 0); |
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} |
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/* memory access */
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void OPPROTO op_ldub_T0_T1(void) |
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{ |
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T0 = ldub((void *)T1);
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} |
440 |
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void OPPROTO op_ldsb_T0_T1(void) |
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{ |
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T0 = ldsb((void *)T1);
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} |
445 |
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void OPPROTO op_lduw_T0_T1(void) |
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{ |
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T0 = lduw((void *)T1);
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} |
450 |
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void OPPROTO op_ldsw_T0_T1(void) |
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{ |
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T0 = ldsw((void *)T1);
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} |
455 |
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void OPPROTO op_ldl_T0_T1(void) |
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{ |
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T0 = ldl((void *)T1);
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} |
460 |
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void OPPROTO op_stb_T0_T1(void) |
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{ |
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stb((void *)T1, T0);
|
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} |
465 |
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void OPPROTO op_stw_T0_T1(void) |
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{ |
468 |
stw((void *)T1, T0);
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} |
470 |
|
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void OPPROTO op_stl_T0_T1(void) |
472 |
{ |
473 |
stl((void *)T1, T0);
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} |
475 |
|
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void OPPROTO op_swpb_T0_T1(void) |
477 |
{ |
478 |
int tmp;
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479 |
|
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cpu_lock(); |
481 |
tmp = ldub((void *)T1);
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stb((void *)T1, T0);
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T0 = tmp; |
484 |
cpu_unlock(); |
485 |
} |
486 |
|
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void OPPROTO op_swpl_T0_T1(void) |
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{ |
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int tmp;
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490 |
|
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cpu_lock(); |
492 |
tmp = ldl((void *)T1);
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stl((void *)T1, T0);
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T0 = tmp; |
495 |
cpu_unlock(); |
496 |
} |
497 |
|
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/* shifts */
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499 |
|
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/* T1 based */
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|
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void OPPROTO op_shll_T1_im(void) |
503 |
{ |
504 |
T1 = T1 << PARAM1; |
505 |
} |
506 |
|
507 |
void OPPROTO op_shrl_T1_im(void) |
508 |
{ |
509 |
T1 = (uint32_t)T1 >> PARAM1; |
510 |
} |
511 |
|
512 |
void OPPROTO op_shrl_T1_0(void) |
513 |
{ |
514 |
T1 = 0;
|
515 |
} |
516 |
|
517 |
void OPPROTO op_sarl_T1_im(void) |
518 |
{ |
519 |
T1 = (int32_t)T1 >> PARAM1; |
520 |
} |
521 |
|
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void OPPROTO op_sarl_T1_0(void) |
523 |
{ |
524 |
T1 = (int32_t)T1 >> 31;
|
525 |
} |
526 |
|
527 |
void OPPROTO op_rorl_T1_im(void) |
528 |
{ |
529 |
int shift;
|
530 |
shift = PARAM1; |
531 |
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
532 |
} |
533 |
|
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void OPPROTO op_rrxl_T1(void) |
535 |
{ |
536 |
T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); |
537 |
} |
538 |
|
539 |
/* T1 based, set C flag */
|
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void OPPROTO op_shll_T1_im_cc(void) |
541 |
{ |
542 |
env->CF = (T1 >> (32 - PARAM1)) & 1; |
543 |
T1 = T1 << PARAM1; |
544 |
} |
545 |
|
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void OPPROTO op_shrl_T1_im_cc(void) |
547 |
{ |
548 |
env->CF = (T1 >> (PARAM1 - 1)) & 1; |
549 |
T1 = (uint32_t)T1 >> PARAM1; |
550 |
} |
551 |
|
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void OPPROTO op_shrl_T1_0_cc(void) |
553 |
{ |
554 |
env->CF = (T1 >> 31) & 1; |
555 |
T1 = 0;
|
556 |
} |
557 |
|
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void OPPROTO op_sarl_T1_im_cc(void) |
559 |
{ |
560 |
env->CF = (T1 >> (PARAM1 - 1)) & 1; |
561 |
T1 = (int32_t)T1 >> PARAM1; |
562 |
} |
563 |
|
564 |
void OPPROTO op_sarl_T1_0_cc(void) |
565 |
{ |
566 |
env->CF = (T1 >> 31) & 1; |
567 |
T1 = (int32_t)T1 >> 31;
|
568 |
} |
569 |
|
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void OPPROTO op_rorl_T1_im_cc(void) |
571 |
{ |
572 |
int shift;
|
573 |
shift = PARAM1; |
574 |
env->CF = (T1 >> (shift - 1)) & 1; |
575 |
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
576 |
} |
577 |
|
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void OPPROTO op_rrxl_T1_cc(void) |
579 |
{ |
580 |
uint32_t c; |
581 |
c = T1 & 1;
|
582 |
T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); |
583 |
env->CF = c; |
584 |
} |
585 |
|
586 |
/* T2 based */
|
587 |
void OPPROTO op_shll_T2_im(void) |
588 |
{ |
589 |
T2 = T2 << PARAM1; |
590 |
} |
591 |
|
592 |
void OPPROTO op_shrl_T2_im(void) |
593 |
{ |
594 |
T2 = (uint32_t)T2 >> PARAM1; |
595 |
} |
596 |
|
597 |
void OPPROTO op_shrl_T2_0(void) |
598 |
{ |
599 |
T2 = 0;
|
600 |
} |
601 |
|
602 |
void OPPROTO op_sarl_T2_im(void) |
603 |
{ |
604 |
T2 = (int32_t)T2 >> PARAM1; |
605 |
} |
606 |
|
607 |
void OPPROTO op_sarl_T2_0(void) |
608 |
{ |
609 |
T2 = (int32_t)T2 >> 31;
|
610 |
} |
611 |
|
612 |
void OPPROTO op_rorl_T2_im(void) |
613 |
{ |
614 |
int shift;
|
615 |
shift = PARAM1; |
616 |
T2 = ((uint32_t)T2 >> shift) | (T2 << (32 - shift));
|
617 |
} |
618 |
|
619 |
void OPPROTO op_rrxl_T2(void) |
620 |
{ |
621 |
T2 = ((uint32_t)T2 >> 1) | ((uint32_t)env->CF << 31); |
622 |
} |
623 |
|
624 |
/* T1 based, use T0 as shift count */
|
625 |
|
626 |
void OPPROTO op_shll_T1_T0(void) |
627 |
{ |
628 |
int shift;
|
629 |
shift = T0 & 0xff;
|
630 |
if (shift >= 32) |
631 |
T1 = 0;
|
632 |
else
|
633 |
T1 = T1 << shift; |
634 |
FORCE_RET(); |
635 |
} |
636 |
|
637 |
void OPPROTO op_shrl_T1_T0(void) |
638 |
{ |
639 |
int shift;
|
640 |
shift = T0 & 0xff;
|
641 |
if (shift >= 32) |
642 |
T1 = 0;
|
643 |
else
|
644 |
T1 = (uint32_t)T1 >> shift; |
645 |
FORCE_RET(); |
646 |
} |
647 |
|
648 |
void OPPROTO op_sarl_T1_T0(void) |
649 |
{ |
650 |
int shift;
|
651 |
shift = T0 & 0xff;
|
652 |
if (shift >= 32) |
653 |
shift = 31;
|
654 |
T1 = (int32_t)T1 >> shift; |
655 |
} |
656 |
|
657 |
void OPPROTO op_rorl_T1_T0(void) |
658 |
{ |
659 |
int shift;
|
660 |
shift = T0 & 0x1f;
|
661 |
if (shift) {
|
662 |
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
663 |
} |
664 |
FORCE_RET(); |
665 |
} |
666 |
|
667 |
/* T1 based, use T0 as shift count and compute CF */
|
668 |
|
669 |
void OPPROTO op_shll_T1_T0_cc(void) |
670 |
{ |
671 |
int shift;
|
672 |
shift = T0 & 0xff;
|
673 |
if (shift >= 32) { |
674 |
if (shift == 32) |
675 |
env->CF = T1 & 1;
|
676 |
else
|
677 |
env->CF = 0;
|
678 |
T1 = 0;
|
679 |
} else if (shift != 0) { |
680 |
env->CF = (T1 >> (32 - shift)) & 1; |
681 |
T1 = T1 << shift; |
682 |
} |
683 |
FORCE_RET(); |
684 |
} |
685 |
|
686 |
void OPPROTO op_shrl_T1_T0_cc(void) |
687 |
{ |
688 |
int shift;
|
689 |
shift = T0 & 0xff;
|
690 |
if (shift >= 32) { |
691 |
if (shift == 32) |
692 |
env->CF = (T1 >> 31) & 1; |
693 |
else
|
694 |
env->CF = 0;
|
695 |
T1 = 0;
|
696 |
} else if (shift != 0) { |
697 |
env->CF = (T1 >> (shift - 1)) & 1; |
698 |
T1 = (uint32_t)T1 >> shift; |
699 |
} |
700 |
FORCE_RET(); |
701 |
} |
702 |
|
703 |
void OPPROTO op_sarl_T1_T0_cc(void) |
704 |
{ |
705 |
int shift;
|
706 |
shift = T0 & 0xff;
|
707 |
if (shift >= 32) { |
708 |
env->CF = (T1 >> 31) & 1; |
709 |
T1 = (int32_t)T1 >> 31;
|
710 |
} else {
|
711 |
env->CF = (T1 >> (shift - 1)) & 1; |
712 |
T1 = (int32_t)T1 >> shift; |
713 |
} |
714 |
FORCE_RET(); |
715 |
} |
716 |
|
717 |
void OPPROTO op_rorl_T1_T0_cc(void) |
718 |
{ |
719 |
int shift1, shift;
|
720 |
shift1 = T0 & 0xff;
|
721 |
shift = shift1 & 0x1f;
|
722 |
if (shift == 0) { |
723 |
if (shift1 != 0) |
724 |
env->CF = (T1 >> 31) & 1; |
725 |
} else {
|
726 |
env->CF = (T1 >> (shift - 1)) & 1; |
727 |
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
728 |
} |
729 |
FORCE_RET(); |
730 |
} |
731 |
|
732 |
/* misc */
|
733 |
void OPPROTO op_clz_T0(void) |
734 |
{ |
735 |
int count;
|
736 |
for (count = 32; T0 > 0; count--) |
737 |
T0 = T0 >> 1;
|
738 |
T0 = count; |
739 |
FORCE_RET(); |
740 |
} |
741 |
|
742 |
void OPPROTO op_sarl_T0_im(void) |
743 |
{ |
744 |
T0 = (int32_t)T0 >> PARAM1; |
745 |
} |
746 |
|
747 |
/* 16->32 Sign extend */
|
748 |
void OPPROTO op_sxl_T0(void) |
749 |
{ |
750 |
T0 = (int16_t)T0; |
751 |
} |
752 |
|
753 |
void OPPROTO op_sxl_T1(void) |
754 |
{ |
755 |
T1 = (int16_t)T1; |
756 |
} |
757 |
|
758 |
#define SIGNBIT (uint32_t)0x80000000 |
759 |
/* saturating arithmetic */
|
760 |
void OPPROTO op_addl_T0_T1_setq(void) |
761 |
{ |
762 |
uint32_t res; |
763 |
|
764 |
res = T0 + T1; |
765 |
if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT))
|
766 |
env->QF = 1;
|
767 |
|
768 |
T0 = res; |
769 |
FORCE_RET(); |
770 |
} |
771 |
|
772 |
void OPPROTO op_addl_T0_T1_saturate(void) |
773 |
{ |
774 |
uint32_t res; |
775 |
|
776 |
res = T0 + T1; |
777 |
if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT)) {
|
778 |
env->QF = 1;
|
779 |
if (T0 & SIGNBIT)
|
780 |
T0 = 0x80000000;
|
781 |
else
|
782 |
T0 = 0x7fffffff;
|
783 |
} |
784 |
else
|
785 |
T0 = res; |
786 |
|
787 |
FORCE_RET(); |
788 |
} |
789 |
|
790 |
void OPPROTO op_subl_T0_T1_saturate(void) |
791 |
{ |
792 |
uint32_t res; |
793 |
|
794 |
res = T0 - T1; |
795 |
if (((res ^ T0) & SIGNBIT) && ((T0 ^ T1) & SIGNBIT)) {
|
796 |
env->QF = 1;
|
797 |
if (T0 & SIGNBIT)
|
798 |
T0 = 0x8000000;
|
799 |
else
|
800 |
T0 = 0x7fffffff;
|
801 |
} |
802 |
else
|
803 |
T0 = res; |
804 |
|
805 |
FORCE_RET(); |
806 |
} |
807 |
|
808 |
void OPPROTO op_double_T1_saturate(void) |
809 |
{ |
810 |
int32_t val; |
811 |
|
812 |
val = T1; |
813 |
if (val >= 0x40000000) { |
814 |
T1 = 0x7fffffff;
|
815 |
env->QF = 1;
|
816 |
} else if (val <= (int32_t)0xc0000000) { |
817 |
T1 = 0x80000000;
|
818 |
env->QF = 1;
|
819 |
} else {
|
820 |
T1 = val << 1;
|
821 |
} |
822 |
FORCE_RET(); |
823 |
} |
824 |
|
825 |
/* thumb shift by immediate */
|
826 |
void OPPROTO op_shll_T0_im_thumb(void) |
827 |
{ |
828 |
int shift;
|
829 |
shift = PARAM1; |
830 |
if (shift != 0) { |
831 |
env->CF = (T1 >> (32 - shift)) & 1; |
832 |
T0 = T0 << shift; |
833 |
} |
834 |
env->NZF = T0; |
835 |
FORCE_RET(); |
836 |
} |
837 |
|
838 |
void OPPROTO op_shrl_T0_im_thumb(void) |
839 |
{ |
840 |
int shift;
|
841 |
|
842 |
shift = PARAM1; |
843 |
if (shift == 0) { |
844 |
env->CF = ((uint32_t)shift) >> 31;
|
845 |
T0 = 0;
|
846 |
} else {
|
847 |
env->CF = (T0 >> (shift - 1)) & 1; |
848 |
T0 = T0 >> shift; |
849 |
} |
850 |
env->NZF = T0; |
851 |
FORCE_RET(); |
852 |
} |
853 |
|
854 |
void OPPROTO op_sarl_T0_im_thumb(void) |
855 |
{ |
856 |
int shift;
|
857 |
|
858 |
shift = PARAM1; |
859 |
if (shift == 0) { |
860 |
T0 = ((int32_t)T0) >> 31;
|
861 |
env->CF = T0 & 1;
|
862 |
} else {
|
863 |
env->CF = (T0 >> (shift - 1)) & 1; |
864 |
T0 = ((int32_t)T0) >> shift; |
865 |
} |
866 |
env->NZF = T0; |
867 |
FORCE_RET(); |
868 |
} |
869 |
|
870 |
/* exceptions */
|
871 |
|
872 |
void OPPROTO op_swi(void) |
873 |
{ |
874 |
env->exception_index = EXCP_SWI; |
875 |
cpu_loop_exit(); |
876 |
} |
877 |
|
878 |
void OPPROTO op_undef_insn(void) |
879 |
{ |
880 |
env->exception_index = EXCP_UDEF; |
881 |
cpu_loop_exit(); |
882 |
} |
883 |
|
884 |
void OPPROTO op_debug(void) |
885 |
{ |
886 |
env->exception_index = EXCP_DEBUG; |
887 |
cpu_loop_exit(); |
888 |
} |
889 |
|
890 |
/* VFP support. We follow the convention used for VFP instrunctions:
|
891 |
Single precition routines have a "s" suffix, double precision a
|
892 |
"d" suffix. */
|
893 |
|
894 |
#define VFP_OP(name, p) void OPPROTO op_vfp_##name##p(void) |
895 |
|
896 |
#define VFP_BINOP(name) \
|
897 |
VFP_OP(name, s) \ |
898 |
{ \ |
899 |
FT0s = float32_ ## name (FT0s, FT1s, &env->vfp.fp_status); \ |
900 |
} \ |
901 |
VFP_OP(name, d) \ |
902 |
{ \ |
903 |
FT0d = float64_ ## name (FT0d, FT1d, &env->vfp.fp_status); \ |
904 |
} |
905 |
VFP_BINOP(add) |
906 |
VFP_BINOP(sub) |
907 |
VFP_BINOP(mul) |
908 |
VFP_BINOP(div) |
909 |
#undef VFP_BINOP
|
910 |
|
911 |
#define VFP_HELPER(name) \
|
912 |
VFP_OP(name, s) \ |
913 |
{ \ |
914 |
do_vfp_##name##s(); \ |
915 |
} \ |
916 |
VFP_OP(name, d) \ |
917 |
{ \ |
918 |
do_vfp_##name##d(); \ |
919 |
} |
920 |
VFP_HELPER(abs) |
921 |
VFP_HELPER(sqrt) |
922 |
VFP_HELPER(cmp) |
923 |
VFP_HELPER(cmpe) |
924 |
#undef VFP_HELPER
|
925 |
|
926 |
/* XXX: Will this do the right thing for NANs. Should invert the signbit
|
927 |
without looking at the rest of the value. */
|
928 |
VFP_OP(neg, s) |
929 |
{ |
930 |
FT0s = float32_chs(FT0s); |
931 |
} |
932 |
|
933 |
VFP_OP(neg, d) |
934 |
{ |
935 |
FT0d = float64_chs(FT0d); |
936 |
} |
937 |
|
938 |
VFP_OP(F1_ld0, s) |
939 |
{ |
940 |
union {
|
941 |
uint32_t i; |
942 |
float32 s; |
943 |
} v; |
944 |
v.i = 0;
|
945 |
FT1s = v.s; |
946 |
} |
947 |
|
948 |
VFP_OP(F1_ld0, d) |
949 |
{ |
950 |
union {
|
951 |
uint64_t i; |
952 |
float64 d; |
953 |
} v; |
954 |
v.i = 0;
|
955 |
FT1d = v.d; |
956 |
} |
957 |
|
958 |
/* Helper routines to perform bitwise copies between float and int. */
|
959 |
static inline float32 vfp_itos(uint32_t i) |
960 |
{ |
961 |
union {
|
962 |
uint32_t i; |
963 |
float32 s; |
964 |
} v; |
965 |
|
966 |
v.i = i; |
967 |
return v.s;
|
968 |
} |
969 |
|
970 |
static inline uint32_t vfp_stoi(float32 s) |
971 |
{ |
972 |
union {
|
973 |
uint32_t i; |
974 |
float32 s; |
975 |
} v; |
976 |
|
977 |
v.s = s; |
978 |
return v.i;
|
979 |
} |
980 |
|
981 |
/* Integer to float conversion. */
|
982 |
VFP_OP(uito, s) |
983 |
{ |
984 |
FT0s = uint32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status); |
985 |
} |
986 |
|
987 |
VFP_OP(uito, d) |
988 |
{ |
989 |
FT0d = uint32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status); |
990 |
} |
991 |
|
992 |
VFP_OP(sito, s) |
993 |
{ |
994 |
FT0s = int32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status); |
995 |
} |
996 |
|
997 |
VFP_OP(sito, d) |
998 |
{ |
999 |
FT0d = int32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status); |
1000 |
} |
1001 |
|
1002 |
/* Float to integer conversion. */
|
1003 |
VFP_OP(toui, s) |
1004 |
{ |
1005 |
FT0s = vfp_itos(float32_to_uint32(FT0s, &env->vfp.fp_status)); |
1006 |
} |
1007 |
|
1008 |
VFP_OP(toui, d) |
1009 |
{ |
1010 |
FT0s = vfp_itos(float64_to_uint32(FT0d, &env->vfp.fp_status)); |
1011 |
} |
1012 |
|
1013 |
VFP_OP(tosi, s) |
1014 |
{ |
1015 |
FT0s = vfp_itos(float32_to_int32(FT0s, &env->vfp.fp_status)); |
1016 |
} |
1017 |
|
1018 |
VFP_OP(tosi, d) |
1019 |
{ |
1020 |
FT0s = vfp_itos(float64_to_int32(FT0d, &env->vfp.fp_status)); |
1021 |
} |
1022 |
|
1023 |
/* TODO: Set rounding mode properly. */
|
1024 |
VFP_OP(touiz, s) |
1025 |
{ |
1026 |
FT0s = vfp_itos(float32_to_uint32_round_to_zero(FT0s, &env->vfp.fp_status)); |
1027 |
} |
1028 |
|
1029 |
VFP_OP(touiz, d) |
1030 |
{ |
1031 |
FT0s = vfp_itos(float64_to_uint32_round_to_zero(FT0d, &env->vfp.fp_status)); |
1032 |
} |
1033 |
|
1034 |
VFP_OP(tosiz, s) |
1035 |
{ |
1036 |
FT0s = vfp_itos(float32_to_int32_round_to_zero(FT0s, &env->vfp.fp_status)); |
1037 |
} |
1038 |
|
1039 |
VFP_OP(tosiz, d) |
1040 |
{ |
1041 |
FT0s = vfp_itos(float64_to_int32_round_to_zero(FT0d, &env->vfp.fp_status)); |
1042 |
} |
1043 |
|
1044 |
/* floating point conversion */
|
1045 |
VFP_OP(fcvtd, s) |
1046 |
{ |
1047 |
FT0d = float32_to_float64(FT0s, &env->vfp.fp_status); |
1048 |
} |
1049 |
|
1050 |
VFP_OP(fcvts, d) |
1051 |
{ |
1052 |
FT0s = float64_to_float32(FT0d, &env->vfp.fp_status); |
1053 |
} |
1054 |
|
1055 |
/* Get and Put values from registers. */
|
1056 |
VFP_OP(getreg_F0, d) |
1057 |
{ |
1058 |
FT0d = *(float64 *)((char *) env + PARAM1);
|
1059 |
} |
1060 |
|
1061 |
VFP_OP(getreg_F0, s) |
1062 |
{ |
1063 |
FT0s = *(float32 *)((char *) env + PARAM1);
|
1064 |
} |
1065 |
|
1066 |
VFP_OP(getreg_F1, d) |
1067 |
{ |
1068 |
FT1d = *(float64 *)((char *) env + PARAM1);
|
1069 |
} |
1070 |
|
1071 |
VFP_OP(getreg_F1, s) |
1072 |
{ |
1073 |
FT1s = *(float32 *)((char *) env + PARAM1);
|
1074 |
} |
1075 |
|
1076 |
VFP_OP(setreg_F0, d) |
1077 |
{ |
1078 |
*(float64 *)((char *) env + PARAM1) = FT0d;
|
1079 |
} |
1080 |
|
1081 |
VFP_OP(setreg_F0, s) |
1082 |
{ |
1083 |
*(float32 *)((char *) env + PARAM1) = FT0s;
|
1084 |
} |
1085 |
|
1086 |
void OPPROTO op_vfp_movl_T0_fpscr(void) |
1087 |
{ |
1088 |
do_vfp_get_fpscr (); |
1089 |
} |
1090 |
|
1091 |
void OPPROTO op_vfp_movl_T0_fpscr_flags(void) |
1092 |
{ |
1093 |
T0 = env->vfp.fpscr & (0xf << 28); |
1094 |
} |
1095 |
|
1096 |
void OPPROTO op_vfp_movl_fpscr_T0(void) |
1097 |
{ |
1098 |
do_vfp_set_fpscr(); |
1099 |
} |
1100 |
|
1101 |
/* Move between FT0s to T0 */
|
1102 |
void OPPROTO op_vfp_mrs(void) |
1103 |
{ |
1104 |
T0 = vfp_stoi(FT0s); |
1105 |
} |
1106 |
|
1107 |
void OPPROTO op_vfp_msr(void) |
1108 |
{ |
1109 |
FT0s = vfp_itos(T0); |
1110 |
} |
1111 |
|
1112 |
/* Move between FT0d and {T0,T1} */
|
1113 |
void OPPROTO op_vfp_mrrd(void) |
1114 |
{ |
1115 |
CPU_DoubleU u; |
1116 |
|
1117 |
u.d = FT0d; |
1118 |
T0 = u.l.lower; |
1119 |
T1 = u.l.upper; |
1120 |
} |
1121 |
|
1122 |
void OPPROTO op_vfp_mdrr(void) |
1123 |
{ |
1124 |
CPU_DoubleU u; |
1125 |
|
1126 |
u.l.lower = T0; |
1127 |
u.l.upper = T1; |
1128 |
FT0d = u.d; |
1129 |
} |
1130 |
|
1131 |
/* Floating point load/store. Address is in T1 */
|
1132 |
void OPPROTO op_vfp_lds(void) |
1133 |
{ |
1134 |
FT0s = ldfl((void *)T1);
|
1135 |
} |
1136 |
|
1137 |
void OPPROTO op_vfp_ldd(void) |
1138 |
{ |
1139 |
FT0d = ldfq((void *)T1);
|
1140 |
} |
1141 |
|
1142 |
void OPPROTO op_vfp_sts(void) |
1143 |
{ |
1144 |
stfl((void *)T1, FT0s);
|
1145 |
} |
1146 |
|
1147 |
void OPPROTO op_vfp_std(void) |
1148 |
{ |
1149 |
stfq((void *)T1, FT0d);
|
1150 |
} |