Revision c53f4a62

b/target-mips/helper.c
387 387
                   come back to the jump.  */
388 388
                env->CP0_EPC = env->PC - 4;
389 389
                env->CP0_Cause |= (1 << CP0Ca_BD);
390
                env->hflags &= ~MIPS_HFLAG_BMASK;
391 390
            } else {
392 391
                env->CP0_EPC = env->PC;
393 392
                env->CP0_Cause &= ~(1 << CP0Ca_BD);
......
395 394
            env->CP0_Status |= (1 << CP0St_EXL);
396 395
            env->hflags &= ~MIPS_HFLAG_UM;
397 396
        }
397
        env->hflags &= ~MIPS_HFLAG_BMASK;
398 398
        if (env->CP0_Status & (1 << CP0St_BEV)) {
399 399
            env->PC = (int32_t)0xBFC00200;
400 400
        } else {
b/target-mips/translate.c
1640 1640
        likely:
1641 1641
            ctx->hflags |= MIPS_HFLAG_BL;
1642 1642
            break;
1643
        default:
1644
            MIPS_INVAL("conditional branch/jump");
1645
            generate_exception(ctx, EXCP_RI);
1646
            return;
1643 1647
        }
1644 1648
        gen_op_set_bcond();
1645 1649
    }
......
1650 1654
        gen_op_set_T0(ctx->pc + 8);
1651 1655
        gen_op_store_T0_gpr(blink);
1652 1656
    }
1653
    return;
1654 1657
}
1655 1658

  
1656 1659
/* special3 bitfield operations */
......
5053 5056
        break;
5054 5057
    }
5055 5058
    if (ctx->hflags & MIPS_HFLAG_BMASK) {
5056
        int hflags = ctx->hflags;
5059
        int hflags = ctx->hflags & MIPS_HFLAG_BMASK;
5057 5060
        /* Branches completion */
5058 5061
        ctx->hflags &= ~MIPS_HFLAG_BMASK;
5059 5062
        ctx->bstate = BS_BRANCH;

Also available in: Unified diff