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1 | 6af0bf9c | bellard | #if !defined (__MIPS_CPU_H__)
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2 | 6af0bf9c | bellard | #define __MIPS_CPU_H__
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3 | 6af0bf9c | bellard | |
4 | 4ad40f36 | bellard | #define TARGET_HAS_ICE 1 |
5 | 4ad40f36 | bellard | |
6 | c5d6edc3 | bellard | #include "config.h" |
7 | 6af0bf9c | bellard | #include "mips-defs.h" |
8 | 6af0bf9c | bellard | #include "cpu-defs.h" |
9 | 6af0bf9c | bellard | #include "softfloat.h" |
10 | 6af0bf9c | bellard | |
11 | fdbb4691 | bellard | // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
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12 | fdbb4691 | bellard | // XXX: move that elsewhere
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13 | fdbb4691 | bellard | #if defined(HOST_SOLARIS) && SOLARISREV < 10 |
14 | fdbb4691 | bellard | typedef unsigned char uint_fast8_t; |
15 | fdbb4691 | bellard | typedef unsigned int uint_fast16_t; |
16 | fdbb4691 | bellard | #endif
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17 | fdbb4691 | bellard | |
18 | c570fd16 | ths | #ifdef MIPS_HAS_MIPS64
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19 | c570fd16 | ths | #define SIGN_EXTEND32(val) (((((uint64_t)(val)) & 0xFFFFFFFF) ^ 0x80000000) - 0x80000000) |
20 | c570fd16 | ths | /* target_ulong size spec */
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21 | c570fd16 | ths | #define TLSZ "%016llx" |
22 | c570fd16 | ths | #else
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23 | c570fd16 | ths | #define SIGN_EXTEND32(val) (val)
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24 | c570fd16 | ths | /* target_ulong size spec */
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25 | c570fd16 | ths | #define TLSZ "%08x" |
26 | c570fd16 | ths | #endif
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27 | c570fd16 | ths | |
28 | 6af0bf9c | bellard | typedef union fpr_t fpr_t; |
29 | 6af0bf9c | bellard | union fpr_t {
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30 | 6ea83fed | bellard | float64 fd; /* ieee double precision */
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31 | 6ea83fed | bellard | float32 fs[2];/* ieee single precision */ |
32 | 6ea83fed | bellard | uint64_t d; /* binary single fixed-point */
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33 | 6ea83fed | bellard | uint32_t w[2]; /* binary single fixed-point */ |
34 | 6af0bf9c | bellard | }; |
35 | 6ea83fed | bellard | /* define FP_ENDIAN_IDX to access the same location
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36 | 6ea83fed | bellard | * in the fpr_t union regardless of the host endianess
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37 | 6ea83fed | bellard | */
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38 | 6ea83fed | bellard | #if defined(WORDS_BIGENDIAN)
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39 | 6ea83fed | bellard | # define FP_ENDIAN_IDX 1 |
40 | 6ea83fed | bellard | #else
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41 | 6ea83fed | bellard | # define FP_ENDIAN_IDX 0 |
42 | 6ea83fed | bellard | #endif
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43 | 6af0bf9c | bellard | |
44 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
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45 | 6af0bf9c | bellard | typedef struct tlb_t tlb_t; |
46 | 6af0bf9c | bellard | struct tlb_t {
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47 | 6af0bf9c | bellard | target_ulong VPN; |
48 | 6af0bf9c | bellard | target_ulong end; |
49 | 4ad40f36 | bellard | target_ulong end2; |
50 | 98c1b82b | pbrook | uint_fast8_t ASID; |
51 | 98c1b82b | pbrook | uint_fast16_t G:1;
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52 | 98c1b82b | pbrook | uint_fast16_t C0:3;
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53 | 98c1b82b | pbrook | uint_fast16_t C1:3;
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54 | 98c1b82b | pbrook | uint_fast16_t V0:1;
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55 | 98c1b82b | pbrook | uint_fast16_t V1:1;
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56 | 98c1b82b | pbrook | uint_fast16_t D0:1;
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57 | 98c1b82b | pbrook | uint_fast16_t D1:1;
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58 | 6af0bf9c | bellard | target_ulong PFN[2];
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59 | 6af0bf9c | bellard | }; |
60 | 6af0bf9c | bellard | #endif
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61 | 6af0bf9c | bellard | |
62 | 6af0bf9c | bellard | typedef struct CPUMIPSState CPUMIPSState; |
63 | 6af0bf9c | bellard | struct CPUMIPSState {
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64 | 6af0bf9c | bellard | /* General integer registers */
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65 | 6af0bf9c | bellard | target_ulong gpr[32];
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66 | 6af0bf9c | bellard | /* Special registers */
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67 | 6af0bf9c | bellard | target_ulong PC; |
68 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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69 | c570fd16 | ths | target_ulong t0; |
70 | c570fd16 | ths | target_ulong t1; |
71 | c570fd16 | ths | target_ulong t2; |
72 | c570fd16 | ths | #endif
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73 | c570fd16 | ths | target_ulong HI, LO; |
74 | 6af0bf9c | bellard | uint32_t DCR; /* ? */
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75 | 6af0bf9c | bellard | #if defined(MIPS_USES_FPU)
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76 | 6af0bf9c | bellard | /* Floating point registers */
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77 | 6af0bf9c | bellard | fpr_t fpr[16];
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78 | 6ea83fed | bellard | #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2]) |
79 | 6ea83fed | bellard | #define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
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80 | 6ea83fed | bellard | #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX]) |
81 | 6ea83fed | bellard | #define FPR_D(cpu, n) (FPR(cpu, n)->d)
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82 | 6ea83fed | bellard | #define FPR_W(cpu, n) (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX]) |
83 | 6ea83fed | bellard | |
84 | 6ea83fed | bellard | #ifndef USE_HOST_FLOAT_REGS
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85 | 6ea83fed | bellard | fpr_t ft0; |
86 | 6ea83fed | bellard | fpr_t ft1; |
87 | 6ea83fed | bellard | fpr_t ft2; |
88 | 6ea83fed | bellard | #endif
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89 | 6ea83fed | bellard | float_status fp_status; |
90 | 6ea83fed | bellard | /* fpu implementation/revision register */
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91 | 6af0bf9c | bellard | uint32_t fcr0; |
92 | 6ea83fed | bellard | /* fcsr */
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93 | 6ea83fed | bellard | uint32_t fcr31; |
94 | 6ea83fed | bellard | #define SET_FP_COND(reg) do { (reg) |= (1<<23); } while(0) |
95 | 6ea83fed | bellard | #define CLEAR_FP_COND(reg) do { (reg) &= ~(1<<23); } while(0) |
96 | 6ea83fed | bellard | #define IS_FP_COND_SET(reg) (((reg) & (1<<23)) != 0) |
97 | 6ea83fed | bellard | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
98 | 6ea83fed | bellard | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
99 | 6ea83fed | bellard | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) |
100 | 6ea83fed | bellard | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v) << 12); } while(0) |
101 | 6ea83fed | bellard | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v) << 7); } while(0) |
102 | 6ea83fed | bellard | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v) << 2); } while(0) |
103 | 6ea83fed | bellard | #define FP_INEXACT 1 |
104 | 6ea83fed | bellard | #define FP_UNDERFLOW 2 |
105 | 6ea83fed | bellard | #define FP_OVERFLOW 4 |
106 | 6ea83fed | bellard | #define FP_DIV0 8 |
107 | 6ea83fed | bellard | #define FP_INVALID 16 |
108 | 6ea83fed | bellard | #define FP_UNIMPLEMENTED 32 |
109 | 6ea83fed | bellard | |
110 | 6af0bf9c | bellard | #endif
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111 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
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112 | 814b9a47 | ths | tlb_t tlb[MIPS_TLB_MAX]; |
113 | 814b9a47 | ths | uint32_t tlb_in_use; |
114 | 6af0bf9c | bellard | #endif
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115 | 6af0bf9c | bellard | uint32_t CP0_index; |
116 | 6af0bf9c | bellard | uint32_t CP0_random; |
117 | 7a387fff | ths | uint64_t CP0_EntryLo0; |
118 | 7a387fff | ths | uint64_t CP0_EntryLo1; |
119 | 7a387fff | ths | uint64_t CP0_Context; |
120 | 6af0bf9c | bellard | uint32_t CP0_PageMask; |
121 | 7a387fff | ths | uint32_t CP0_PageGrain; |
122 | 6af0bf9c | bellard | uint32_t CP0_Wired; |
123 | 7a387fff | ths | uint32_t CP0_HWREna; |
124 | c570fd16 | ths | target_ulong CP0_BadVAddr; |
125 | 6af0bf9c | bellard | uint32_t CP0_Count; |
126 | 7a387fff | ths | uint64_t CP0_EntryHi; |
127 | 6af0bf9c | bellard | uint32_t CP0_Compare; |
128 | 6af0bf9c | bellard | uint32_t CP0_Status; |
129 | 6af0bf9c | bellard | #define CP0St_CU3 31 |
130 | 6af0bf9c | bellard | #define CP0St_CU2 30 |
131 | 6af0bf9c | bellard | #define CP0St_CU1 29 |
132 | 6af0bf9c | bellard | #define CP0St_CU0 28 |
133 | 6af0bf9c | bellard | #define CP0St_RP 27 |
134 | 6ea83fed | bellard | #define CP0St_FR 26 |
135 | 6af0bf9c | bellard | #define CP0St_RE 25 |
136 | 7a387fff | ths | #define CP0St_MX 24 |
137 | 7a387fff | ths | #define CP0St_PX 23 |
138 | 6af0bf9c | bellard | #define CP0St_BEV 22 |
139 | 6af0bf9c | bellard | #define CP0St_TS 21 |
140 | 6af0bf9c | bellard | #define CP0St_SR 20 |
141 | 6af0bf9c | bellard | #define CP0St_NMI 19 |
142 | 6af0bf9c | bellard | #define CP0St_IM 8 |
143 | 7a387fff | ths | #define CP0St_KX 7 |
144 | 7a387fff | ths | #define CP0St_SX 6 |
145 | 7a387fff | ths | #define CP0St_UX 5 |
146 | 6af0bf9c | bellard | #define CP0St_UM 4 |
147 | 7a387fff | ths | #define CP0St_R0 3 |
148 | 6af0bf9c | bellard | #define CP0St_ERL 2 |
149 | 6af0bf9c | bellard | #define CP0St_EXL 1 |
150 | 6af0bf9c | bellard | #define CP0St_IE 0 |
151 | 7a387fff | ths | uint32_t CP0_IntCtl; |
152 | 7a387fff | ths | uint32_t CP0_SRSCtl; |
153 | 6af0bf9c | bellard | uint32_t CP0_Cause; |
154 | 7a387fff | ths | #define CP0Ca_BD 31 |
155 | 7a387fff | ths | #define CP0Ca_TI 30 |
156 | 7a387fff | ths | #define CP0Ca_CE 28 |
157 | 7a387fff | ths | #define CP0Ca_DC 27 |
158 | 7a387fff | ths | #define CP0Ca_PCI 26 |
159 | 6af0bf9c | bellard | #define CP0Ca_IV 23 |
160 | 7a387fff | ths | #define CP0Ca_WP 22 |
161 | 7a387fff | ths | #define CP0Ca_IP 8 |
162 | 7a387fff | ths | #define CP0Ca_EC 2 |
163 | c570fd16 | ths | target_ulong CP0_EPC; |
164 | 6af0bf9c | bellard | uint32_t CP0_PRid; |
165 | c570fd16 | ths | target_ulong CP0_EBase; |
166 | 6af0bf9c | bellard | uint32_t CP0_Config0; |
167 | 6af0bf9c | bellard | #define CP0C0_M 31 |
168 | 6af0bf9c | bellard | #define CP0C0_K23 28 |
169 | 6af0bf9c | bellard | #define CP0C0_KU 25 |
170 | 6af0bf9c | bellard | #define CP0C0_MDU 20 |
171 | 6af0bf9c | bellard | #define CP0C0_MM 17 |
172 | 6af0bf9c | bellard | #define CP0C0_BM 16 |
173 | 6af0bf9c | bellard | #define CP0C0_BE 15 |
174 | 6af0bf9c | bellard | #define CP0C0_AT 13 |
175 | 6af0bf9c | bellard | #define CP0C0_AR 10 |
176 | 6af0bf9c | bellard | #define CP0C0_MT 7 |
177 | 7a387fff | ths | #define CP0C0_VI 3 |
178 | 6af0bf9c | bellard | #define CP0C0_K0 0 |
179 | 6af0bf9c | bellard | uint32_t CP0_Config1; |
180 | 7a387fff | ths | #define CP0C1_M 31 |
181 | 6af0bf9c | bellard | #define CP0C1_MMU 25 |
182 | 6af0bf9c | bellard | #define CP0C1_IS 22 |
183 | 6af0bf9c | bellard | #define CP0C1_IL 19 |
184 | 6af0bf9c | bellard | #define CP0C1_IA 16 |
185 | 6af0bf9c | bellard | #define CP0C1_DS 13 |
186 | 6af0bf9c | bellard | #define CP0C1_DL 10 |
187 | 6af0bf9c | bellard | #define CP0C1_DA 7 |
188 | 7a387fff | ths | #define CP0C1_C2 6 |
189 | 7a387fff | ths | #define CP0C1_MD 5 |
190 | 6af0bf9c | bellard | #define CP0C1_PC 4 |
191 | 6af0bf9c | bellard | #define CP0C1_WR 3 |
192 | 6af0bf9c | bellard | #define CP0C1_CA 2 |
193 | 6af0bf9c | bellard | #define CP0C1_EP 1 |
194 | 6af0bf9c | bellard | #define CP0C1_FP 0 |
195 | 7a387fff | ths | uint32_t CP0_Config2; |
196 | 7a387fff | ths | #define CP0C2_M 31 |
197 | 7a387fff | ths | #define CP0C2_TU 28 |
198 | 7a387fff | ths | #define CP0C2_TS 24 |
199 | 7a387fff | ths | #define CP0C2_TL 20 |
200 | 7a387fff | ths | #define CP0C2_TA 16 |
201 | 7a387fff | ths | #define CP0C2_SU 12 |
202 | 7a387fff | ths | #define CP0C2_SS 8 |
203 | 7a387fff | ths | #define CP0C2_SL 4 |
204 | 7a387fff | ths | #define CP0C2_SA 0 |
205 | 7a387fff | ths | uint32_t CP0_Config3; |
206 | 7a387fff | ths | #define CP0C3_M 31 |
207 | 7a387fff | ths | #define CP0C3_DSPP 10 |
208 | 7a387fff | ths | #define CP0C3_LPA 7 |
209 | 7a387fff | ths | #define CP0C3_VEIC 6 |
210 | 7a387fff | ths | #define CP0C3_VInt 5 |
211 | 7a387fff | ths | #define CP0C3_SP 4 |
212 | 7a387fff | ths | #define CP0C3_MT 2 |
213 | 7a387fff | ths | #define CP0C3_SM 1 |
214 | 7a387fff | ths | #define CP0C3_TL 0 |
215 | c570fd16 | ths | target_ulong CP0_LLAddr; |
216 | 6af0bf9c | bellard | uint32_t CP0_WatchLo; |
217 | 6af0bf9c | bellard | uint32_t CP0_WatchHi; |
218 | 7a387fff | ths | uint32_t CP0_XContext; |
219 | 7a387fff | ths | uint32_t CP0_Framemask; |
220 | 6af0bf9c | bellard | uint32_t CP0_Debug; |
221 | 6af0bf9c | bellard | #define CPDB_DBD 31 |
222 | 6af0bf9c | bellard | #define CP0DB_DM 30 |
223 | 6af0bf9c | bellard | #define CP0DB_LSNM 28 |
224 | 6af0bf9c | bellard | #define CP0DB_Doze 27 |
225 | 6af0bf9c | bellard | #define CP0DB_Halt 26 |
226 | 6af0bf9c | bellard | #define CP0DB_CNT 25 |
227 | 6af0bf9c | bellard | #define CP0DB_IBEP 24 |
228 | 6af0bf9c | bellard | #define CP0DB_DBEP 21 |
229 | 6af0bf9c | bellard | #define CP0DB_IEXI 20 |
230 | 6af0bf9c | bellard | #define CP0DB_VER 15 |
231 | 6af0bf9c | bellard | #define CP0DB_DEC 10 |
232 | 6af0bf9c | bellard | #define CP0DB_SSt 8 |
233 | 6af0bf9c | bellard | #define CP0DB_DINT 5 |
234 | 6af0bf9c | bellard | #define CP0DB_DIB 4 |
235 | 6af0bf9c | bellard | #define CP0DB_DDBS 3 |
236 | 6af0bf9c | bellard | #define CP0DB_DDBL 2 |
237 | 6af0bf9c | bellard | #define CP0DB_DBp 1 |
238 | 6af0bf9c | bellard | #define CP0DB_DSS 0 |
239 | c570fd16 | ths | target_ulong CP0_DEPC; |
240 | 7a387fff | ths | uint32_t CP0_Performance0; |
241 | 6af0bf9c | bellard | uint32_t CP0_TagLo; |
242 | 6af0bf9c | bellard | uint32_t CP0_DataLo; |
243 | 7a387fff | ths | uint32_t CP0_TagHi; |
244 | 7a387fff | ths | uint32_t CP0_DataHi; |
245 | c570fd16 | ths | target_ulong CP0_ErrorEPC; |
246 | 6af0bf9c | bellard | uint32_t CP0_DESAVE; |
247 | 6af0bf9c | bellard | /* Qemu */
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248 | 6af0bf9c | bellard | int interrupt_request;
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249 | 6af0bf9c | bellard | jmp_buf jmp_env; |
250 | 6af0bf9c | bellard | int exception_index;
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251 | 6af0bf9c | bellard | int error_code;
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252 | 6af0bf9c | bellard | int user_mode_only; /* user mode only simulation */ |
253 | 6af0bf9c | bellard | uint32_t hflags; /* CPU State */
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254 | 6af0bf9c | bellard | /* TMASK defines different execution modes */
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255 | 56b19403 | pbrook | #define MIPS_HFLAG_TMASK 0x007F |
256 | 6af0bf9c | bellard | #define MIPS_HFLAG_MODE 0x001F /* execution modes */ |
257 | 6af0bf9c | bellard | #define MIPS_HFLAG_UM 0x0001 /* user mode */ |
258 | 6af0bf9c | bellard | #define MIPS_HFLAG_ERL 0x0002 /* Error mode */ |
259 | 6af0bf9c | bellard | #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */ |
260 | 6af0bf9c | bellard | #define MIPS_HFLAG_DM 0x0008 /* Debug mode */ |
261 | 6af0bf9c | bellard | #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */ |
262 | 6af0bf9c | bellard | #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */ |
263 | 4ad40f36 | bellard | /* If translation is interrupted between the branch instruction and
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264 | 4ad40f36 | bellard | * the delay slot, record what type of branch it is so that we can
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265 | 4ad40f36 | bellard | * resume translation properly. It might be possible to reduce
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266 | 4ad40f36 | bellard | * this from three bits to two. */
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267 | 4ad40f36 | bellard | #define MIPS_HFLAG_BMASK 0x0380 |
268 | 4ad40f36 | bellard | #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */ |
269 | 4ad40f36 | bellard | #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */ |
270 | 4ad40f36 | bellard | #define MIPS_HFLAG_BL 0x0180 /* Likely branch */ |
271 | 4ad40f36 | bellard | #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */ |
272 | 6af0bf9c | bellard | target_ulong btarget; /* Jump / branch target */
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273 | 6af0bf9c | bellard | int bcond; /* Branch condition (if needed) */ |
274 | a316d335 | bellard | |
275 | 4ad40f36 | bellard | int halted; /* TRUE if the CPU is in suspend state */ |
276 | 4ad40f36 | bellard | |
277 | 7a387fff | ths | int SYNCI_Step; /* Address step size for SYNCI */ |
278 | 7a387fff | ths | int CCRes; /* Cycle count resolution/divisor */ |
279 | 7a387fff | ths | |
280 | a316d335 | bellard | CPU_COMMON |
281 | 6ae81775 | ths | |
282 | 6ae81775 | ths | int ram_size;
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283 | 6ae81775 | ths | const char *kernel_filename; |
284 | 6ae81775 | ths | const char *kernel_cmdline; |
285 | 6ae81775 | ths | const char *initrd_filename; |
286 | 6ae81775 | ths | |
287 | 6ae81775 | ths | struct QEMUTimer *timer; /* Internal timer */ |
288 | 6af0bf9c | bellard | }; |
289 | 6af0bf9c | bellard | |
290 | 6af0bf9c | bellard | #include "cpu-all.h" |
291 | 6af0bf9c | bellard | |
292 | 6af0bf9c | bellard | /* Memory access type :
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293 | 6af0bf9c | bellard | * may be needed for precise access rights control and precise exceptions.
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294 | 6af0bf9c | bellard | */
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295 | 6af0bf9c | bellard | enum {
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296 | 6af0bf9c | bellard | /* 1 bit to define user level / supervisor access */
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297 | 6af0bf9c | bellard | ACCESS_USER = 0x00,
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298 | 6af0bf9c | bellard | ACCESS_SUPER = 0x01,
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299 | 6af0bf9c | bellard | /* 1 bit to indicate direction */
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300 | 6af0bf9c | bellard | ACCESS_STORE = 0x02,
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301 | 6af0bf9c | bellard | /* Type of instruction that generated the access */
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302 | 6af0bf9c | bellard | ACCESS_CODE = 0x10, /* Code fetch access */ |
303 | 6af0bf9c | bellard | ACCESS_INT = 0x20, /* Integer load/store access */ |
304 | 6af0bf9c | bellard | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
305 | 6af0bf9c | bellard | }; |
306 | 6af0bf9c | bellard | |
307 | 6af0bf9c | bellard | /* Exceptions */
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308 | 6af0bf9c | bellard | enum {
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309 | 6af0bf9c | bellard | EXCP_NONE = -1,
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310 | 6af0bf9c | bellard | EXCP_RESET = 0,
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311 | 6af0bf9c | bellard | EXCP_SRESET, |
312 | 6af0bf9c | bellard | EXCP_DSS, |
313 | 6af0bf9c | bellard | EXCP_DINT, |
314 | 6af0bf9c | bellard | EXCP_NMI, |
315 | 6af0bf9c | bellard | EXCP_MCHECK, |
316 | 6af0bf9c | bellard | EXCP_EXT_INTERRUPT, |
317 | 6af0bf9c | bellard | EXCP_DFWATCH, |
318 | 6af0bf9c | bellard | EXCP_DIB, /* 8 */
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319 | 6af0bf9c | bellard | EXCP_IWATCH, |
320 | 6af0bf9c | bellard | EXCP_AdEL, |
321 | 6af0bf9c | bellard | EXCP_AdES, |
322 | 6af0bf9c | bellard | EXCP_TLBF, |
323 | 6af0bf9c | bellard | EXCP_IBE, |
324 | 6af0bf9c | bellard | EXCP_DBp, |
325 | 6af0bf9c | bellard | EXCP_SYSCALL, |
326 | 4ad40f36 | bellard | EXCP_BREAK, /* 16 */
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327 | 4ad40f36 | bellard | EXCP_CpU, |
328 | 6af0bf9c | bellard | EXCP_RI, |
329 | 6af0bf9c | bellard | EXCP_OVERFLOW, |
330 | 6af0bf9c | bellard | EXCP_TRAP, |
331 | 6af0bf9c | bellard | EXCP_DDBS, |
332 | 6af0bf9c | bellard | EXCP_DWATCH, |
333 | 4ad40f36 | bellard | EXCP_LAE, |
334 | 4ad40f36 | bellard | EXCP_SAE, /* 24 */
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335 | 6af0bf9c | bellard | EXCP_LTLBL, |
336 | 6af0bf9c | bellard | EXCP_TLBL, |
337 | 6af0bf9c | bellard | EXCP_TLBS, |
338 | 6af0bf9c | bellard | EXCP_DBE, |
339 | 6af0bf9c | bellard | EXCP_DDBL, |
340 | 6af0bf9c | bellard | EXCP_MTCP0 = 0x104, /* mtmsr instruction: */ |
341 | 6af0bf9c | bellard | /* may change privilege level */
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342 | 6af0bf9c | bellard | EXCP_BRANCH = 0x108, /* branch instruction */ |
343 | 6af0bf9c | bellard | EXCP_ERET = 0x10C, /* return from interrupt */ |
344 | 6af0bf9c | bellard | EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */ |
345 | 6af0bf9c | bellard | EXCP_FLUSH = 0x109,
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346 | 6af0bf9c | bellard | }; |
347 | 6af0bf9c | bellard | |
348 | 6af0bf9c | bellard | int cpu_mips_exec(CPUMIPSState *s);
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349 | 6af0bf9c | bellard | CPUMIPSState *cpu_mips_init(void);
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350 | 6af0bf9c | bellard | uint32_t cpu_mips_get_clock (void);
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351 | 6af0bf9c | bellard | |
352 | 6af0bf9c | bellard | #endif /* !defined (__MIPS_CPU_H__) */ |