Revision c570fd16 target-mips/cpu.h
| b/target-mips/cpu.h | ||
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| 15 | 15 |
typedef unsigned int uint_fast16_t; |
| 16 | 16 |
#endif |
| 17 | 17 |
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#ifdef MIPS_HAS_MIPS64 |
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#define SIGN_EXTEND32(val) (((((uint64_t)(val)) & 0xFFFFFFFF) ^ 0x80000000) - 0x80000000) |
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/* target_ulong size spec */ |
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#define TLSZ "%016llx" |
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#else |
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#define SIGN_EXTEND32(val) (val) |
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/* target_ulong size spec */ |
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#define TLSZ "%08x" |
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#endif |
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| 18 | 28 |
typedef union fpr_t fpr_t; |
| 19 | 29 |
union fpr_t {
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| 20 | 30 |
float64 fd; /* ieee double precision */ |
| ... | ... | |
| 55 | 65 |
target_ulong gpr[32]; |
| 56 | 66 |
/* Special registers */ |
| 57 | 67 |
target_ulong PC; |
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uint32_t HI, LO; |
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#if TARGET_LONG_BITS > HOST_LONG_BITS |
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target_ulong t0; |
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target_ulong t1; |
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target_ulong t2; |
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#endif |
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target_ulong HI, LO; |
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| 59 | 74 |
uint32_t DCR; /* ? */ |
| 60 | 75 |
#if defined(MIPS_USES_FPU) |
| 61 | 76 |
/* Floating point registers */ |
| ... | ... | |
| 106 | 121 |
uint32_t CP0_PageGrain; |
| 107 | 122 |
uint32_t CP0_Wired; |
| 108 | 123 |
uint32_t CP0_HWREna; |
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uint32_t CP0_BadVAddr;
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target_ulong CP0_BadVAddr;
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| 110 | 125 |
uint32_t CP0_Count; |
| 111 | 126 |
uint64_t CP0_EntryHi; |
| 112 | 127 |
uint32_t CP0_Compare; |
| ... | ... | |
| 145 | 160 |
#define CP0Ca_WP 22 |
| 146 | 161 |
#define CP0Ca_IP 8 |
| 147 | 162 |
#define CP0Ca_EC 2 |
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uint32_t CP0_EPC;
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target_ulong CP0_EPC;
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| 149 | 164 |
uint32_t CP0_PRid; |
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uint32_t CP0_EBase;
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target_ulong CP0_EBase;
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| 151 | 166 |
uint32_t CP0_Config0; |
| 152 | 167 |
#define CP0C0_M 31 |
| 153 | 168 |
#define CP0C0_K23 28 |
| ... | ... | |
| 197 | 212 |
#define CP0C3_MT 2 |
| 198 | 213 |
#define CP0C3_SM 1 |
| 199 | 214 |
#define CP0C3_TL 0 |
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uint32_t CP0_LLAddr;
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target_ulong CP0_LLAddr;
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| 201 | 216 |
uint32_t CP0_WatchLo; |
| 202 | 217 |
uint32_t CP0_WatchHi; |
| 203 | 218 |
uint32_t CP0_XContext; |
| ... | ... | |
| 221 | 236 |
#define CP0DB_DDBL 2 |
| 222 | 237 |
#define CP0DB_DBp 1 |
| 223 | 238 |
#define CP0DB_DSS 0 |
| 224 |
uint32_t CP0_DEPC;
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target_ulong CP0_DEPC;
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| 225 | 240 |
uint32_t CP0_Performance0; |
| 226 | 241 |
uint32_t CP0_TagLo; |
| 227 | 242 |
uint32_t CP0_DataLo; |
| 228 | 243 |
uint32_t CP0_TagHi; |
| 229 | 244 |
uint32_t CP0_DataHi; |
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uint32_t CP0_ErrorEPC;
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target_ulong CP0_ErrorEPC;
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| 231 | 246 |
uint32_t CP0_DESAVE; |
| 232 | 247 |
/* Qemu */ |
| 233 | 248 |
int interrupt_request; |
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