Revision c570fd16 target-mips/op_mem.c
b/target-mips/op_mem.c | ||
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/* "half" load and stores. We must do the memory access inline, |
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or fault handling won't work. */ |
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/* XXX: This is broken, CP0_BADVADDR has the wrong (aligned) value. */ |
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void glue(op_lwl, MEMSUFFIX) (void) |
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{ |
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uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3); |
... | ... | |
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RETURN(); |
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} |
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#ifdef MIPS_HAS_MIPS64 |
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void glue(op_ld, MEMSUFFIX) (void) |
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{ |
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T0 = glue(ldq, MEMSUFFIX)(T0); |
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RETURN(); |
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} |
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void glue(op_sd, MEMSUFFIX) (void) |
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{ |
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glue(stq, MEMSUFFIX)(T0, T1); |
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RETURN(); |
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} |
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/* "half" load and stores. We must do the memory access inline, |
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or fault handling won't work. */ |
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void glue(op_ldl, MEMSUFFIX) (void) |
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{ |
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7); |
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CALL_FROM_TB1(glue(do_ldl, MEMSUFFIX), tmp); |
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RETURN(); |
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} |
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void glue(op_ldr, MEMSUFFIX) (void) |
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{ |
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7); |
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CALL_FROM_TB1(glue(do_ldr, MEMSUFFIX), tmp); |
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RETURN(); |
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} |
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void glue(op_sdl, MEMSUFFIX) (void) |
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{ |
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7); |
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tmp = CALL_FROM_TB1(glue(do_sdl, MEMSUFFIX), tmp); |
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glue(stq, MEMSUFFIX)(T0 & ~7, tmp); |
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RETURN(); |
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} |
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void glue(op_sdr, MEMSUFFIX) (void) |
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{ |
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7); |
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tmp = CALL_FROM_TB1(glue(do_sdr, MEMSUFFIX), tmp); |
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glue(stq, MEMSUFFIX)(T0 & ~7, tmp); |
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RETURN(); |
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} |
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void glue(op_lld, MEMSUFFIX) (void) |
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{ |
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T1 = T0; |
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T0 = glue(ldq, MEMSUFFIX)(T0); |
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env->CP0_LLAddr = T1; |
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RETURN(); |
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} |
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void glue(op_scd, MEMSUFFIX) (void) |
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{ |
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CALL_FROM_TB0(dump_sc); |
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if (T0 == env->CP0_LLAddr) { |
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glue(stq, MEMSUFFIX)(T0, T1); |
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T0 = 1; |
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} else { |
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T0 = 0; |
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} |
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RETURN(); |
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} |
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#endif /* MIPS_HAS_MIPS64 */ |
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|
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#ifdef MIPS_USES_FPU |
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void glue(op_lwc1, MEMSUFFIX) (void) |
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{ |
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