Revision c570fd16 target-mips/translate.c

b/target-mips/translate.c
31 31
#include "disas.h"
32 32

  
33 33
//#define MIPS_DEBUG_DISAS
34
//#define MIPS_DEBUG_SIGN_EXTENSIONS
34 35
//#define MIPS_SINGLE_STEP
35 36

  
36 37
#ifdef USE_DIRECT_JUMP
......
502 503
#define MIPS_DEBUG(fmt, args...)                                              \
503 504
do {                                                                          \
504 505
    if (loglevel & CPU_LOG_TB_IN_ASM) {                                       \
505
        fprintf(logfile, "%08x: %08x " fmt "\n",                              \
506
        fprintf(logfile, TLSZ ": %08x " fmt "\n",                             \
506 507
                ctx->pc, ctx->opcode , ##args);                               \
507 508
    }                                                                         \
508 509
} while (0)
......
621 622
OP_ST_TABLE(d);
622 623
OP_ST_TABLE(dl);
623 624
OP_ST_TABLE(dr);
625
OP_LD_TABLE(ld);
626
OP_ST_TABLE(cd);
624 627
#endif
625 628
OP_LD_TABLE(w);
626 629
OP_LD_TABLE(wu);
......
1417 1420
    case OPC_J:
1418 1421
    case OPC_JAL:
1419 1422
        /* Jump to immediate */
1420
        btarget = ((ctx->pc + 4) & 0xF0000000) | offset;
1423
        btarget = ((ctx->pc + 4) & SIGN_EXTEND32(0xF0000000)) | offset;
1421 1424
        break;
1422 1425
    case OPC_JR:
1423 1426
    case OPC_JALR:
......
2927 2930
    switch (op) {
2928 2931
    case OPC_BC1F:
2929 2932
        gen_op_bc1f();
2930
        MIPS_DEBUG("bc1f %08x", btarget);
2933
        MIPS_DEBUG("bc1f " TLSZ, btarget);
2931 2934
        goto not_likely;
2932 2935
    case OPC_BC1FL:
2933 2936
        gen_op_bc1f();
2934
        MIPS_DEBUG("bc1fl %08x", btarget);
2937
        MIPS_DEBUG("bc1fl " TLSZ, btarget);
2935 2938
        goto likely;
2936 2939
    case OPC_BC1T:
2937 2940
        gen_op_bc1t();
2938
        MIPS_DEBUG("bc1t %08x", btarget);
2941
        MIPS_DEBUG("bc1t " TLSZ, btarget);
2939 2942
    not_likely:
2940 2943
        ctx->hflags |= MIPS_HFLAG_BC;
2941 2944
        break;
2942 2945
    case OPC_BC1TL:
2943 2946
        gen_op_bc1t();
2944
        MIPS_DEBUG("bc1tl %08x", btarget);
2947
        MIPS_DEBUG("bc1tl " TLSZ, btarget);
2945 2948
    likely:
2946 2949
        ctx->hflags |= MIPS_HFLAG_BL;
2947 2950
        break;
......
2952 2955
    }
2953 2956
    gen_op_set_bcond();
2954 2957

  
2955
    MIPS_DEBUG("enter ds: cond %02x target %08x",
2958
    MIPS_DEBUG("enter ds: cond %02x target " TLSZ,
2956 2959
               ctx->hflags, btarget);
2957 2960
    ctx->btarget = btarget;
2958 2961

  
......
3351 3354
/* SmartMIPS extension to MIPS32 */
3352 3355

  
3353 3356
#ifdef MIPS_HAS_MIPS64
3354
static void gen_arith64 (DisasContext *ctx, uint32_t opc)
3355
{
3356
    if (func == 0x02 && rd == 0) {
3357
        /* NOP */
3358
        return;
3359
    }
3360
    if (rs == 0 || rt == 0) {
3361
        gen_op_reset_T0();
3362
        gen_op_save64();
3363
    } else {
3364
        gen_op_load_gpr_T0(rs);
3365
        gen_op_load_gpr_T1(rt);
3366
        gen_op_save64();
3367
        if (func & 0x01)
3368
            gen_op_mul64u();
3369
        else
3370
            gen_op_mul64s();
3371
    }
3372
    if (func & 0x02)
3373
        gen_op_add64();
3374
    else
3375
        gen_op_sub64();
3376
}
3377

  
3378 3357
/* Coprocessor 3 (FPU) */
3379 3358

  
3380 3359
/* MDMX extension to MIPS64 */
......
3407 3386

  
3408 3387
    if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
3409 3388
        /* Handle blikely not taken case */
3410
        MIPS_DEBUG("blikely condition (%08x)", ctx->pc + 4);
3389
        MIPS_DEBUG("blikely condition (" TLSZ ")", ctx->pc + 4);
3411 3390
        gen_blikely(ctx);
3412 3391
    }
3413 3392
    op = MASK_OP_MAJOR(ctx->opcode);
......
4011 3990
void dump_fpu (CPUState *env)
4012 3991
{
4013 3992
    if (loglevel) { 
4014
       fprintf(logfile, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
3993
       fprintf(logfile, "pc=0x" TLSZ " HI=0x" TLSZ " LO=0x" TLSZ " ds %04x " TLSZ " %d\n",
4015 3994
               env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
4016 3995
       fpu_dump_state(env, logfile, fprintf, 0);
4017 3996
    }
......
4019 3998

  
4020 3999
#endif /* MIPS_USES_FPU */
4021 4000

  
4001
#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
4002
/* Debug help: The architecture requires 32bit code to maintain proper
4003
   sign-extened values on 64bit machines.  */
4004

  
4005
#define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
4006

  
4007
void cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
4008
                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
4009
                     int flags)
4010
{
4011
    int i;
4012

  
4013
    if (!SIGN_EXT_P(env->PC))
4014
        cpu_fprintf(f, "BROKEN: pc=0x" TLSZ "\n", env->PC);
4015
    if (!SIGN_EXT_P(env->HI))
4016
        cpu_fprintf(f, "BROKEN: HI=0x" TLSZ "\n", env->HI);
4017
    if (!SIGN_EXT_P(env->LO))
4018
        cpu_fprintf(f, "BROKEN: LO=0x" TLSZ "\n", env->LO);
4019
    if (!SIGN_EXT_P(env->btarget))
4020
        cpu_fprintf(f, "BROKEN: btarget=0x" TLSZ "\n", env->btarget);
4021

  
4022
    for (i = 0; i < 32; i++) {
4023
        if (!SIGN_EXT_P(env->gpr[i]))
4024
            cpu_fprintf(f, "BROKEN: %s=0x" TLSZ "\n", regnames[i], env->gpr[i]);
4025
    }
4026

  
4027
    if (!SIGN_EXT_P(env->CP0_EPC))
4028
        cpu_fprintf(f, "BROKEN: EPC=0x" TLSZ "\n", env->CP0_EPC);
4029
    if (!SIGN_EXT_P(env->CP0_LLAddr))
4030
        cpu_fprintf(f, "BROKEN: LLAddr=0x" TLSZ "\n", env->CP0_LLAddr);
4031
}
4032
#endif
4033

  
4022 4034
void cpu_dump_state (CPUState *env, FILE *f, 
4023 4035
                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
4024 4036
                     int flags)
......
4026 4038
    uint32_t c0_status;
4027 4039
    int i;
4028 4040
    
4029
    cpu_fprintf(f, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
4041
    cpu_fprintf(f, "pc=0x" TLSZ " HI=0x" TLSZ " LO=0x" TLSZ " ds %04x " TLSZ " %d\n",
4030 4042
                env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond);
4031 4043
    for (i = 0; i < 32; i++) {
4032 4044
        if ((i & 3) == 0)
4033 4045
            cpu_fprintf(f, "GPR%02d:", i);
4034
        cpu_fprintf(f, " %s %08x", regnames[i], env->gpr[i]);
4046
        cpu_fprintf(f, " %s " TLSZ, regnames[i], env->gpr[i]);
4035 4047
        if ((i & 3) == 3)
4036 4048
            cpu_fprintf(f, "\n");
4037 4049
    }
......
4044 4056
    if (env->hflags & MIPS_HFLAG_EXL)
4045 4057
        c0_status |= (1 << CP0St_EXL);
4046 4058

  
4047
    cpu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x%08x\n",
4059
    cpu_fprintf(f, "CP0 Status  0x%08x Cause   0x%08x EPC    0x" TLSZ "\n",
4048 4060
                c0_status, env->CP0_Cause, env->CP0_EPC);
4049
    cpu_fprintf(f, "    Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",
4061
    cpu_fprintf(f, "    Config0 0x%08x Config1 0x%08x LLAddr 0x" TLSZ "\n",
4050 4062
                env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
4051 4063
#ifdef MIPS_USES_FPU
4052 4064
    if (c0_status & (1 << CP0St_CU1))
4053 4065
        fpu_dump_state(env, f, cpu_fprintf, flags);
4054 4066
#endif
4067
#if defined(MIPS_HAS_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
4068
    cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
4069
#endif
4055 4070
}
4056 4071

  
4057 4072
CPUMIPSState *cpu_mips_init (void)
......
4082 4097
    } else {
4083 4098
        env->CP0_ErrorEPC = env->PC;
4084 4099
    }
4085
    env->PC = 0xBFC00000;
4100
    env->PC = SIGN_EXTEND32(0xBFC00000);
4086 4101
#if defined (MIPS_USES_R4K_TLB)
4087 4102
    env->CP0_random = MIPS_TLB_NB - 1;
4088 4103
    env->tlb_in_use = MIPS_TLB_NB;
4089 4104
#endif
4090 4105
    env->CP0_Wired = 0;
4091 4106
    /* SMP not implemented */
4092
    env->CP0_EBase = 0x80000000;
4107
    env->CP0_EBase = SIGN_EXTEND32(0x80000000);
4093 4108
    env->CP0_Config0 = MIPS_CONFIG0;
4094 4109
    env->CP0_Config1 = MIPS_CONFIG1;
4095 4110
    env->CP0_Config2 = MIPS_CONFIG2;

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