root / hw / m48t59.c @ c5df018e
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/*
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* QEMU M48T59 NVRAM emulation for PPC PREP platform
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*
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* Copyright (c) 2003-2004 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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#include "m48t59.h" |
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//#define NVRAM_DEBUG
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#if defined(NVRAM_DEBUG)
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#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
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#else
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#define NVRAM_PRINTF(fmt, args...) do { } while (0) |
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#endif
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struct m48t59_t {
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/* Hardware parameters */
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int IRQ;
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uint32_t io_base; |
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uint16_t size; |
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/* RTC management */
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time_t time_offset; |
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time_t stop_time; |
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/* Alarm & watchdog */
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time_t alarm; |
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struct QEMUTimer *alrm_timer;
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struct QEMUTimer *wd_timer;
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/* NVRAM storage */
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uint16_t addr; |
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uint8_t *buffer; |
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}; |
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|
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/* Fake timer functions */
|
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/* Generic helpers for BCD */
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static inline uint8_t toBCD (uint8_t value) |
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{
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return (((value / 10) % 10) << 4) | (value % 10); |
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} |
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|
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static inline uint8_t fromBCD (uint8_t BCD) |
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{
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return ((BCD >> 4) * 10) + (BCD & 0x0F); |
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} |
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|
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/* RTC management helpers */
|
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static void get_time (m48t59_t *NVRAM, struct tm *tm) |
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{
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time_t t; |
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|
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t = time(NULL) + NVRAM->time_offset;
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localtime_r(&t, tm); |
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} |
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|
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static void set_time (m48t59_t *NVRAM, struct tm *tm) |
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{
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time_t now, new_time; |
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|
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new_time = mktime(tm); |
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now = time(NULL);
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NVRAM->time_offset = new_time - now; |
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} |
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|
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/* Alarm management */
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static void alarm_cb (void *opaque) |
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{
|
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struct tm tm, tm_now;
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uint64_t next_time; |
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m48t59_t *NVRAM = opaque; |
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|
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pic_set_irq(NVRAM->IRQ, 1);
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if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a month */
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get_time(NVRAM, &tm_now); |
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memcpy(&tm, &tm_now, sizeof(struct tm)); |
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tm.tm_mon++; |
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if (tm.tm_mon == 13) { |
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tm.tm_mon = 1;
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tm.tm_year++; |
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} |
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next_time = mktime(&tm); |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a day */
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next_time = 24 * 60 * 60 + mktime(&tm_now); |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once an hour */
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next_time = 60 * 60 + mktime(&tm_now); |
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
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/* Repeat once a minute */
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next_time = 60 + mktime(&tm_now);
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} else {
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/* Repeat once a second */
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next_time = 1 + mktime(&tm_now);
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} |
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qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
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pic_set_irq(NVRAM->IRQ, 0);
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} |
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static void get_alarm (m48t59_t *NVRAM, struct tm *tm) |
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{
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localtime_r(&NVRAM->alarm, tm); |
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} |
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static void set_alarm (m48t59_t *NVRAM, struct tm *tm) |
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{
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NVRAM->alarm = mktime(tm); |
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if (NVRAM->alrm_timer != NULL) { |
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qemu_del_timer(NVRAM->alrm_timer); |
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NVRAM->alrm_timer = NULL;
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} |
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if (NVRAM->alarm - time(NULL) > 0) |
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qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
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} |
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|
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/* Watchdog management */
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static void watchdog_cb (void *opaque) |
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{
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m48t59_t *NVRAM = opaque; |
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|
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NVRAM->buffer[0x1FF0] |= 0x80; |
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if (NVRAM->buffer[0x1FF7] & 0x80) { |
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NVRAM->buffer[0x1FF7] = 0x00; |
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NVRAM->buffer[0x1FFC] &= ~0x40; |
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// reset_CPU();
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} else {
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pic_set_irq(NVRAM->IRQ, 1);
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pic_set_irq(NVRAM->IRQ, 0);
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} |
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} |
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static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) |
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{
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uint64_t interval; /* in 1/16 seconds */
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if (NVRAM->wd_timer != NULL) { |
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qemu_del_timer(NVRAM->wd_timer); |
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NVRAM->wd_timer = NULL;
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} |
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NVRAM->buffer[0x1FF0] &= ~0x80; |
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if (value != 0) { |
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interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
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qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
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((interval * 1000) >> 4)); |
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} |
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} |
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|
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/* Direct access to NVRAM */
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void m48t59_write (m48t59_t *NVRAM, uint32_t val)
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{
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struct tm tm;
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int tmp;
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|
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if (NVRAM->addr > 0x1FF8 && NVRAM->addr < 0x2000) |
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, NVRAM->addr, val);
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switch (NVRAM->addr) {
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case 0x1FF0: |
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/* flags register : read-only */
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break;
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case 0x1FF1: |
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/* unused */
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break;
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case 0x1FF2: |
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/* alarm seconds */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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get_alarm(NVRAM, &tm); |
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tm.tm_sec = tmp; |
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NVRAM->buffer[0x1FF2] = val;
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set_alarm(NVRAM, &tm); |
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} |
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break;
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case 0x1FF3: |
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/* alarm minutes */
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tmp = fromBCD(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) { |
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get_alarm(NVRAM, &tm); |
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tm.tm_min = tmp; |
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NVRAM->buffer[0x1FF3] = val;
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set_alarm(NVRAM, &tm); |
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} |
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break;
|
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case 0x1FF4: |
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/* alarm hours */
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tmp = fromBCD(val & 0x3F);
|
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if (tmp >= 0 && tmp <= 23) { |
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get_alarm(NVRAM, &tm); |
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tm.tm_hour = tmp; |
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NVRAM->buffer[0x1FF4] = val;
|
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set_alarm(NVRAM, &tm); |
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} |
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break;
|
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case 0x1FF5: |
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/* alarm date */
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tmp = fromBCD(val & 0x1F);
|
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if (tmp != 0) { |
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get_alarm(NVRAM, &tm); |
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tm.tm_mday = tmp; |
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NVRAM->buffer[0x1FF5] = val;
|
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set_alarm(NVRAM, &tm); |
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} |
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break;
|
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case 0x1FF6: |
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/* interrupts */
|
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NVRAM->buffer[0x1FF6] = val;
|
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break;
|
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case 0x1FF7: |
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/* watchdog */
|
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NVRAM->buffer[0x1FF7] = val;
|
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set_up_watchdog(NVRAM, val); |
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break;
|
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case 0x1FF8: |
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/* control */
|
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NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90; |
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break;
|
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case 0x1FF9: |
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/* seconds (BCD) */
|
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tmp = fromBCD(val & 0x7F);
|
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if (tmp >= 0 && tmp <= 59) { |
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get_time(NVRAM, &tm); |
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tm.tm_sec = tmp; |
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set_time(NVRAM, &tm); |
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} |
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if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) { |
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if (val & 0x80) { |
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NVRAM->stop_time = time(NULL);
|
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} else {
|
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NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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NVRAM->stop_time = 0;
|
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} |
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} |
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NVRAM->buffer[0x1FF9] = val & 0x80; |
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break;
|
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case 0x1FFA: |
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/* minutes (BCD) */
|
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tmp = fromBCD(val & 0x7F);
|
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if (tmp >= 0 && tmp <= 59) { |
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get_time(NVRAM, &tm); |
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tm.tm_min = tmp; |
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set_time(NVRAM, &tm); |
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} |
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break;
|
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case 0x1FFB: |
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/* hours (BCD) */
|
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tmp = fromBCD(val & 0x3F);
|
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if (tmp >= 0 && tmp <= 23) { |
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get_time(NVRAM, &tm); |
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tm.tm_hour = tmp; |
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set_time(NVRAM, &tm); |
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} |
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break;
|
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case 0x1FFC: |
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/* day of the week / century */
|
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tmp = fromBCD(val & 0x07);
|
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get_time(NVRAM, &tm); |
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tm.tm_wday = tmp; |
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set_time(NVRAM, &tm); |
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NVRAM->buffer[0x1FFC] = val & 0x40; |
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break;
|
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case 0x1FFD: |
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/* date */
|
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tmp = fromBCD(val & 0x1F);
|
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if (tmp != 0) { |
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get_time(NVRAM, &tm); |
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tm.tm_mday = tmp; |
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set_time(NVRAM, &tm); |
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} |
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break;
|
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case 0x1FFE: |
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/* month */
|
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tmp = fromBCD(val & 0x1F);
|
| 302 |
if (tmp >= 1 && tmp <= 12) { |
| 303 |
get_time(NVRAM, &tm); |
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tm.tm_mon = tmp - 1;
|
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set_time(NVRAM, &tm); |
| 306 |
} |
| 307 |
break;
|
| 308 |
case 0x1FFF: |
| 309 |
/* year */
|
| 310 |
tmp = fromBCD(val); |
| 311 |
if (tmp >= 0 && tmp <= 99) { |
| 312 |
get_time(NVRAM, &tm); |
| 313 |
tm.tm_year = fromBCD(val); |
| 314 |
set_time(NVRAM, &tm); |
| 315 |
} |
| 316 |
break;
|
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default:
|
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if (NVRAM->addr < 0x1FF0 || |
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(NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
|
| 320 |
NVRAM->buffer[NVRAM->addr] = val & 0xFF;
|
| 321 |
} |
| 322 |
break;
|
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} |
| 324 |
} |
| 325 |
|
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uint32_t m48t59_read (m48t59_t *NVRAM) |
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{
|
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struct tm tm;
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uint32_t retval = 0xFF;
|
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|
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switch (NVRAM->addr) {
|
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case 0x1FF0: |
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/* flags register */
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goto do_read;
|
| 335 |
case 0x1FF1: |
| 336 |
/* unused */
|
| 337 |
retval = 0;
|
| 338 |
break;
|
| 339 |
case 0x1FF2: |
| 340 |
/* alarm seconds */
|
| 341 |
goto do_read;
|
| 342 |
case 0x1FF3: |
| 343 |
/* alarm minutes */
|
| 344 |
goto do_read;
|
| 345 |
case 0x1FF4: |
| 346 |
/* alarm hours */
|
| 347 |
goto do_read;
|
| 348 |
case 0x1FF5: |
| 349 |
/* alarm date */
|
| 350 |
goto do_read;
|
| 351 |
case 0x1FF6: |
| 352 |
/* interrupts */
|
| 353 |
goto do_read;
|
| 354 |
case 0x1FF7: |
| 355 |
/* A read resets the watchdog */
|
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set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
|
| 357 |
goto do_read;
|
| 358 |
case 0x1FF8: |
| 359 |
/* control */
|
| 360 |
goto do_read;
|
| 361 |
case 0x1FF9: |
| 362 |
/* seconds (BCD) */
|
| 363 |
get_time(NVRAM, &tm); |
| 364 |
retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec); |
| 365 |
break;
|
| 366 |
case 0x1FFA: |
| 367 |
/* minutes (BCD) */
|
| 368 |
get_time(NVRAM, &tm); |
| 369 |
retval = toBCD(tm.tm_min); |
| 370 |
break;
|
| 371 |
case 0x1FFB: |
| 372 |
/* hours (BCD) */
|
| 373 |
get_time(NVRAM, &tm); |
| 374 |
retval = toBCD(tm.tm_hour); |
| 375 |
break;
|
| 376 |
case 0x1FFC: |
| 377 |
/* day of the week / century */
|
| 378 |
get_time(NVRAM, &tm); |
| 379 |
retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
|
| 380 |
break;
|
| 381 |
case 0x1FFD: |
| 382 |
/* date */
|
| 383 |
get_time(NVRAM, &tm); |
| 384 |
retval = toBCD(tm.tm_mday); |
| 385 |
break;
|
| 386 |
case 0x1FFE: |
| 387 |
/* month */
|
| 388 |
get_time(NVRAM, &tm); |
| 389 |
retval = toBCD(tm.tm_mon + 1);
|
| 390 |
break;
|
| 391 |
case 0x1FFF: |
| 392 |
/* year */
|
| 393 |
get_time(NVRAM, &tm); |
| 394 |
retval = toBCD(tm.tm_year); |
| 395 |
break;
|
| 396 |
default:
|
| 397 |
if (NVRAM->addr < 0x1FF0 || |
| 398 |
(NVRAM->addr > 0x1FFF && NVRAM->addr < NVRAM->size)) {
|
| 399 |
do_read:
|
| 400 |
retval = NVRAM->buffer[NVRAM->addr]; |
| 401 |
} |
| 402 |
break;
|
| 403 |
} |
| 404 |
if (NVRAM->addr > 0x1FF9 && NVRAM->addr < 0x2000) |
| 405 |
NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM->addr, retval);
|
| 406 |
|
| 407 |
return retval;
|
| 408 |
} |
| 409 |
|
| 410 |
void m48t59_set_addr (m48t59_t *NVRAM, uint32_t addr)
|
| 411 |
{
|
| 412 |
NVRAM->addr = addr; |
| 413 |
} |
| 414 |
|
| 415 |
/* IO access to NVRAM */
|
| 416 |
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
| 417 |
{
|
| 418 |
m48t59_t *NVRAM = opaque; |
| 419 |
|
| 420 |
addr -= NVRAM->io_base; |
| 421 |
switch (addr) {
|
| 422 |
case 0: |
| 423 |
NVRAM->addr &= ~0x00FF;
|
| 424 |
NVRAM->addr |= val; |
| 425 |
break;
|
| 426 |
case 1: |
| 427 |
NVRAM->addr &= ~0xFF00;
|
| 428 |
NVRAM->addr |= val << 8;
|
| 429 |
break;
|
| 430 |
case 3: |
| 431 |
m48t59_write(NVRAM, val); |
| 432 |
NVRAM->addr = 0x0000;
|
| 433 |
break;
|
| 434 |
default:
|
| 435 |
break;
|
| 436 |
} |
| 437 |
} |
| 438 |
|
| 439 |
static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
| 440 |
{
|
| 441 |
m48t59_t *NVRAM = opaque; |
| 442 |
|
| 443 |
if (addr == NVRAM->io_base + 3) |
| 444 |
return m48t59_read(NVRAM);
|
| 445 |
|
| 446 |
return 0xFF; |
| 447 |
} |
| 448 |
|
| 449 |
/* Initialisation routine */
|
| 450 |
m48t59_t *m48t59_init (int IRQ, uint32_t io_base, uint16_t size)
|
| 451 |
{
|
| 452 |
m48t59_t *s; |
| 453 |
|
| 454 |
s = qemu_mallocz(sizeof(m48t59_t));
|
| 455 |
if (!s)
|
| 456 |
return NULL; |
| 457 |
s->buffer = qemu_mallocz(size); |
| 458 |
if (!s->buffer) {
|
| 459 |
qemu_free(s); |
| 460 |
return NULL; |
| 461 |
} |
| 462 |
s->IRQ = IRQ; |
| 463 |
s->size = size; |
| 464 |
s->io_base = io_base; |
| 465 |
s->addr = 0;
|
| 466 |
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); |
| 467 |
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); |
| 468 |
s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s); |
| 469 |
s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s); |
| 470 |
return s;
|
| 471 |
} |