Archipelago » qemu

//#define DEBUG_CONSOLE

#define DEFAULT_BACKSCROLL 512

#define MAX_CONSOLES 12

#define QEMU_RGBA(r, g, b, a) (((a) << 24) | ((r) << 16) | ((g) << 8) | (b))

#define QEMU_RGB(r, g, b) QEMU_RGBA(r, g, b, 0xff)

typedef enum {

    GRAPHIC_CONSOLE,

} console_type_t;

/* ??? This is mis-named.

    s = consoles[index];

    if (s) {

        active_console = s;

        vga_hw_invalidate();

    }

}

{

    TextConsole *s = (TextConsole *) opaque;

    console_refresh(s);

}

    chr = qemu_mallocz(sizeof(CharDriverState));

    if (!chr)

        return NULL;

    if (!s) {

        free(chr);

        return NULL;

    }

    chr->opaque = s;

    chr->chr_write = console_puts;

    chr->chr_send_event = console_send_event;

    return chr;

}

CharDriverState *text_console_init(DisplayState *ds, const char *p);

void console_select(unsigned int index);

void console_color_init(DisplayState *ds);

/* sdl.c */

void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);

    uint8_t iformat;

    uint8_t source;

    DisplayState *state;

    blizzard_fn_t *line_fn_tab[2];

    void *fb;

    if (s->x != s->state->width || s->y != s->state->height) {

        s->invalidate = 1;

    }

    if (s->invalidate) {

    blizzard_reset(s);

    return s;

}

                    ds, vga_ram_base, vga_ram_offset, vga_ram_size);

    cirrus_init_common(s, device_id, 1);

    s->pci_dev = (PCIDevice *)d;

    uint8_t palette[256][3];

    /* display refresh support */

    DisplayState *ds;

    int graphic_mode;

    uint32_t scr_width, scr_height; /* in pixels */

    uint32_t last_scr_width, last_scr_height; /* in pixels */

{

    if (s->scr_width == 0 || s->scr_height == 0)

        return;

    switch (s->ds->depth) {

        case 8:

#endif

                break;

        }

    }

}

static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val)

    s->ds = ds;

    s->vram_base = vram_base;

    io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);

    cpu_register_physical_memory(s->vram_base, vram_size, io_vram);

    target_phys_addr_t base;

    uint8_t segments;

    DisplayState *ds;

    screen_state_t state;

} LedState;

    char buf[2];

    dpy_cursor(s->ds, -1, -1);

    /* TODO: draw the segments */

    snprintf(buf, 2, "%02hhx\n", s->segments);

    io = cpu_register_io_memory(0, led_read, led_write, s);

    cpu_register_physical_memory(s->base, 1, io);

}

    int page;

    int page_off;

    DisplayState *ds;

    uint8_t video_ram[128*64/8];

} musicpal_lcd_state;

static uint32_t lcd_brightness;

    musicpal_lcd_state *s = opaque;

    int x, y, col;

    switch (s->ds->depth) {

    case 0:

        return;

static void lcd_invalidate(void *opaque)

{

}

static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)

        return;

    s->base = base;

    s->ds = ds;

    iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,

                                       musicpal_lcd_writefn, s);

    cpu_register_physical_memory(base, MP_LCD_SIZE, iomemtype);

}

/* PIC register offsets */

        n800_setup_nolo_tags(phys_ram_base + sdram_size);

    }

    dpy_resize(ds, 800, 480);

}

    target_phys_addr_t base;

    qemu_irq irq;

    DisplayState *state;

    ram_addr_t imif_base;

    ram_addr_t emiff_base;

    width = omap_lcd->width;

    if (width != omap_lcd->state->width ||

            omap_lcd->height != omap_lcd->state->height) {

        omap_lcd->invalidate = 1;

    }

                    omap_lcdc_writefn, s);

    cpu_register_physical_memory(s->base, 0x100, iomemtype);

    return s;

}

        arm_load_kernel(cpu->env, &palmte_binfo);

    }

    dpy_resize(ds, 320, 320);

}

typedef struct {

    uint32_t base;

    DisplayState *ds;

    /* The Versatile/PB uses a slightly modified PL110 controller.  */

    int versatile;

    uint32_t timing[4];

{

    if (width != s->cols || height != s->rows) {

        if (pl110_enabled(s)) {

        }

    }

    s->cols = width;

        s->cr = val;

        s->bpp = (val >> 1) & 7;

        if (pl110_enabled(s)) {

        }

        break;

    case 10: /* LCDICR */

    s->ds = ds;

    s->versatile = versatile;

    s->irq = irq;

    /* ??? Save/restore.  */

    return s;

}

    int invalidated;

    DisplayState *ds;

    drawfn *line_fn[2];

    int dest_width;

    int xres, yres;

    if (width != s->xres || height != s->yres) {

        if (s->orientation)

        else

        s->invalidated = 1;

        s->xres = width;

        s->yres = height;

                    pxa2xx_lcdc_writefn, s);

    cpu_register_physical_memory(base, 0x00100000, iomemtype);

    switch (s->ds->depth) {

    case 0:

typedef struct {

    i2c_slave i2c;

    DisplayState *ds;

    int row;

    int col;

    int start_line;

    s->i2c.event = ssd0303_event;

    s->i2c.recv = ssd0303_recv;

    s->i2c.send = ssd0303_send;

}

typedef struct {

    DisplayState *ds;

    int cmd_len;

    int cmd;

    qemu_irq *cmd;

    s = (ssd0323_state *)qemu_mallocz(sizeof(ssd0323_state));

    s->col_end = 63;

    s->row_end = 79;

    cmd = qemu_allocate_irqs(ssd0323_cd, s, 1);

    *cmd_p = *cmd;

typedef struct TCXState {

    target_phys_addr_t addr;

    DisplayState *ds;

    uint8_t *vram;

    uint32_t *vram24, *cplane;

    ram_addr_t vram_offset, vram24_offset, cplane_offset;

    if (ts->ds->depth == 0)

        return;

    page = ts->vram_offset;

    y_start = -1;

    page_min = 0xffffffff;

    if (ts->ds->depth != 32)

            return;

    page = ts->vram_offset;

    page24 = ts->vram24_offset;

    cpage = ts->cplane_offset;

        s->cplane = (uint32_t *)vram_base;

        s->cplane_offset = vram_offset;

        cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);

    } else {

        cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,

                                     dummy_memory);

    }

    // NetBSD writes here even with 8-bit display

    cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,

    register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);

    qemu_register_reset(tcx_reset, s);

    tcx_reset(s);

}

static void tcx_screen_dump(void *opaque, const char *filename)

        cw != s->last_cw || cheight != s->last_ch) {

        s->last_scr_width = width * cw;

        s->last_scr_height = height * cheight;

        s->last_width = width;

        s->last_height = height;

        s->last_ch = cheight;

    if (disp_width != s->last_width ||

        height != s->last_height) {

        s->last_scr_width = disp_width;

        s->last_scr_height = height;

        s->last_width = disp_width;

            cw != s->last_cw || cheight != s->last_ch) {

            s->last_scr_width = width * cw;

            s->last_scr_height = height * cheight;

            s->last_width = width;

            s->last_height = height;

            s->last_ch = cheight;

    s->last_width = 60;

    s->last_height = height = 3;

    dpy_cursor(s->ds, -1, -1);

    for (dst = chardata, i = 0; i < s->last_width * height; i ++)

        console_write_ch(dst ++, ' ');

    vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);

    vga_init(s);

#ifdef CONFIG_BOCHS_VBE

    /* XXX: use optimized standard vga accesses */

    vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);

    vga_mm_init(s, vram_base, ctrl_base, it_shift);

#ifdef CONFIG_BOCHS_VBE

    /* XXX: use optimized standard vga accesses */

    vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);

    vga_init(s);

    s->pci_dev = &d->dev;

    VGA_STATE_COMMON_BOCHS_VBE                                          \

    /* display refresh support */                                       \

    DisplayState *ds;                                                   \

    uint32_t font_offsets[2];                                           \

    int graphic_mode;                                                   \

    uint8_t shift_control;                                              \

#ifndef EMBED_STDVGA

    DisplayState *ds;

    int vram_size;

    ram_addr_t vram_offset;

#endif

    if (s->new_width != s->width || s->new_height != s->height) {

        s->width = s->new_width;

        s->height = s->new_height;

        s->invalidated = 1;

    }

}

    vmsvga_reset(s);

#ifdef EMBED_STDVGA

    vga_common_init((VGAState *) s, ds,

typedef struct BlockDriverState BlockDriverState;

typedef struct DisplayState DisplayState;

typedef struct TextConsole TextConsole;

typedef struct CharDriverState CharDriverState;

typedef struct VLANState VLANState;

typedef struct QEMUFile QEMUFile;

    kernel_cmdline = "";

    cyls = heads = secs = 0;

    translation = BIOS_ATA_TRANSLATION_AUTO;

    serial_devices[0] = "vc:80Cx24C";

    for(i = 1; i < MAX_SERIAL_PORTS; i++)