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/*
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* OMAP LCD controller.
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*
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* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "hw.h" |
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#include "console.h" |
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#include "omap.h" |
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struct omap_lcd_panel_s {
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target_phys_addr_t base; |
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qemu_irq irq; |
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DisplayState *state; |
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QEMUConsole *console; |
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ram_addr_t imif_base; |
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ram_addr_t emiff_base; |
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int plm;
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int tft;
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int mono;
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int enable;
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int width;
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int height;
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int interrupts;
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uint32_t timing[3];
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uint32_t subpanel; |
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uint32_t ctrl; |
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struct omap_dma_lcd_channel_s *dma;
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uint16_t palette[256];
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int palette_done;
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int frame_done;
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int invalidate;
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int sync_error;
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}; |
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static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) |
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{ |
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if (s->frame_done && (s->interrupts & 1)) { |
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qemu_irq_raise(s->irq); |
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return;
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} |
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if (s->palette_done && (s->interrupts & 2)) { |
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qemu_irq_raise(s->irq); |
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return;
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} |
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if (s->sync_error) {
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qemu_irq_raise(s->irq); |
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return;
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} |
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qemu_irq_lower(s->irq); |
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} |
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#include "pixel_ops.h" |
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typedef void draw_line_func( |
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uint8_t *d, const uint8_t *s, int width, const uint16_t *pal); |
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#define DEPTH 8 |
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#include "omap_lcd_template.h" |
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#define DEPTH 15 |
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#include "omap_lcd_template.h" |
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#define DEPTH 16 |
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#include "omap_lcd_template.h" |
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#define DEPTH 32 |
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#include "omap_lcd_template.h" |
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static draw_line_func *draw_line_table2[33] = { |
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[0 ... 32] = 0, |
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[8] = draw_line2_8,
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[15] = draw_line2_15,
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[16] = draw_line2_16,
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[32] = draw_line2_32,
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}, *draw_line_table4[33] = {
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[0 ... 32] = 0, |
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[8] = draw_line4_8,
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[15] = draw_line4_15,
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[16] = draw_line4_16,
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[32] = draw_line4_32,
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}, *draw_line_table8[33] = {
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[0 ... 32] = 0, |
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[8] = draw_line8_8,
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[15] = draw_line8_15,
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[16] = draw_line8_16,
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[32] = draw_line8_32,
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}, *draw_line_table12[33] = {
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[0 ... 32] = 0, |
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[8] = draw_line12_8,
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[15] = draw_line12_15,
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[16] = draw_line12_16,
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[32] = draw_line12_32,
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}, *draw_line_table16[33] = {
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[0 ... 32] = 0, |
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[8] = draw_line16_8,
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[15] = draw_line16_15,
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[16] = draw_line16_16,
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[32] = draw_line16_32,
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}; |
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static void omap_update_display(void *opaque) |
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{ |
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struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque; |
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draw_line_func *draw_line; |
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int size, dirty[2], minline, maxline, height; |
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int line, width, linesize, step, bpp, frame_offset;
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ram_addr_t frame_base, scanline, newline, x; |
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uint8_t *s, *d; |
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if (!omap_lcd || omap_lcd->plm == 1 || |
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!omap_lcd->enable || !omap_lcd->state->depth) |
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return;
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frame_offset = 0;
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if (omap_lcd->plm != 2) { |
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memcpy(omap_lcd->palette, phys_ram_base + |
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omap_lcd->dma->phys_framebuffer[ |
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omap_lcd->dma->current_frame], 0x200);
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switch (omap_lcd->palette[0] >> 12 & 7) { |
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case 3 ... 7: |
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frame_offset += 0x200;
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break;
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default:
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frame_offset += 0x20;
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} |
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} |
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/* Colour depth */
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switch ((omap_lcd->palette[0] >> 12) & 7) { |
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case 1: |
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draw_line = draw_line_table2[omap_lcd->state->depth]; |
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bpp = 2;
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break;
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case 2: |
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draw_line = draw_line_table4[omap_lcd->state->depth]; |
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bpp = 4;
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break;
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case 3: |
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draw_line = draw_line_table8[omap_lcd->state->depth]; |
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bpp = 8;
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break;
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case 4 ... 7: |
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if (!omap_lcd->tft)
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draw_line = draw_line_table12[omap_lcd->state->depth]; |
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else
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draw_line = draw_line_table16[omap_lcd->state->depth]; |
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bpp = 16;
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break;
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default:
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/* Unsupported at the moment. */
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return;
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} |
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/* Resolution */
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width = omap_lcd->width; |
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if (width != omap_lcd->state->width ||
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omap_lcd->height != omap_lcd->state->height) { |
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qemu_console_resize(omap_lcd->console, |
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omap_lcd->width, omap_lcd->height); |
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omap_lcd->invalidate = 1;
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} |
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if (omap_lcd->dma->current_frame == 0) |
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size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top; |
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else
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size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top; |
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if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) { |
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omap_lcd->sync_error = 1;
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omap_lcd_interrupts(omap_lcd); |
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omap_lcd->enable = 0;
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return;
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} |
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/* Content */
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frame_base = omap_lcd->dma->phys_framebuffer[ |
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omap_lcd->dma->current_frame] + frame_offset; |
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omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame;
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if (omap_lcd->dma->interrupts & 1) |
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qemu_irq_raise(omap_lcd->dma->irq); |
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if (omap_lcd->dma->dual)
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omap_lcd->dma->current_frame ^= 1;
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if (!omap_lcd->state->depth)
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return;
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line = 0;
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height = omap_lcd->height; |
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if (omap_lcd->subpanel & (1 << 31)) { |
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if (omap_lcd->subpanel & (1 << 29)) |
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line = (omap_lcd->subpanel >> 16) & 0x3ff; |
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else
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height = (omap_lcd->subpanel >> 16) & 0x3ff; |
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/* TODO: fill the rest of the panel with DPD */
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} |
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step = width * bpp >> 3;
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scanline = frame_base + step * line; |
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s = (uint8_t *) (phys_ram_base + scanline); |
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d = omap_lcd->state->data; |
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linesize = omap_lcd->state->linesize; |
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dirty[0] = dirty[1] = |
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cpu_physical_memory_get_dirty(scanline, VGA_DIRTY_FLAG); |
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minline = height; |
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maxline = line; |
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for (; line < height; line ++) {
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newline = scanline + step; |
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for (x = scanline + TARGET_PAGE_SIZE; x < newline;
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x += TARGET_PAGE_SIZE) { |
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dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
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dirty[0] |= dirty[1]; |
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} |
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if (dirty[0] || omap_lcd->invalidate) { |
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draw_line(d, s, width, omap_lcd->palette); |
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if (line < minline)
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minline = line; |
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maxline = line + 1;
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} |
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scanline = newline; |
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dirty[0] = dirty[1]; |
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s += step; |
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d += linesize; |
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} |
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if (maxline >= minline) {
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dpy_update(omap_lcd->state, 0, minline, width, maxline);
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cpu_physical_memory_reset_dirty(frame_base + step * minline, |
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frame_base + step * maxline, VGA_DIRTY_FLAG); |
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} |
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} |
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static int ppm_save(const char *filename, uint8_t *data, |
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int w, int h, int linesize) |
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{ |
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FILE *f; |
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uint8_t *d, *d1; |
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unsigned int v; |
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int y, x, bpp;
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f = fopen(filename, "wb");
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if (!f)
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return -1; |
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fprintf(f, "P6\n%d %d\n%d\n", w, h, 255); |
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d1 = data; |
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bpp = linesize / w; |
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for (y = 0; y < h; y ++) { |
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d = d1; |
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for (x = 0; x < w; x ++) { |
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v = *(uint32_t *) d; |
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switch (bpp) {
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case 2: |
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fputc((v >> 8) & 0xf8, f); |
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fputc((v >> 3) & 0xfc, f); |
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fputc((v << 3) & 0xf8, f); |
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break;
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case 3: |
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case 4: |
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default:
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fputc((v >> 16) & 0xff, f); |
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fputc((v >> 8) & 0xff, f); |
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fputc((v) & 0xff, f);
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break;
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} |
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d += bpp; |
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} |
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d1 += linesize; |
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} |
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fclose(f); |
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return 0; |
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} |
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static void omap_screen_dump(void *opaque, const char *filename) { |
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struct omap_lcd_panel_s *omap_lcd = opaque;
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omap_update_display(opaque); |
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if (omap_lcd && omap_lcd->state->data)
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ppm_save(filename, omap_lcd->state->data, |
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omap_lcd->width, omap_lcd->height, |
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omap_lcd->state->linesize); |
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} |
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static void omap_invalidate_display(void *opaque) { |
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struct omap_lcd_panel_s *omap_lcd = opaque;
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omap_lcd->invalidate = 1;
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} |
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static void omap_lcd_update(struct omap_lcd_panel_s *s) { |
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if (!s->enable) {
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s->dma->current_frame = -1;
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s->sync_error = 0;
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if (s->plm != 1) |
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s->frame_done = 1;
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omap_lcd_interrupts(s); |
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return;
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} |
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if (s->dma->current_frame == -1) { |
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s->frame_done = 0;
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s->palette_done = 0;
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s->dma->current_frame = 0;
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} |
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if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu,
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s->dma->src_f1_top) || |
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!s->dma->mpu->port[ |
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s->dma->src].addr_valid(s->dma->mpu, |
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s->dma->src_f1_bottom) || |
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(s->dma->dual && |
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(!s->dma->mpu->port[ |
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s->dma->src].addr_valid(s->dma->mpu, |
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s->dma->src_f2_top) || |
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!s->dma->mpu->port[ |
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s->dma->src].addr_valid(s->dma->mpu, |
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s->dma->src_f2_bottom)))) { |
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s->dma->condition |= 1 << 2; |
336 |
if (s->dma->interrupts & (1 << 1)) |
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qemu_irq_raise(s->dma->irq); |
338 |
s->enable = 0;
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return;
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} |
341 |
|
342 |
if (s->dma->src == imif) {
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/* Framebuffers are in SRAM */
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s->dma->phys_framebuffer[0] = s->imif_base +
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s->dma->src_f1_top - OMAP_IMIF_BASE; |
346 |
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s->dma->phys_framebuffer[1] = s->imif_base +
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s->dma->src_f2_top - OMAP_IMIF_BASE; |
349 |
} else {
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/* Framebuffers are in RAM */
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s->dma->phys_framebuffer[0] = s->emiff_base +
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s->dma->src_f1_top - OMAP_EMIFF_BASE; |
353 |
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s->dma->phys_framebuffer[1] = s->emiff_base +
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s->dma->src_f2_top - OMAP_EMIFF_BASE; |
356 |
} |
357 |
|
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if (s->plm != 2 && !s->palette_done) { |
359 |
memcpy(s->palette, phys_ram_base + |
360 |
s->dma->phys_framebuffer[s->dma->current_frame], 0x200);
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s->palette_done = 1;
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omap_lcd_interrupts(s); |
363 |
} |
364 |
} |
365 |
|
366 |
static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr) |
367 |
{ |
368 |
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; |
369 |
int offset = addr - s->base;
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370 |
|
371 |
switch (offset) {
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372 |
case 0x00: /* LCD_CONTROL */ |
373 |
return (s->tft << 23) | (s->plm << 20) | |
374 |
(s->tft << 7) | (s->interrupts << 3) | |
375 |
(s->mono << 1) | s->enable | s->ctrl | 0xfe000c34; |
376 |
|
377 |
case 0x04: /* LCD_TIMING0 */ |
378 |
return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f; |
379 |
|
380 |
case 0x08: /* LCD_TIMING1 */ |
381 |
return (s->timing[1] << 10) | (s->height - 1); |
382 |
|
383 |
case 0x0c: /* LCD_TIMING2 */ |
384 |
return s->timing[2] | 0xfc000000; |
385 |
|
386 |
case 0x10: /* LCD_STATUS */ |
387 |
return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done; |
388 |
|
389 |
case 0x14: /* LCD_SUBPANEL */ |
390 |
return s->subpanel;
|
391 |
|
392 |
default:
|
393 |
break;
|
394 |
} |
395 |
OMAP_BAD_REG(addr); |
396 |
return 0; |
397 |
} |
398 |
|
399 |
static void omap_lcdc_write(void *opaque, target_phys_addr_t addr, |
400 |
uint32_t value) |
401 |
{ |
402 |
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; |
403 |
int offset = addr - s->base;
|
404 |
|
405 |
switch (offset) {
|
406 |
case 0x00: /* LCD_CONTROL */ |
407 |
s->plm = (value >> 20) & 3; |
408 |
s->tft = (value >> 7) & 1; |
409 |
s->interrupts = (value >> 3) & 3; |
410 |
s->mono = (value >> 1) & 1; |
411 |
s->ctrl = value & 0x01cff300;
|
412 |
if (s->enable != (value & 1)) { |
413 |
s->enable = value & 1;
|
414 |
omap_lcd_update(s); |
415 |
} |
416 |
break;
|
417 |
|
418 |
case 0x04: /* LCD_TIMING0 */ |
419 |
s->timing[0] = value >> 10; |
420 |
s->width = (value & 0x3ff) + 1; |
421 |
break;
|
422 |
|
423 |
case 0x08: /* LCD_TIMING1 */ |
424 |
s->timing[1] = value >> 10; |
425 |
s->height = (value & 0x3ff) + 1; |
426 |
break;
|
427 |
|
428 |
case 0x0c: /* LCD_TIMING2 */ |
429 |
s->timing[2] = value;
|
430 |
break;
|
431 |
|
432 |
case 0x10: /* LCD_STATUS */ |
433 |
break;
|
434 |
|
435 |
case 0x14: /* LCD_SUBPANEL */ |
436 |
s->subpanel = value & 0xa1ffffff;
|
437 |
break;
|
438 |
|
439 |
default:
|
440 |
OMAP_BAD_REG(addr); |
441 |
} |
442 |
} |
443 |
|
444 |
static CPUReadMemoryFunc *omap_lcdc_readfn[] = {
|
445 |
omap_lcdc_read, |
446 |
omap_lcdc_read, |
447 |
omap_lcdc_read, |
448 |
}; |
449 |
|
450 |
static CPUWriteMemoryFunc *omap_lcdc_writefn[] = {
|
451 |
omap_lcdc_write, |
452 |
omap_lcdc_write, |
453 |
omap_lcdc_write, |
454 |
}; |
455 |
|
456 |
void omap_lcdc_reset(struct omap_lcd_panel_s *s) |
457 |
{ |
458 |
s->dma->current_frame = -1;
|
459 |
s->plm = 0;
|
460 |
s->tft = 0;
|
461 |
s->mono = 0;
|
462 |
s->enable = 0;
|
463 |
s->width = 0;
|
464 |
s->height = 0;
|
465 |
s->interrupts = 0;
|
466 |
s->timing[0] = 0; |
467 |
s->timing[1] = 0; |
468 |
s->timing[2] = 0; |
469 |
s->subpanel = 0;
|
470 |
s->palette_done = 0;
|
471 |
s->frame_done = 0;
|
472 |
s->sync_error = 0;
|
473 |
s->invalidate = 1;
|
474 |
s->subpanel = 0;
|
475 |
s->ctrl = 0;
|
476 |
} |
477 |
|
478 |
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
|
479 |
struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
|
480 |
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk) |
481 |
{ |
482 |
int iomemtype;
|
483 |
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) |
484 |
qemu_mallocz(sizeof(struct omap_lcd_panel_s)); |
485 |
|
486 |
s->irq = irq; |
487 |
s->dma = dma; |
488 |
s->base = base; |
489 |
s->state = ds; |
490 |
s->imif_base = imif_base; |
491 |
s->emiff_base = emiff_base; |
492 |
omap_lcdc_reset(s); |
493 |
|
494 |
iomemtype = cpu_register_io_memory(0, omap_lcdc_readfn,
|
495 |
omap_lcdc_writefn, s); |
496 |
cpu_register_physical_memory(s->base, 0x100, iomemtype);
|
497 |
|
498 |
s->console = graphic_console_init(ds, omap_update_display, |
499 |
omap_invalidate_display, |
500 |
omap_screen_dump, NULL, s);
|
501 |
|
502 |
return s;
|
503 |
} |