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/*
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* QEMU ETRAX Ethernet Controller.
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h> |
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#include "hw.h" |
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#include "net.h" |
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#include "etraxfs_dma.h" |
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#define D(x)
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/* Advertisement control register. */
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#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ |
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#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ |
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#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ |
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#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ |
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/*
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* The MDIO extensions in the TDK PHY model were reversed engineered from the
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* linux driver (PHYID and Diagnostics reg).
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* TODO: Add friendly names for the register nums.
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*/
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struct qemu_phy
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{ |
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uint32_t regs[32];
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unsigned int (*read)(struct qemu_phy *phy, unsigned int req); |
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void (*write)(struct qemu_phy *phy, unsigned int req, |
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unsigned int data); |
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}; |
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static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req) |
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{ |
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int regnum;
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unsigned r = 0; |
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regnum = req & 0x1f;
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switch (regnum) {
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case 1: |
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/* MR1. */
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/* Speeds and modes. */
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r |= (1 << 13) | (1 << 14); |
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r |= (1 << 11) | (1 << 12); |
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r |= (1 << 5); /* Autoneg complete. */ |
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r |= (1 << 3); /* Autoneg able. */ |
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r |= (1 << 2); /* Link. */ |
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break;
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case 5: |
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/* Link partner ability.
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We are kind; always agree with whatever best mode
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the guest advertises. */
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r = 1 << 14; /* Success. */ |
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/* Copy advertised modes. */
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r |= phy->regs[4] & (15 << 5); |
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/* Autoneg support. */
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r |= 1;
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break;
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case 18: |
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{ |
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/* Diagnostics reg. */
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int duplex = 0; |
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int speed_100 = 0; |
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/* Are we advertising 100 half or 100 duplex ? */
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speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
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speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
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/* Are we advertising 10 duplex or 100 duplex ? */
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duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
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duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
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r = (speed_100 << 10) | (duplex << 11); |
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} |
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break;
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default:
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r = phy->regs[regnum]; |
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break;
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} |
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D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum));
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return r;
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} |
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static void |
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tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data) |
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{ |
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int regnum;
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regnum = req & 0x1f;
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D(printf("%s reg[%d] = %x\n", __func__, regnum, data));
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switch (regnum) {
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default:
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phy->regs[regnum] = data; |
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break;
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} |
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} |
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static void |
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tdk_init(struct qemu_phy *phy)
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{ |
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phy->regs[0] = 0x3100; |
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/* PHY Id. */
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phy->regs[2] = 0x0300; |
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phy->regs[3] = 0xe400; |
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/* Autonegotiation advertisement reg. */
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phy->regs[4] = 0x01E1; |
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phy->read = tdk_read; |
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phy->write = tdk_write; |
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} |
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struct qemu_mdio
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{ |
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/* bus. */
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int mdc;
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int mdio;
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/* decoder. */
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enum {
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PREAMBLE, |
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SOF, |
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OPC, |
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ADDR, |
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REQ, |
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TURNAROUND, |
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DATA |
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} state; |
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unsigned int drive; |
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unsigned int cnt; |
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unsigned int addr; |
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unsigned int opc; |
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unsigned int req; |
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unsigned int data; |
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struct qemu_phy *devs[32]; |
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}; |
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static void |
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mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) |
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{ |
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bus->devs[addr & 0x1f] = phy;
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} |
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#ifdef USE_THIS_DEAD_CODE
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static void |
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mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) |
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{ |
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bus->devs[addr & 0x1f] = NULL; |
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} |
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#endif
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static void mdio_read_req(struct qemu_mdio *bus) |
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{ |
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struct qemu_phy *phy;
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phy = bus->devs[bus->addr]; |
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if (phy && phy->read)
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bus->data = phy->read(phy, bus->req); |
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else
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bus->data = 0xffff;
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} |
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static void mdio_write_req(struct qemu_mdio *bus) |
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{ |
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struct qemu_phy *phy;
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phy = bus->devs[bus->addr]; |
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if (phy && phy->write)
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phy->write(phy, bus->req, bus->data); |
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} |
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static void mdio_cycle(struct qemu_mdio *bus) |
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{ |
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bus->cnt++; |
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D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n",
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bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive)); |
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#if 0
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if (bus->mdc)
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printf("%d", bus->mdio);
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#endif
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switch (bus->state)
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{ |
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case PREAMBLE:
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if (bus->mdc) {
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if (bus->cnt >= (32 * 2) && !bus->mdio) { |
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bus->cnt = 0;
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bus->state = SOF; |
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bus->data = 0;
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} |
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} |
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break;
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case SOF:
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if (bus->mdc) {
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if (bus->mdio != 1) |
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printf("WARNING: no SOF\n");
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if (bus->cnt == 1*2) { |
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bus->cnt = 0;
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bus->opc = 0;
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bus->state = OPC; |
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} |
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} |
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break;
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case OPC:
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if (bus->mdc) {
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bus->opc <<= 1;
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bus->opc |= bus->mdio & 1;
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if (bus->cnt == 2*2) { |
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bus->cnt = 0;
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bus->addr = 0;
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bus->state = ADDR; |
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} |
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} |
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break;
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case ADDR:
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if (bus->mdc) {
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bus->addr <<= 1;
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bus->addr |= bus->mdio & 1;
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if (bus->cnt == 5*2) { |
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bus->cnt = 0;
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bus->req = 0;
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bus->state = REQ; |
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} |
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} |
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break;
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case REQ:
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if (bus->mdc) {
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bus->req <<= 1;
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bus->req |= bus->mdio & 1;
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if (bus->cnt == 5*2) { |
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bus->cnt = 0;
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bus->state = TURNAROUND; |
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} |
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} |
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break;
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case TURNAROUND:
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if (bus->mdc && bus->cnt == 2*2) { |
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bus->mdio = 0;
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bus->cnt = 0;
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if (bus->opc == 2) { |
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bus->drive = 1;
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mdio_read_req(bus); |
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bus->mdio = bus->data & 1;
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} |
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bus->state = DATA; |
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} |
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break;
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case DATA:
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if (!bus->mdc) {
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if (bus->drive) {
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bus->mdio = !!(bus->data & (1 << 15)); |
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bus->data <<= 1;
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} |
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} else {
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if (!bus->drive) {
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bus->data <<= 1;
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bus->data |= bus->mdio; |
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} |
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if (bus->cnt == 16 * 2) { |
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bus->cnt = 0;
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bus->state = PREAMBLE; |
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if (!bus->drive)
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mdio_write_req(bus); |
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bus->drive = 0;
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} |
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} |
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break;
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default:
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break;
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} |
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} |
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/* ETRAX-FS Ethernet MAC block starts here. */
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#define RW_MA0_LO 0x00 |
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#define RW_MA0_HI 0x04 |
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#define RW_MA1_LO 0x08 |
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#define RW_MA1_HI 0x0c |
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#define RW_GA_LO 0x10 |
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#define RW_GA_HI 0x14 |
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#define RW_GEN_CTRL 0x18 |
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#define RW_REC_CTRL 0x1c |
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#define RW_TR_CTRL 0x20 |
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#define RW_CLR_ERR 0x24 |
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#define RW_MGM_CTRL 0x28 |
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#define R_STAT 0x2c |
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#define FS_ETH_MAX_REGS 0x5c |
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struct fs_eth
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{ |
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CPUState *env; |
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qemu_irq *irq; |
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target_phys_addr_t base; |
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VLANClientState *vc; |
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int ethregs;
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/* Two addrs in the filter. */
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uint8_t macaddr[2][6]; |
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uint32_t regs[FS_ETH_MAX_REGS]; |
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unsigned char rx_fifo[1536]; |
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int rx_fifo_len;
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int rx_fifo_pos;
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struct etraxfs_dma_client *dma_out;
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struct etraxfs_dma_client *dma_in;
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/* MDIO bus. */
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struct qemu_mdio mdio_bus;
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unsigned int phyaddr; |
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int duplex_mismatch;
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/* PHY. */
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struct qemu_phy phy;
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}; |
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static void eth_validate_duplex(struct fs_eth *eth) |
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{ |
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struct qemu_phy *phy;
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unsigned int phy_duplex; |
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unsigned int mac_duplex; |
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int new_mm = 0; |
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phy = eth->mdio_bus.devs[eth->phyaddr]; |
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phy_duplex = !!(phy->read(phy, 18) & (1 << 11)); |
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mac_duplex = !!(eth->regs[RW_REC_CTRL] & 128);
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if (mac_duplex != phy_duplex)
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new_mm = 1;
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if (eth->regs[RW_GEN_CTRL] & 1) { |
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if (new_mm != eth->duplex_mismatch) {
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if (new_mm)
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printf("HW: WARNING "
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"ETH duplex mismatch MAC=%d PHY=%d\n",
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mac_duplex, phy_duplex); |
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else
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printf("HW: ETH duplex ok.\n");
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} |
364 |
eth->duplex_mismatch = new_mm; |
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} |
366 |
} |
367 |
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static uint32_t eth_rinvalid (void *opaque, target_phys_addr_t addr) |
369 |
{ |
370 |
struct fs_eth *eth = opaque;
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CPUState *env = eth->env; |
372 |
cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
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addr); |
374 |
return 0; |
375 |
} |
376 |
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static uint32_t eth_readl (void *opaque, target_phys_addr_t addr) |
378 |
{ |
379 |
struct fs_eth *eth = opaque;
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380 |
uint32_t r = 0;
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381 |
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/* Make addr relative to this instances base. */
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addr -= eth->base; |
384 |
switch (addr) {
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385 |
case R_STAT:
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386 |
/* Attach an MDIO/PHY abstraction. */
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387 |
r = eth->mdio_bus.mdio & 1;
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break;
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389 |
default:
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390 |
r = eth->regs[addr]; |
391 |
D(printf ("%s %x\n", __func__, addr));
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392 |
break;
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393 |
} |
394 |
return r;
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395 |
} |
396 |
|
397 |
static void |
398 |
eth_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
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399 |
{ |
400 |
struct fs_eth *eth = opaque;
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CPUState *env = eth->env; |
402 |
cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
403 |
addr); |
404 |
} |
405 |
|
406 |
static void eth_update_ma(struct fs_eth *eth, int ma) |
407 |
{ |
408 |
int reg;
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409 |
int i = 0; |
410 |
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411 |
ma &= 1;
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412 |
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413 |
reg = RW_MA0_LO; |
414 |
if (ma)
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415 |
reg = RW_MA1_LO; |
416 |
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417 |
eth->macaddr[ma][i++] = eth->regs[reg]; |
418 |
eth->macaddr[ma][i++] = eth->regs[reg] >> 8;
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419 |
eth->macaddr[ma][i++] = eth->regs[reg] >> 16;
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420 |
eth->macaddr[ma][i++] = eth->regs[reg] >> 24;
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421 |
eth->macaddr[ma][i++] = eth->regs[reg + 4];
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422 |
eth->macaddr[ma][i++] = eth->regs[reg + 4] >> 8; |
423 |
|
424 |
D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma,
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425 |
eth->macaddr[ma][0], eth->macaddr[ma][1], |
426 |
eth->macaddr[ma][2], eth->macaddr[ma][3], |
427 |
eth->macaddr[ma][4], eth->macaddr[ma][5])); |
428 |
} |
429 |
|
430 |
static void |
431 |
eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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432 |
{ |
433 |
struct fs_eth *eth = opaque;
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434 |
|
435 |
/* Make addr relative to this instances base. */
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436 |
addr -= eth->base; |
437 |
switch (addr)
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438 |
{ |
439 |
case RW_MA0_LO:
|
440 |
eth->regs[addr] = value; |
441 |
eth_update_ma(eth, 0);
|
442 |
break;
|
443 |
case RW_MA0_HI:
|
444 |
eth->regs[addr] = value; |
445 |
eth_update_ma(eth, 0);
|
446 |
break;
|
447 |
case RW_MA1_LO:
|
448 |
eth->regs[addr] = value; |
449 |
eth_update_ma(eth, 1);
|
450 |
break;
|
451 |
case RW_MA1_HI:
|
452 |
eth->regs[addr] = value; |
453 |
eth_update_ma(eth, 1);
|
454 |
break;
|
455 |
|
456 |
case RW_MGM_CTRL:
|
457 |
/* Attach an MDIO/PHY abstraction. */
|
458 |
if (value & 2) |
459 |
eth->mdio_bus.mdio = value & 1;
|
460 |
if (eth->mdio_bus.mdc != (value & 4)) { |
461 |
mdio_cycle(ð->mdio_bus); |
462 |
eth_validate_duplex(eth); |
463 |
} |
464 |
eth->mdio_bus.mdc = !!(value & 4);
|
465 |
break;
|
466 |
|
467 |
case RW_REC_CTRL:
|
468 |
eth->regs[addr] = value; |
469 |
eth_validate_duplex(eth); |
470 |
break;
|
471 |
|
472 |
default:
|
473 |
eth->regs[addr] = value; |
474 |
D(printf ("%s %x %x\n",
|
475 |
__func__, addr, value)); |
476 |
break;
|
477 |
} |
478 |
} |
479 |
|
480 |
/* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
|
481 |
filter dropping group addresses we have not joined. The filter has 64
|
482 |
bits (m). The has function is a simple nible xor of the group addr. */
|
483 |
static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa) |
484 |
{ |
485 |
unsigned int hsh; |
486 |
int m_individual = eth->regs[RW_REC_CTRL] & 4; |
487 |
int match;
|
488 |
|
489 |
/* First bit on the wire of a MAC address signals multicast or
|
490 |
physical address. */
|
491 |
if (!m_individual && !sa[0] & 1) |
492 |
return 0; |
493 |
|
494 |
/* Calculate the hash index for the GA registers. */
|
495 |
hsh = 0;
|
496 |
hsh ^= (*sa) & 0x3f;
|
497 |
hsh ^= ((*sa) >> 6) & 0x03; |
498 |
++sa; |
499 |
hsh ^= ((*sa) << 2) & 0x03c; |
500 |
hsh ^= ((*sa) >> 4) & 0xf; |
501 |
++sa; |
502 |
hsh ^= ((*sa) << 4) & 0x30; |
503 |
hsh ^= ((*sa) >> 2) & 0x3f; |
504 |
++sa; |
505 |
hsh ^= (*sa) & 0x3f;
|
506 |
hsh ^= ((*sa) >> 6) & 0x03; |
507 |
++sa; |
508 |
hsh ^= ((*sa) << 2) & 0x03c; |
509 |
hsh ^= ((*sa) >> 4) & 0xf; |
510 |
++sa; |
511 |
hsh ^= ((*sa) << 4) & 0x30; |
512 |
hsh ^= ((*sa) >> 2) & 0x3f; |
513 |
|
514 |
hsh &= 63;
|
515 |
if (hsh > 31) |
516 |
match = eth->regs[RW_GA_HI] & (1 << (hsh - 32)); |
517 |
else
|
518 |
match = eth->regs[RW_GA_LO] & (1 << hsh);
|
519 |
D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh,
|
520 |
eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match)); |
521 |
return match;
|
522 |
} |
523 |
|
524 |
static int eth_can_receive(void *opaque) |
525 |
{ |
526 |
struct fs_eth *eth = opaque;
|
527 |
int r;
|
528 |
|
529 |
r = eth->rx_fifo_len == 0;
|
530 |
if (!r) {
|
531 |
/* TODO: signal fifo overrun. */
|
532 |
printf("PACKET LOSS!\n");
|
533 |
} |
534 |
return r;
|
535 |
} |
536 |
|
537 |
static void eth_receive(void *opaque, const uint8_t *buf, int size) |
538 |
{ |
539 |
unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
540 |
struct fs_eth *eth = opaque;
|
541 |
int use_ma0 = eth->regs[RW_REC_CTRL] & 1; |
542 |
int use_ma1 = eth->regs[RW_REC_CTRL] & 2; |
543 |
int r_bcast = eth->regs[RW_REC_CTRL] & 8; |
544 |
|
545 |
if (size < 12) |
546 |
return;
|
547 |
|
548 |
D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
|
549 |
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], |
550 |
use_ma0, use_ma1, r_bcast)); |
551 |
|
552 |
/* Does the frame get through the address filters? */
|
553 |
if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6)) |
554 |
&& (!use_ma1 || memcmp(buf, eth->macaddr[1], 6)) |
555 |
&& (!r_bcast || memcmp(buf, sa_bcast, 6))
|
556 |
&& !eth_match_groupaddr(eth, buf)) |
557 |
return;
|
558 |
|
559 |
if (size > sizeof(eth->rx_fifo)) { |
560 |
/* TODO: signal error. */
|
561 |
} else if (eth->rx_fifo_len) { |
562 |
/* FIFO overrun. */
|
563 |
} else {
|
564 |
memcpy(eth->rx_fifo, buf, size); |
565 |
/* +4, HW passes the CRC to sw. */
|
566 |
eth->rx_fifo_len = size + 4;
|
567 |
eth->rx_fifo_pos = 0;
|
568 |
} |
569 |
} |
570 |
|
571 |
static void eth_rx_pull(void *opaque) |
572 |
{ |
573 |
struct fs_eth *eth = opaque;
|
574 |
int len;
|
575 |
if (eth->rx_fifo_len) {
|
576 |
D(printf("%s %d\n", __func__, eth->rx_fifo_len));
|
577 |
#if 0
|
578 |
{
|
579 |
int i;
|
580 |
for (i = 0; i < 32; i++)
|
581 |
printf("%2.2x", eth->rx_fifo[i]);
|
582 |
printf("\n");
|
583 |
}
|
584 |
#endif
|
585 |
len = etraxfs_dmac_input(eth->dma_in, |
586 |
eth->rx_fifo + eth->rx_fifo_pos, |
587 |
eth->rx_fifo_len, 1);
|
588 |
eth->rx_fifo_len -= len; |
589 |
eth->rx_fifo_pos += len; |
590 |
} |
591 |
} |
592 |
|
593 |
static int eth_tx_push(void *opaque, unsigned char *buf, int len) |
594 |
{ |
595 |
struct fs_eth *eth = opaque;
|
596 |
|
597 |
D(printf("%s buf=%p len=%d\n", __func__, buf, len));
|
598 |
qemu_send_packet(eth->vc, buf, len); |
599 |
return len;
|
600 |
} |
601 |
|
602 |
static CPUReadMemoryFunc *eth_read[] = {
|
603 |
ð_rinvalid, |
604 |
ð_rinvalid, |
605 |
ð_readl, |
606 |
}; |
607 |
|
608 |
static CPUWriteMemoryFunc *eth_write[] = {
|
609 |
ð_winvalid, |
610 |
ð_winvalid, |
611 |
ð_writel, |
612 |
}; |
613 |
|
614 |
void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
|
615 |
qemu_irq *irq, target_phys_addr_t base) |
616 |
{ |
617 |
struct etraxfs_dma_client *dma = NULL; |
618 |
struct fs_eth *eth = NULL; |
619 |
|
620 |
dma = qemu_mallocz(sizeof *dma * 2); |
621 |
if (!dma)
|
622 |
return NULL; |
623 |
|
624 |
eth = qemu_mallocz(sizeof *eth);
|
625 |
if (!eth)
|
626 |
goto err;
|
627 |
|
628 |
dma[0].client.push = eth_tx_push;
|
629 |
dma[0].client.opaque = eth;
|
630 |
dma[1].client.opaque = eth;
|
631 |
dma[1].client.pull = eth_rx_pull;
|
632 |
|
633 |
eth->env = env; |
634 |
eth->base = base; |
635 |
eth->irq = irq; |
636 |
eth->dma_out = dma; |
637 |
eth->dma_in = dma + 1;
|
638 |
|
639 |
/* Connect the phy. */
|
640 |
eth->phyaddr = 1;
|
641 |
tdk_init(ð->phy); |
642 |
mdio_attach(ð->mdio_bus, ð->phy, eth->phyaddr); |
643 |
|
644 |
eth->ethregs = cpu_register_io_memory(0, eth_read, eth_write, eth);
|
645 |
cpu_register_physical_memory (base, 0x5c, eth->ethregs);
|
646 |
|
647 |
eth->vc = qemu_new_vlan_client(nd->vlan, |
648 |
eth_receive, eth_can_receive, eth); |
649 |
|
650 |
return dma;
|
651 |
err:
|
652 |
qemu_free(eth); |
653 |
qemu_free(dma); |
654 |
return NULL; |
655 |
} |