Revision c66fb5bc hw/omap2.c
| b/hw/omap2.c | ||
|---|---|---|
| 485 | 485 |
omap_gp_timer_reset(s); |
| 486 | 486 |
omap_gp_timer_clk_setup(s); |
| 487 | 487 |
|
| 488 |
iomemtype = cpu_register_io_memory(0, omap_gp_timer_readfn,
|
|
| 488 |
iomemtype = l4_register_io_memory(0, omap_gp_timer_readfn,
|
|
| 489 | 489 |
omap_gp_timer_writefn, s); |
| 490 | 490 |
s->base = omap_l4_attach(ta, 0, iomemtype); |
| 491 | 491 |
|
| ... | ... | |
| 557 | 557 |
struct omap_synctimer_s *s = &mpu->synctimer; |
| 558 | 558 |
|
| 559 | 559 |
omap_synctimer_reset(s); |
| 560 |
s->base = omap_l4_attach(ta, 0, cpu_register_io_memory(0,
|
|
| 560 |
s->base = omap_l4_attach(ta, 0, l4_register_io_memory(0,
|
|
| 561 | 561 |
omap_synctimer_readfn, omap_synctimer_writefn, s)); |
| 562 | 562 |
} |
| 563 | 563 |
|
| ... | ... | |
| 960 | 960 |
s->wkup = wkup; |
| 961 | 961 |
s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32); |
| 962 | 962 |
|
| 963 |
iomemtype = cpu_register_io_memory(0, omap_gpio_module_readfn,
|
|
| 963 |
iomemtype = l4_register_io_memory(0, omap_gpio_module_readfn,
|
|
| 964 | 964 |
omap_gpio_module_writefn, s); |
| 965 | 965 |
s->base = omap_l4_attach(ta, region, iomemtype); |
| 966 | 966 |
} |
| ... | ... | |
| 1071 | 1071 |
|
| 1072 | 1072 |
omap_gpif_reset(s); |
| 1073 | 1073 |
|
| 1074 |
iomemtype = cpu_register_io_memory(0, omap_gpif_top_readfn,
|
|
| 1074 |
iomemtype = l4_register_io_memory(0, omap_gpif_top_readfn,
|
|
| 1075 | 1075 |
omap_gpif_top_writefn, s); |
| 1076 | 1076 |
s->topbase = omap_l4_attach(ta, 1, iomemtype); |
| 1077 | 1077 |
|
| ... | ... | |
| 1401 | 1401 |
} |
| 1402 | 1402 |
omap_mcspi_reset(s); |
| 1403 | 1403 |
|
| 1404 |
iomemtype = cpu_register_io_memory(0, omap_mcspi_readfn,
|
|
| 1404 |
iomemtype = l4_register_io_memory(0, omap_mcspi_readfn,
|
|
| 1405 | 1405 |
omap_mcspi_writefn, s); |
| 1406 | 1406 |
s->base = omap_l4_attach(ta, 0, iomemtype); |
| 1407 | 1407 |
|
| ... | ... | |
| 1602 | 1602 |
|
| 1603 | 1603 |
s->chr = chr ?: qemu_chr_open("null");
|
| 1604 | 1604 |
|
| 1605 |
iomemtype = cpu_register_io_memory(0, omap_sti_readfn,
|
|
| 1605 |
iomemtype = l4_register_io_memory(0, omap_sti_readfn,
|
|
| 1606 | 1606 |
omap_sti_writefn, s); |
| 1607 | 1607 |
s->base = omap_l4_attach(ta, 0, iomemtype); |
| 1608 | 1608 |
|
| ... | ... | |
| 1631 | 1631 |
struct omap_target_agent_s ta[0]; |
| 1632 | 1632 |
}; |
| 1633 | 1633 |
|
| 1634 |
#ifdef L4_MUX_HACK |
|
| 1635 |
static int omap_l4_io_entries; |
|
| 1636 |
static int omap_cpu_io_entry; |
|
| 1637 |
static struct omap_l4_entry {
|
|
| 1638 |
CPUReadMemoryFunc **mem_read; |
|
| 1639 |
CPUWriteMemoryFunc **mem_write; |
|
| 1640 |
void *opaque; |
|
| 1641 |
} *omap_l4_io_entry; |
|
| 1642 |
static CPUReadMemoryFunc **omap_l4_io_readb_fn; |
|
| 1643 |
static CPUReadMemoryFunc **omap_l4_io_readh_fn; |
|
| 1644 |
static CPUReadMemoryFunc **omap_l4_io_readw_fn; |
|
| 1645 |
static CPUWriteMemoryFunc **omap_l4_io_writeb_fn; |
|
| 1646 |
static CPUWriteMemoryFunc **omap_l4_io_writeh_fn; |
|
| 1647 |
static CPUWriteMemoryFunc **omap_l4_io_writew_fn; |
|
| 1648 |
static void **omap_l4_io_opaque; |
|
| 1649 |
|
|
| 1650 |
int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read, |
|
| 1651 |
CPUWriteMemoryFunc **mem_write, void *opaque) |
|
| 1652 |
{
|
|
| 1653 |
omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read; |
|
| 1654 |
omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write; |
|
| 1655 |
omap_l4_io_entry[omap_l4_io_entries].opaque = opaque; |
|
| 1656 |
|
|
| 1657 |
return omap_l4_io_entries ++; |
|
| 1658 |
} |
|
| 1659 |
|
|
| 1660 |
static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr) |
|
| 1661 |
{
|
|
| 1662 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
|
| 1663 |
|
|
| 1664 |
return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr); |
|
| 1665 |
} |
|
| 1666 |
|
|
| 1667 |
static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr) |
|
| 1668 |
{
|
|
| 1669 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
|
| 1670 |
|
|
| 1671 |
return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr); |
|
| 1672 |
} |
|
| 1673 |
|
|
| 1674 |
static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr) |
|
| 1675 |
{
|
|
| 1676 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
|
| 1677 |
|
|
| 1678 |
return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr); |
|
| 1679 |
} |
|
| 1680 |
|
|
| 1681 |
static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr, |
|
| 1682 |
uint32_t value) |
|
| 1683 |
{
|
|
| 1684 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
|
| 1685 |
|
|
| 1686 |
return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value); |
|
| 1687 |
} |
|
| 1688 |
|
|
| 1689 |
static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr, |
|
| 1690 |
uint32_t value) |
|
| 1691 |
{
|
|
| 1692 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
|
| 1693 |
|
|
| 1694 |
return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value); |
|
| 1695 |
} |
|
| 1696 |
|
|
| 1697 |
static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr, |
|
| 1698 |
uint32_t value) |
|
| 1699 |
{
|
|
| 1700 |
unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; |
|
| 1701 |
|
|
| 1702 |
return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value); |
|
| 1703 |
} |
|
| 1704 |
|
|
| 1705 |
static CPUReadMemoryFunc *omap_l4_io_readfn[] = {
|
|
| 1706 |
omap_l4_io_readb, |
|
| 1707 |
omap_l4_io_readh, |
|
| 1708 |
omap_l4_io_readw, |
|
| 1709 |
}; |
|
| 1710 |
|
|
| 1711 |
static CPUWriteMemoryFunc *omap_l4_io_writefn[] = {
|
|
| 1712 |
omap_l4_io_writeb, |
|
| 1713 |
omap_l4_io_writeh, |
|
| 1714 |
omap_l4_io_writew, |
|
| 1715 |
}; |
|
| 1716 |
#endif |
|
| 1717 |
|
|
| 1634 | 1718 |
struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num) |
| 1635 | 1719 |
{
|
| 1636 | 1720 |
struct omap_l4_s *bus = qemu_mallocz( |
| ... | ... | |
| 1639 | 1723 |
bus->ta_num = ta_num; |
| 1640 | 1724 |
bus->base = base; |
| 1641 | 1725 |
|
| 1726 |
#ifdef L4_MUX_HACK |
|
| 1727 |
omap_l4_io_entries = 1; |
|
| 1728 |
omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry)); |
|
| 1729 |
|
|
| 1730 |
omap_cpu_io_entry = |
|
| 1731 |
cpu_register_io_memory(0, omap_l4_io_readfn, |
|
| 1732 |
omap_l4_io_writefn, bus); |
|
| 1733 |
# define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE) |
|
| 1734 |
omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
|
| 1735 |
omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
|
| 1736 |
omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
|
| 1737 |
omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
|
| 1738 |
omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
|
| 1739 |
omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); |
|
| 1740 |
omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES); |
|
| 1741 |
#endif |
|
| 1742 |
|
|
| 1642 | 1743 |
return bus; |
| 1643 | 1744 |
} |
| 1644 | 1745 |
|
| ... | ... | |
| 1917 | 2018 |
ta->bus = bus; |
| 1918 | 2019 |
ta->start = &omap_l4_region[info->region]; |
| 1919 | 2020 |
ta->regions = info->regions; |
| 1920 |
ta->base = bus->base + ta->start[info->ta_region].offset; |
|
| 1921 | 2021 |
|
| 1922 | 2022 |
ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
|
| 1923 | 2023 |
ta->status = 0x00000000; |
| 1924 | 2024 |
ta->control = 0x00000200; /* XXX 01000200 for L4TAO */ |
| 1925 | 2025 |
|
| 1926 |
iomemtype = cpu_register_io_memory(0, omap_l4ta_readfn,
|
|
| 2026 |
iomemtype = l4_register_io_memory(0, omap_l4ta_readfn,
|
|
| 1927 | 2027 |
omap_l4ta_writefn, ta); |
| 1928 |
cpu_register_physical_memory(ta->base, 0x200, iomemtype);
|
|
| 2028 |
ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
|
|
| 1929 | 2029 |
|
| 1930 | 2030 |
return ta; |
| 1931 | 2031 |
} |
| ... | ... | |
| 1934 | 2034 |
int iotype) |
| 1935 | 2035 |
{
|
| 1936 | 2036 |
target_phys_addr_t base; |
| 1937 |
size_t size; |
|
| 2037 |
ssize_t size; |
|
| 2038 |
#ifdef L4_MUX_HACK |
|
| 2039 |
int i; |
|
| 2040 |
#endif |
|
| 1938 | 2041 |
|
| 1939 | 2042 |
if (region < 0 || region >= ta->regions) {
|
| 1940 | 2043 |
fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region); |
| ... | ... | |
| 1943 | 2046 |
|
| 1944 | 2047 |
base = ta->bus->base + ta->start[region].offset; |
| 1945 | 2048 |
size = ta->start[region].size; |
| 1946 |
if (iotype) |
|
| 2049 |
if (iotype) {
|
|
| 2050 |
#ifndef L4_MUX_HACK |
|
| 1947 | 2051 |
cpu_register_physical_memory(base, size, iotype); |
| 2052 |
#else |
|
| 2053 |
cpu_register_physical_memory(base, size, omap_cpu_io_entry); |
|
| 2054 |
i = (base - ta->bus->base) / TARGET_PAGE_SIZE; |
|
| 2055 |
for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
|
|
| 2056 |
omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0]; |
|
| 2057 |
omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1]; |
|
| 2058 |
omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2]; |
|
| 2059 |
omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0]; |
|
| 2060 |
omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1]; |
|
| 2061 |
omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2]; |
|
| 2062 |
omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque; |
|
| 2063 |
} |
|
| 2064 |
#endif |
|
| 2065 |
} |
|
| 1948 | 2066 |
|
| 1949 | 2067 |
return base; |
| 1950 | 2068 |
} |
| ... | ... | |
| 2036 | 2154 |
void omap_tap_init(struct omap_target_agent_s *ta, |
| 2037 | 2155 |
struct omap_mpu_state_s *mpu) |
| 2038 | 2156 |
{
|
| 2039 |
mpu->tap_base = omap_l4_attach(ta, 0, cpu_register_io_memory(0,
|
|
| 2157 |
mpu->tap_base = omap_l4_attach(ta, 0, l4_register_io_memory(0,
|
|
| 2040 | 2158 |
omap_tap_readfn, omap_tap_writefn, mpu)); |
| 2041 | 2159 |
} |
| 2042 | 2160 |
|
| ... | ... | |
| 2755 | 2873 |
s->mpu = mpu; |
| 2756 | 2874 |
omap_prcm_coldreset(s); |
| 2757 | 2875 |
|
| 2758 |
iomemtype = cpu_register_io_memory(0, omap_prcm_readfn,
|
|
| 2876 |
iomemtype = l4_register_io_memory(0, omap_prcm_readfn,
|
|
| 2759 | 2877 |
omap_prcm_writefn, s); |
| 2760 | 2878 |
s->base = omap_l4_attach(ta, 0, iomemtype); |
| 2761 | 2879 |
omap_l4_attach(ta, 1, iomemtype); |
| ... | ... | |
| 3079 | 3197 |
s->mpu = mpu; |
| 3080 | 3198 |
omap_sysctl_reset(s); |
| 3081 | 3199 |
|
| 3082 |
iomemtype = cpu_register_io_memory(0, omap_sysctl_readfn,
|
|
| 3200 |
iomemtype = l4_register_io_memory(0, omap_sysctl_readfn,
|
|
| 3083 | 3201 |
omap_sysctl_writefn, s); |
| 3084 | 3202 |
s->base = omap_l4_attach(ta, 0, iomemtype); |
| 3085 | 3203 |
omap_l4_attach(ta, 0, iomemtype); |
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