root / hw / omap_dss.c @ c66fb5bc
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/*
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* OMAP2 Display Subsystem.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "hw.h" |
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#include "console.h" |
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#include "omap.h" |
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struct omap_dss_s {
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target_phys_addr_t diss_base; |
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target_phys_addr_t disc_base; |
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target_phys_addr_t rfbi_base; |
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target_phys_addr_t venc_base; |
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target_phys_addr_t im3_base; |
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qemu_irq irq; |
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qemu_irq drq; |
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DisplayState *state; |
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int autoidle;
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int control;
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int enable;
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struct omap_dss_panel_s {
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int enable;
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int nx;
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int ny;
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int x;
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int y;
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} dig, lcd; |
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struct {
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uint32_t idlemode; |
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uint32_t irqst; |
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uint32_t irqen; |
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uint32_t control; |
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uint32_t config; |
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uint32_t capable; |
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uint32_t timing[3];
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int line;
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uint32_t bg[2];
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uint32_t trans[2];
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struct omap_dss_plane_s {
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int enable;
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int bpp;
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int posx;
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int posy;
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int nx;
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int ny;
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target_phys_addr_t addr[3];
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uint32_t attr; |
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uint32_t tresh; |
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int rowinc;
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int colinc;
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int wininc;
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} l[3];
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int invalidate;
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uint16_t palette[256];
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} dispc; |
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struct {
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int idlemode;
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uint32_t control; |
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int enable;
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int pixels;
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int busy;
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int skiplines;
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uint16_t rxbuf; |
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uint32_t config[2];
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uint32_t time[4];
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uint32_t data[6];
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uint16_t vsync; |
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uint16_t hsync; |
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struct rfbi_chip_s *chip[2]; |
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} rfbi; |
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}; |
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static void omap_dispc_interrupt_update(struct omap_dss_s *s) |
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{
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qemu_set_irq(s->irq, s->dispc.irqst & s->dispc.irqen); |
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} |
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static void omap_rfbi_reset(struct omap_dss_s *s) |
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{
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s->rfbi.idlemode = 0;
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s->rfbi.control = 2;
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s->rfbi.enable = 0;
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s->rfbi.pixels = 0;
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s->rfbi.skiplines = 0;
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s->rfbi.busy = 0;
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s->rfbi.config[0] = 0x00310000; |
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s->rfbi.config[1] = 0x00310000; |
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s->rfbi.time[0] = 0; |
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s->rfbi.time[1] = 0; |
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s->rfbi.time[2] = 0; |
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s->rfbi.time[3] = 0; |
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s->rfbi.data[0] = 0; |
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s->rfbi.data[1] = 0; |
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s->rfbi.data[2] = 0; |
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s->rfbi.data[3] = 0; |
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s->rfbi.data[4] = 0; |
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s->rfbi.data[5] = 0; |
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s->rfbi.vsync = 0;
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s->rfbi.hsync = 0;
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} |
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void omap_dss_reset(struct omap_dss_s *s) |
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{
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s->autoidle = 0;
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s->control = 0;
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s->enable = 0;
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s->dig.enable = 0;
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s->dig.nx = 1;
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s->dig.ny = 1;
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s->lcd.enable = 0;
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s->lcd.nx = 1;
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s->lcd.ny = 1;
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s->dispc.idlemode = 0;
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s->dispc.irqst = 0;
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s->dispc.irqen = 0;
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s->dispc.control = 0;
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s->dispc.config = 0;
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s->dispc.capable = 0x161;
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s->dispc.timing[0] = 0; |
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s->dispc.timing[1] = 0; |
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s->dispc.timing[2] = 0; |
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s->dispc.line = 0;
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s->dispc.bg[0] = 0; |
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s->dispc.bg[1] = 0; |
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s->dispc.trans[0] = 0; |
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s->dispc.trans[1] = 0; |
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s->dispc.l[0].enable = 0; |
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s->dispc.l[0].bpp = 0; |
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s->dispc.l[0].addr[0] = 0; |
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s->dispc.l[0].addr[1] = 0; |
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s->dispc.l[0].addr[2] = 0; |
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s->dispc.l[0].posx = 0; |
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s->dispc.l[0].posy = 0; |
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s->dispc.l[0].nx = 1; |
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s->dispc.l[0].ny = 1; |
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s->dispc.l[0].attr = 0; |
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s->dispc.l[0].tresh = 0; |
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s->dispc.l[0].rowinc = 1; |
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s->dispc.l[0].colinc = 1; |
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s->dispc.l[0].wininc = 0; |
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omap_rfbi_reset(s); |
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omap_dispc_interrupt_update(s); |
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} |
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static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->diss_base;
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switch (offset) {
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case 0x00: /* DSS_REVISIONNUMBER */ |
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return 0x20; |
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case 0x10: /* DSS_SYSCONFIG */ |
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return s->autoidle;
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case 0x14: /* DSS_SYSSTATUS */ |
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return 1; /* RESETDONE */ |
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case 0x40: /* DSS_CONTROL */ |
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return s->control;
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case 0x50: /* DSS_PSA_LCD_REG_1 */ |
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case 0x54: /* DSS_PSA_LCD_REG_2 */ |
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case 0x58: /* DSS_PSA_VIDEO_REG */ |
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/* TODO: fake some values when appropriate s->control bits are set */
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return 0; |
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case 0x5c: /* DSS_STATUS */ |
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return 1 + (s->control & 1); |
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default:
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break;
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} |
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OMAP_BAD_REG(addr); |
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return 0; |
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} |
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static void omap_diss_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->diss_base;
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switch (offset) {
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case 0x00: /* DSS_REVISIONNUMBER */ |
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case 0x14: /* DSS_SYSSTATUS */ |
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case 0x50: /* DSS_PSA_LCD_REG_1 */ |
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case 0x54: /* DSS_PSA_LCD_REG_2 */ |
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case 0x58: /* DSS_PSA_VIDEO_REG */ |
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case 0x5c: /* DSS_STATUS */ |
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OMAP_RO_REG(addr); |
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break;
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case 0x10: /* DSS_SYSCONFIG */ |
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if (value & 2) /* SOFTRESET */ |
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omap_dss_reset(s); |
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s->autoidle = value & 1;
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break;
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case 0x40: /* DSS_CONTROL */ |
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s->control = value & 0x3dd;
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break;
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default:
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OMAP_BAD_REG(addr); |
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} |
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} |
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static CPUReadMemoryFunc *omap_diss1_readfn[] = {
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omap_badwidth_read32, |
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omap_badwidth_read32, |
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omap_diss_read, |
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}; |
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static CPUWriteMemoryFunc *omap_diss1_writefn[] = {
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omap_badwidth_write32, |
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omap_badwidth_write32, |
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omap_diss_write, |
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}; |
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static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->disc_base;
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switch (offset) {
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case 0x000: /* DISPC_REVISION */ |
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return 0x20; |
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case 0x010: /* DISPC_SYSCONFIG */ |
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return s->dispc.idlemode;
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case 0x014: /* DISPC_SYSSTATUS */ |
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return 1; /* RESETDONE */ |
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case 0x018: /* DISPC_IRQSTATUS */ |
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return s->dispc.irqst;
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case 0x01c: /* DISPC_IRQENABLE */ |
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return s->dispc.irqen;
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case 0x040: /* DISPC_CONTROL */ |
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return s->dispc.control;
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case 0x044: /* DISPC_CONFIG */ |
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return s->dispc.config;
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case 0x048: /* DISPC_CAPABLE */ |
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return s->dispc.capable;
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case 0x04c: /* DISPC_DEFAULT_COLOR0 */ |
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return s->dispc.bg[0]; |
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case 0x050: /* DISPC_DEFAULT_COLOR1 */ |
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return s->dispc.bg[1]; |
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case 0x054: /* DISPC_TRANS_COLOR0 */ |
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return s->dispc.trans[0]; |
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case 0x058: /* DISPC_TRANS_COLOR1 */ |
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return s->dispc.trans[1]; |
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case 0x05c: /* DISPC_LINE_STATUS */ |
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return 0x7ff; |
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case 0x060: /* DISPC_LINE_NUMBER */ |
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return s->dispc.line;
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case 0x064: /* DISPC_TIMING_H */ |
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return s->dispc.timing[0]; |
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case 0x068: /* DISPC_TIMING_V */ |
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return s->dispc.timing[1]; |
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case 0x06c: /* DISPC_POL_FREQ */ |
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return s->dispc.timing[2]; |
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case 0x070: /* DISPC_DIVISOR */ |
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return s->dispc.timing[3]; |
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case 0x078: /* DISPC_SIZE_DIG */ |
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return ((s->dig.ny - 1) << 16) | (s->dig.nx - 1); |
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case 0x07c: /* DISPC_SIZE_LCD */ |
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return ((s->lcd.ny - 1) << 16) | (s->lcd.nx - 1); |
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case 0x080: /* DISPC_GFX_BA0 */ |
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return s->dispc.l[0].addr[0]; |
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case 0x084: /* DISPC_GFX_BA1 */ |
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return s->dispc.l[0].addr[1]; |
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case 0x088: /* DISPC_GFX_POSITION */ |
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return (s->dispc.l[0].posy << 16) | s->dispc.l[0].posx; |
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case 0x08c: /* DISPC_GFX_SIZE */ |
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return ((s->dispc.l[0].ny - 1) << 16) | (s->dispc.l[0].nx - 1); |
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case 0x0a0: /* DISPC_GFX_ATTRIBUTES */ |
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return s->dispc.l[0].attr; |
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case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */ |
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return s->dispc.l[0].tresh; |
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case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */ |
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return 256; |
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case 0x0ac: /* DISPC_GFX_ROW_INC */ |
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return s->dispc.l[0].rowinc; |
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case 0x0b0: /* DISPC_GFX_PIXEL_INC */ |
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return s->dispc.l[0].colinc; |
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case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */ |
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return s->dispc.l[0].wininc; |
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case 0x0b8: /* DISPC_GFX_TABLE_BA */ |
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return s->dispc.l[0].addr[2]; |
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|
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case 0x0bc: /* DISPC_VID1_BA0 */ |
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case 0x0c0: /* DISPC_VID1_BA1 */ |
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case 0x0c4: /* DISPC_VID1_POSITION */ |
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case 0x0c8: /* DISPC_VID1_SIZE */ |
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case 0x0cc: /* DISPC_VID1_ATTRIBUTES */ |
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case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */ |
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case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */ |
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case 0x0d8: /* DISPC_VID1_ROW_INC */ |
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case 0x0dc: /* DISPC_VID1_PIXEL_INC */ |
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case 0x0e0: /* DISPC_VID1_FIR */ |
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case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */ |
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case 0x0e8: /* DISPC_VID1_ACCU0 */ |
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case 0x0ec: /* DISPC_VID1_ACCU1 */ |
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case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */ |
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case 0x14c: /* DISPC_VID2_BA0 */ |
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case 0x150: /* DISPC_VID2_BA1 */ |
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case 0x154: /* DISPC_VID2_POSITION */ |
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case 0x158: /* DISPC_VID2_SIZE */ |
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case 0x15c: /* DISPC_VID2_ATTRIBUTES */ |
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case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */ |
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case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */ |
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case 0x168: /* DISPC_VID2_ROW_INC */ |
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case 0x16c: /* DISPC_VID2_PIXEL_INC */ |
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case 0x170: /* DISPC_VID2_FIR */ |
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case 0x174: /* DISPC_VID2_PICTURE_SIZE */ |
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case 0x178: /* DISPC_VID2_ACCU0 */ |
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case 0x17c: /* DISPC_VID2_ACCU1 */ |
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case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */ |
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case 0x1d4: /* DISPC_DATA_CYCLE1 */ |
| 363 |
case 0x1d8: /* DISPC_DATA_CYCLE2 */ |
| 364 |
case 0x1dc: /* DISPC_DATA_CYCLE3 */ |
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return 0; |
| 366 |
|
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default:
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break;
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} |
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OMAP_BAD_REG(addr); |
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return 0; |
| 372 |
} |
| 373 |
|
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static void omap_disc_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->disc_base;
|
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|
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switch (offset) {
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case 0x010: /* DISPC_SYSCONFIG */ |
| 382 |
if (value & 2) /* SOFTRESET */ |
| 383 |
omap_dss_reset(s); |
| 384 |
s->dispc.idlemode = value & 0x301b;
|
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break;
|
| 386 |
|
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case 0x018: /* DISPC_IRQSTATUS */ |
| 388 |
s->dispc.irqst &= ~value; |
| 389 |
omap_dispc_interrupt_update(s); |
| 390 |
break;
|
| 391 |
|
| 392 |
case 0x01c: /* DISPC_IRQENABLE */ |
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s->dispc.irqen = value & 0xffff;
|
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omap_dispc_interrupt_update(s); |
| 395 |
break;
|
| 396 |
|
| 397 |
case 0x040: /* DISPC_CONTROL */ |
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s->dispc.control = value & 0x07ff9fff;
|
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s->dig.enable = (value >> 1) & 1; |
| 400 |
s->lcd.enable = (value >> 0) & 1; |
| 401 |
if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */ |
| 402 |
if (~((s->dispc.l[1].attr | s->dispc.l[2].attr) & 1)) |
| 403 |
fprintf(stderr, "%s: Overlay Optimization when no overlay "
|
| 404 |
"region effectively exists leads to "
|
| 405 |
"unpredictable behaviour!\n", __FUNCTION__);
|
| 406 |
if (value & (1 << 6)) { /* GODIGITAL */ |
| 407 |
/* XXX: Shadowed fields are:
|
| 408 |
* s->dispc.config
|
| 409 |
* s->dispc.capable
|
| 410 |
* s->dispc.bg[0]
|
| 411 |
* s->dispc.bg[1]
|
| 412 |
* s->dispc.trans[0]
|
| 413 |
* s->dispc.trans[1]
|
| 414 |
* s->dispc.line
|
| 415 |
* s->dispc.timing[0]
|
| 416 |
* s->dispc.timing[1]
|
| 417 |
* s->dispc.timing[2]
|
| 418 |
* s->dispc.timing[3]
|
| 419 |
* s->lcd.nx
|
| 420 |
* s->lcd.ny
|
| 421 |
* s->dig.nx
|
| 422 |
* s->dig.ny
|
| 423 |
* s->dispc.l[0].addr[0]
|
| 424 |
* s->dispc.l[0].addr[1]
|
| 425 |
* s->dispc.l[0].addr[2]
|
| 426 |
* s->dispc.l[0].posx
|
| 427 |
* s->dispc.l[0].posy
|
| 428 |
* s->dispc.l[0].nx
|
| 429 |
* s->dispc.l[0].ny
|
| 430 |
* s->dispc.l[0].tresh
|
| 431 |
* s->dispc.l[0].rowinc
|
| 432 |
* s->dispc.l[0].colinc
|
| 433 |
* s->dispc.l[0].wininc
|
| 434 |
* All they need to be loaded here from their shadow registers.
|
| 435 |
*/
|
| 436 |
} |
| 437 |
if (value & (1 << 5)) { /* GOLCD */ |
| 438 |
/* XXX: Likewise for LCD here. */
|
| 439 |
} |
| 440 |
s->dispc.invalidate = 1;
|
| 441 |
break;
|
| 442 |
|
| 443 |
case 0x044: /* DISPC_CONFIG */ |
| 444 |
s->dispc.config = value & 0x3fff;
|
| 445 |
/* XXX:
|
| 446 |
* bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded
|
| 447 |
* bits 2:1 (LOADMODE) reset to 2 after set to 3 and palette loaded
|
| 448 |
*/
|
| 449 |
s->dispc.invalidate = 1;
|
| 450 |
break;
|
| 451 |
|
| 452 |
case 0x048: /* DISPC_CAPABLE */ |
| 453 |
s->dispc.capable = value & 0x3ff;
|
| 454 |
break;
|
| 455 |
|
| 456 |
case 0x04c: /* DISPC_DEFAULT_COLOR0 */ |
| 457 |
s->dispc.bg[0] = value & 0xffffff; |
| 458 |
s->dispc.invalidate = 1;
|
| 459 |
break;
|
| 460 |
case 0x050: /* DISPC_DEFAULT_COLOR1 */ |
| 461 |
s->dispc.bg[1] = value & 0xffffff; |
| 462 |
s->dispc.invalidate = 1;
|
| 463 |
break;
|
| 464 |
case 0x054: /* DISPC_TRANS_COLOR0 */ |
| 465 |
s->dispc.trans[0] = value & 0xffffff; |
| 466 |
s->dispc.invalidate = 1;
|
| 467 |
break;
|
| 468 |
case 0x058: /* DISPC_TRANS_COLOR1 */ |
| 469 |
s->dispc.trans[1] = value & 0xffffff; |
| 470 |
s->dispc.invalidate = 1;
|
| 471 |
break;
|
| 472 |
|
| 473 |
case 0x060: /* DISPC_LINE_NUMBER */ |
| 474 |
s->dispc.line = value & 0x7ff;
|
| 475 |
break;
|
| 476 |
|
| 477 |
case 0x064: /* DISPC_TIMING_H */ |
| 478 |
s->dispc.timing[0] = value & 0x0ff0ff3f; |
| 479 |
break;
|
| 480 |
case 0x068: /* DISPC_TIMING_V */ |
| 481 |
s->dispc.timing[1] = value & 0x0ff0ff3f; |
| 482 |
break;
|
| 483 |
case 0x06c: /* DISPC_POL_FREQ */ |
| 484 |
s->dispc.timing[2] = value & 0x0003ffff; |
| 485 |
break;
|
| 486 |
case 0x070: /* DISPC_DIVISOR */ |
| 487 |
s->dispc.timing[3] = value & 0x00ff00ff; |
| 488 |
break;
|
| 489 |
|
| 490 |
case 0x078: /* DISPC_SIZE_DIG */ |
| 491 |
s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */ |
| 492 |
s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */ |
| 493 |
s->dispc.invalidate = 1;
|
| 494 |
break;
|
| 495 |
case 0x07c: /* DISPC_SIZE_LCD */ |
| 496 |
s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */ |
| 497 |
s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */ |
| 498 |
s->dispc.invalidate = 1;
|
| 499 |
break;
|
| 500 |
case 0x080: /* DISPC_GFX_BA0 */ |
| 501 |
s->dispc.l[0].addr[0] = (target_phys_addr_t) value; |
| 502 |
s->dispc.invalidate = 1;
|
| 503 |
break;
|
| 504 |
case 0x084: /* DISPC_GFX_BA1 */ |
| 505 |
s->dispc.l[0].addr[1] = (target_phys_addr_t) value; |
| 506 |
s->dispc.invalidate = 1;
|
| 507 |
break;
|
| 508 |
case 0x088: /* DISPC_GFX_POSITION */ |
| 509 |
s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */ |
| 510 |
s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */ |
| 511 |
s->dispc.invalidate = 1;
|
| 512 |
break;
|
| 513 |
case 0x08c: /* DISPC_GFX_SIZE */ |
| 514 |
s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */ |
| 515 |
s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */ |
| 516 |
s->dispc.invalidate = 1;
|
| 517 |
break;
|
| 518 |
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */ |
| 519 |
s->dispc.l[0].attr = value & 0x7ff; |
| 520 |
if (value & (3 << 9)) |
| 521 |
fprintf(stderr, "%s: Big-endian pixel format not supported\n",
|
| 522 |
__FUNCTION__); |
| 523 |
s->dispc.l[0].enable = value & 1; |
| 524 |
s->dispc.l[0].bpp = (value >> 1) & 0xf; |
| 525 |
s->dispc.invalidate = 1;
|
| 526 |
break;
|
| 527 |
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */ |
| 528 |
s->dispc.l[0].tresh = value & 0x01ff01ff; |
| 529 |
break;
|
| 530 |
case 0x0ac: /* DISPC_GFX_ROW_INC */ |
| 531 |
s->dispc.l[0].rowinc = value;
|
| 532 |
s->dispc.invalidate = 1;
|
| 533 |
break;
|
| 534 |
case 0x0b0: /* DISPC_GFX_PIXEL_INC */ |
| 535 |
s->dispc.l[0].colinc = value;
|
| 536 |
s->dispc.invalidate = 1;
|
| 537 |
break;
|
| 538 |
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */ |
| 539 |
s->dispc.l[0].wininc = value;
|
| 540 |
break;
|
| 541 |
case 0x0b8: /* DISPC_GFX_TABLE_BA */ |
| 542 |
s->dispc.l[0].addr[2] = (target_phys_addr_t) value; |
| 543 |
s->dispc.invalidate = 1;
|
| 544 |
break;
|
| 545 |
|
| 546 |
case 0x0bc: /* DISPC_VID1_BA0 */ |
| 547 |
case 0x0c0: /* DISPC_VID1_BA1 */ |
| 548 |
case 0x0c4: /* DISPC_VID1_POSITION */ |
| 549 |
case 0x0c8: /* DISPC_VID1_SIZE */ |
| 550 |
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */ |
| 551 |
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */ |
| 552 |
case 0x0d8: /* DISPC_VID1_ROW_INC */ |
| 553 |
case 0x0dc: /* DISPC_VID1_PIXEL_INC */ |
| 554 |
case 0x0e0: /* DISPC_VID1_FIR */ |
| 555 |
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */ |
| 556 |
case 0x0e8: /* DISPC_VID1_ACCU0 */ |
| 557 |
case 0x0ec: /* DISPC_VID1_ACCU1 */ |
| 558 |
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */ |
| 559 |
case 0x14c: /* DISPC_VID2_BA0 */ |
| 560 |
case 0x150: /* DISPC_VID2_BA1 */ |
| 561 |
case 0x154: /* DISPC_VID2_POSITION */ |
| 562 |
case 0x158: /* DISPC_VID2_SIZE */ |
| 563 |
case 0x15c: /* DISPC_VID2_ATTRIBUTES */ |
| 564 |
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */ |
| 565 |
case 0x168: /* DISPC_VID2_ROW_INC */ |
| 566 |
case 0x16c: /* DISPC_VID2_PIXEL_INC */ |
| 567 |
case 0x170: /* DISPC_VID2_FIR */ |
| 568 |
case 0x174: /* DISPC_VID2_PICTURE_SIZE */ |
| 569 |
case 0x178: /* DISPC_VID2_ACCU0 */ |
| 570 |
case 0x17c: /* DISPC_VID2_ACCU1 */ |
| 571 |
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */ |
| 572 |
case 0x1d4: /* DISPC_DATA_CYCLE1 */ |
| 573 |
case 0x1d8: /* DISPC_DATA_CYCLE2 */ |
| 574 |
case 0x1dc: /* DISPC_DATA_CYCLE3 */ |
| 575 |
break;
|
| 576 |
|
| 577 |
default:
|
| 578 |
OMAP_BAD_REG(addr); |
| 579 |
} |
| 580 |
} |
| 581 |
|
| 582 |
static CPUReadMemoryFunc *omap_disc1_readfn[] = {
|
| 583 |
omap_badwidth_read32, |
| 584 |
omap_badwidth_read32, |
| 585 |
omap_disc_read, |
| 586 |
}; |
| 587 |
|
| 588 |
static CPUWriteMemoryFunc *omap_disc1_writefn[] = {
|
| 589 |
omap_badwidth_write32, |
| 590 |
omap_badwidth_write32, |
| 591 |
omap_disc_write, |
| 592 |
}; |
| 593 |
|
| 594 |
static void *omap_rfbi_get_buffer(struct omap_dss_s *s) |
| 595 |
{
|
| 596 |
target_phys_addr_t fb; |
| 597 |
uint32_t pd; |
| 598 |
|
| 599 |
/* TODO */
|
| 600 |
fb = s->dispc.l[0].addr[0]; |
| 601 |
|
| 602 |
pd = cpu_get_physical_page_desc(fb); |
| 603 |
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM)
|
| 604 |
/* TODO */
|
| 605 |
cpu_abort(cpu_single_env, "%s: framebuffer outside RAM!\n",
|
| 606 |
__FUNCTION__); |
| 607 |
else
|
| 608 |
return phys_ram_base +
|
| 609 |
(pd & TARGET_PAGE_MASK) + |
| 610 |
(fb & ~TARGET_PAGE_MASK); |
| 611 |
} |
| 612 |
|
| 613 |
static void omap_rfbi_transfer_stop(struct omap_dss_s *s) |
| 614 |
{
|
| 615 |
if (!s->rfbi.busy)
|
| 616 |
return;
|
| 617 |
|
| 618 |
/* TODO: in non-Bypass mode we probably need to just deassert the DRQ. */
|
| 619 |
|
| 620 |
s->rfbi.busy = 0;
|
| 621 |
} |
| 622 |
|
| 623 |
static void omap_rfbi_transfer_start(struct omap_dss_s *s) |
| 624 |
{
|
| 625 |
void *data;
|
| 626 |
size_t len; |
| 627 |
int pitch;
|
| 628 |
|
| 629 |
if (!s->rfbi.enable || s->rfbi.busy)
|
| 630 |
return;
|
| 631 |
|
| 632 |
if (s->rfbi.control & (1 << 1)) { /* BYPASS */ |
| 633 |
/* TODO: in non-Bypass mode we probably need to just assert the
|
| 634 |
* DRQ and wait for DMA to write the pixels. */
|
| 635 |
fprintf(stderr, "%s: Bypass mode unimplemented\n", __FUNCTION__);
|
| 636 |
return;
|
| 637 |
} |
| 638 |
|
| 639 |
if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */ |
| 640 |
return;
|
| 641 |
/* TODO: check that LCD output is enabled in DISPC. */
|
| 642 |
|
| 643 |
s->rfbi.busy = 1;
|
| 644 |
|
| 645 |
data = omap_rfbi_get_buffer(s); |
| 646 |
|
| 647 |
/* TODO bpp */
|
| 648 |
len = s->rfbi.pixels * 2;
|
| 649 |
s->rfbi.pixels = 0;
|
| 650 |
|
| 651 |
/* TODO: negative values */
|
| 652 |
pitch = s->dispc.l[0].nx + (s->dispc.l[0].rowinc - 1) / 2; |
| 653 |
|
| 654 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
| 655 |
s->rfbi.chip[0]->block(s->rfbi.chip[0]->opaque, 1, data, len, pitch); |
| 656 |
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
| 657 |
s->rfbi.chip[1]->block(s->rfbi.chip[1]->opaque, 1, data, len, pitch); |
| 658 |
|
| 659 |
omap_rfbi_transfer_stop(s); |
| 660 |
|
| 661 |
/* TODO */
|
| 662 |
s->dispc.irqst |= 1; /* FRAMEDONE */ |
| 663 |
omap_dispc_interrupt_update(s); |
| 664 |
} |
| 665 |
|
| 666 |
static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr) |
| 667 |
{
|
| 668 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| 669 |
int offset = addr - s->rfbi_base;
|
| 670 |
|
| 671 |
switch (offset) {
|
| 672 |
case 0x00: /* RFBI_REVISION */ |
| 673 |
return 0x10; |
| 674 |
|
| 675 |
case 0x10: /* RFBI_SYSCONFIG */ |
| 676 |
return s->rfbi.idlemode;
|
| 677 |
|
| 678 |
case 0x14: /* RFBI_SYSSTATUS */ |
| 679 |
return 1 | (s->rfbi.busy << 8); /* RESETDONE */ |
| 680 |
|
| 681 |
case 0x40: /* RFBI_CONTROL */ |
| 682 |
return s->rfbi.control;
|
| 683 |
|
| 684 |
case 0x44: /* RFBI_PIXELCNT */ |
| 685 |
return s->rfbi.pixels;
|
| 686 |
|
| 687 |
case 0x48: /* RFBI_LINE_NUMBER */ |
| 688 |
return s->rfbi.skiplines;
|
| 689 |
|
| 690 |
case 0x58: /* RFBI_READ */ |
| 691 |
case 0x5c: /* RFBI_STATUS */ |
| 692 |
return s->rfbi.rxbuf;
|
| 693 |
|
| 694 |
case 0x60: /* RFBI_CONFIG0 */ |
| 695 |
return s->rfbi.config[0]; |
| 696 |
case 0x64: /* RFBI_ONOFF_TIME0 */ |
| 697 |
return s->rfbi.time[0]; |
| 698 |
case 0x68: /* RFBI_CYCLE_TIME0 */ |
| 699 |
return s->rfbi.time[1]; |
| 700 |
case 0x6c: /* RFBI_DATA_CYCLE1_0 */ |
| 701 |
return s->rfbi.data[0]; |
| 702 |
case 0x70: /* RFBI_DATA_CYCLE2_0 */ |
| 703 |
return s->rfbi.data[1]; |
| 704 |
case 0x74: /* RFBI_DATA_CYCLE3_0 */ |
| 705 |
return s->rfbi.data[2]; |
| 706 |
|
| 707 |
case 0x78: /* RFBI_CONFIG1 */ |
| 708 |
return s->rfbi.config[1]; |
| 709 |
case 0x7c: /* RFBI_ONOFF_TIME1 */ |
| 710 |
return s->rfbi.time[2]; |
| 711 |
case 0x80: /* RFBI_CYCLE_TIME1 */ |
| 712 |
return s->rfbi.time[3]; |
| 713 |
case 0x84: /* RFBI_DATA_CYCLE1_1 */ |
| 714 |
return s->rfbi.data[3]; |
| 715 |
case 0x88: /* RFBI_DATA_CYCLE2_1 */ |
| 716 |
return s->rfbi.data[4]; |
| 717 |
case 0x8c: /* RFBI_DATA_CYCLE3_1 */ |
| 718 |
return s->rfbi.data[5]; |
| 719 |
|
| 720 |
case 0x90: /* RFBI_VSYNC_WIDTH */ |
| 721 |
return s->rfbi.vsync;
|
| 722 |
case 0x94: /* RFBI_HSYNC_WIDTH */ |
| 723 |
return s->rfbi.hsync;
|
| 724 |
} |
| 725 |
OMAP_BAD_REG(addr); |
| 726 |
return 0; |
| 727 |
} |
| 728 |
|
| 729 |
static void omap_rfbi_write(void *opaque, target_phys_addr_t addr, |
| 730 |
uint32_t value) |
| 731 |
{
|
| 732 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| 733 |
int offset = addr - s->rfbi_base;
|
| 734 |
|
| 735 |
switch (offset) {
|
| 736 |
case 0x10: /* RFBI_SYSCONFIG */ |
| 737 |
if (value & 2) /* SOFTRESET */ |
| 738 |
omap_rfbi_reset(s); |
| 739 |
s->rfbi.idlemode = value & 0x19;
|
| 740 |
break;
|
| 741 |
|
| 742 |
case 0x40: /* RFBI_CONTROL */ |
| 743 |
s->rfbi.control = value & 0xf;
|
| 744 |
s->rfbi.enable = value & 1;
|
| 745 |
if (value & (1 << 4) && /* ITE */ |
| 746 |
!(s->rfbi.config[0] & s->rfbi.config[1] & 0xc)) |
| 747 |
omap_rfbi_transfer_start(s); |
| 748 |
break;
|
| 749 |
|
| 750 |
case 0x44: /* RFBI_PIXELCNT */ |
| 751 |
s->rfbi.pixels = value; |
| 752 |
break;
|
| 753 |
|
| 754 |
case 0x48: /* RFBI_LINE_NUMBER */ |
| 755 |
s->rfbi.skiplines = value & 0x7ff;
|
| 756 |
break;
|
| 757 |
|
| 758 |
case 0x4c: /* RFBI_CMD */ |
| 759 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
| 760 |
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 0, value & 0xffff); |
| 761 |
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
| 762 |
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 0, value & 0xffff); |
| 763 |
break;
|
| 764 |
case 0x50: /* RFBI_PARAM */ |
| 765 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
| 766 |
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff); |
| 767 |
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
| 768 |
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff); |
| 769 |
break;
|
| 770 |
case 0x54: /* RFBI_DATA */ |
| 771 |
/* TODO: take into account the format set up in s->rfbi.config[?] and
|
| 772 |
* s->rfbi.data[?], but special-case the most usual scenario so that
|
| 773 |
* speed doesn't suffer. */
|
| 774 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) { |
| 775 |
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff); |
| 776 |
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value >> 16); |
| 777 |
} |
| 778 |
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) { |
| 779 |
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff); |
| 780 |
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value >> 16); |
| 781 |
} |
| 782 |
if (!-- s->rfbi.pixels)
|
| 783 |
omap_rfbi_transfer_stop(s); |
| 784 |
break;
|
| 785 |
case 0x58: /* RFBI_READ */ |
| 786 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
| 787 |
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1); |
| 788 |
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
| 789 |
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1); |
| 790 |
if (!-- s->rfbi.pixels)
|
| 791 |
omap_rfbi_transfer_stop(s); |
| 792 |
break;
|
| 793 |
|
| 794 |
case 0x5c: /* RFBI_STATUS */ |
| 795 |
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0]) |
| 796 |
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0); |
| 797 |
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
| 798 |
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0); |
| 799 |
if (!-- s->rfbi.pixels)
|
| 800 |
omap_rfbi_transfer_stop(s); |
| 801 |
break;
|
| 802 |
|
| 803 |
case 0x60: /* RFBI_CONFIG0 */ |
| 804 |
s->rfbi.config[0] = value & 0x003f1fff; |
| 805 |
break;
|
| 806 |
|
| 807 |
case 0x64: /* RFBI_ONOFF_TIME0 */ |
| 808 |
s->rfbi.time[0] = value & 0x3fffffff; |
| 809 |
break;
|
| 810 |
case 0x68: /* RFBI_CYCLE_TIME0 */ |
| 811 |
s->rfbi.time[1] = value & 0x0fffffff; |
| 812 |
break;
|
| 813 |
case 0x6c: /* RFBI_DATA_CYCLE1_0 */ |
| 814 |
s->rfbi.data[0] = value & 0x0f1f0f1f; |
| 815 |
break;
|
| 816 |
case 0x70: /* RFBI_DATA_CYCLE2_0 */ |
| 817 |
s->rfbi.data[1] = value & 0x0f1f0f1f; |
| 818 |
break;
|
| 819 |
case 0x74: /* RFBI_DATA_CYCLE3_0 */ |
| 820 |
s->rfbi.data[2] = value & 0x0f1f0f1f; |
| 821 |
break;
|
| 822 |
case 0x78: /* RFBI_CONFIG1 */ |
| 823 |
s->rfbi.config[1] = value & 0x003f1fff; |
| 824 |
break;
|
| 825 |
|
| 826 |
case 0x7c: /* RFBI_ONOFF_TIME1 */ |
| 827 |
s->rfbi.time[2] = value & 0x3fffffff; |
| 828 |
break;
|
| 829 |
case 0x80: /* RFBI_CYCLE_TIME1 */ |
| 830 |
s->rfbi.time[3] = value & 0x0fffffff; |
| 831 |
break;
|
| 832 |
case 0x84: /* RFBI_DATA_CYCLE1_1 */ |
| 833 |
s->rfbi.data[3] = value & 0x0f1f0f1f; |
| 834 |
break;
|
| 835 |
case 0x88: /* RFBI_DATA_CYCLE2_1 */ |
| 836 |
s->rfbi.data[4] = value & 0x0f1f0f1f; |
| 837 |
break;
|
| 838 |
case 0x8c: /* RFBI_DATA_CYCLE3_1 */ |
| 839 |
s->rfbi.data[5] = value & 0x0f1f0f1f; |
| 840 |
break;
|
| 841 |
|
| 842 |
case 0x90: /* RFBI_VSYNC_WIDTH */ |
| 843 |
s->rfbi.vsync = value & 0xffff;
|
| 844 |
break;
|
| 845 |
case 0x94: /* RFBI_HSYNC_WIDTH */ |
| 846 |
s->rfbi.hsync = value & 0xffff;
|
| 847 |
break;
|
| 848 |
|
| 849 |
default:
|
| 850 |
OMAP_BAD_REG(addr); |
| 851 |
} |
| 852 |
} |
| 853 |
|
| 854 |
static CPUReadMemoryFunc *omap_rfbi1_readfn[] = {
|
| 855 |
omap_badwidth_read32, |
| 856 |
omap_badwidth_read32, |
| 857 |
omap_rfbi_read, |
| 858 |
}; |
| 859 |
|
| 860 |
static CPUWriteMemoryFunc *omap_rfbi1_writefn[] = {
|
| 861 |
omap_badwidth_write32, |
| 862 |
omap_badwidth_write32, |
| 863 |
omap_rfbi_write, |
| 864 |
}; |
| 865 |
|
| 866 |
static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr) |
| 867 |
{
|
| 868 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| 869 |
int offset = addr - s->venc_base;
|
| 870 |
|
| 871 |
switch (offset) {
|
| 872 |
case 0x00: /* REV_ID */ |
| 873 |
case 0x04: /* STATUS */ |
| 874 |
case 0x08: /* F_CONTROL */ |
| 875 |
case 0x10: /* VIDOUT_CTRL */ |
| 876 |
case 0x14: /* SYNC_CTRL */ |
| 877 |
case 0x1c: /* LLEN */ |
| 878 |
case 0x20: /* FLENS */ |
| 879 |
case 0x24: /* HFLTR_CTRL */ |
| 880 |
case 0x28: /* CC_CARR_WSS_CARR */ |
| 881 |
case 0x2c: /* C_PHASE */ |
| 882 |
case 0x30: /* GAIN_U */ |
| 883 |
case 0x34: /* GAIN_V */ |
| 884 |
case 0x38: /* GAIN_Y */ |
| 885 |
case 0x3c: /* BLACK_LEVEL */ |
| 886 |
case 0x40: /* BLANK_LEVEL */ |
| 887 |
case 0x44: /* X_COLOR */ |
| 888 |
case 0x48: /* M_CONTROL */ |
| 889 |
case 0x4c: /* BSTAMP_WSS_DATA */ |
| 890 |
case 0x50: /* S_CARR */ |
| 891 |
case 0x54: /* LINE21 */ |
| 892 |
case 0x58: /* LN_SEL */ |
| 893 |
case 0x5c: /* L21__WC_CTL */ |
| 894 |
case 0x60: /* HTRIGGER_VTRIGGER */ |
| 895 |
case 0x64: /* SAVID__EAVID */ |
| 896 |
case 0x68: /* FLEN__FAL */ |
| 897 |
case 0x6c: /* LAL__PHASE_RESET */ |
| 898 |
case 0x70: /* HS_INT_START_STOP_X */ |
| 899 |
case 0x74: /* HS_EXT_START_STOP_X */ |
| 900 |
case 0x78: /* VS_INT_START_X */ |
| 901 |
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */ |
| 902 |
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */ |
| 903 |
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */ |
| 904 |
case 0x88: /* VS_EXT_STOP_Y */ |
| 905 |
case 0x90: /* AVID_START_STOP_X */ |
| 906 |
case 0x94: /* AVID_START_STOP_Y */ |
| 907 |
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */ |
| 908 |
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */ |
| 909 |
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */ |
| 910 |
case 0xb0: /* TVDETGP_INT_START_STOP_X */ |
| 911 |
case 0xb4: /* TVDETGP_INT_START_STOP_Y */ |
| 912 |
case 0xb8: /* GEN_CTRL */ |
| 913 |
case 0xc4: /* DAC_TST__DAC_A */ |
| 914 |
case 0xc8: /* DAC_B__DAC_C */ |
| 915 |
return 0; |
| 916 |
|
| 917 |
default:
|
| 918 |
break;
|
| 919 |
} |
| 920 |
OMAP_BAD_REG(addr); |
| 921 |
return 0; |
| 922 |
} |
| 923 |
|
| 924 |
static void omap_venc_write(void *opaque, target_phys_addr_t addr, |
| 925 |
uint32_t value) |
| 926 |
{
|
| 927 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| 928 |
int offset = addr - s->venc_base;
|
| 929 |
|
| 930 |
switch (offset) {
|
| 931 |
case 0x08: /* F_CONTROL */ |
| 932 |
case 0x10: /* VIDOUT_CTRL */ |
| 933 |
case 0x14: /* SYNC_CTRL */ |
| 934 |
case 0x1c: /* LLEN */ |
| 935 |
case 0x20: /* FLENS */ |
| 936 |
case 0x24: /* HFLTR_CTRL */ |
| 937 |
case 0x28: /* CC_CARR_WSS_CARR */ |
| 938 |
case 0x2c: /* C_PHASE */ |
| 939 |
case 0x30: /* GAIN_U */ |
| 940 |
case 0x34: /* GAIN_V */ |
| 941 |
case 0x38: /* GAIN_Y */ |
| 942 |
case 0x3c: /* BLACK_LEVEL */ |
| 943 |
case 0x40: /* BLANK_LEVEL */ |
| 944 |
case 0x44: /* X_COLOR */ |
| 945 |
case 0x48: /* M_CONTROL */ |
| 946 |
case 0x4c: /* BSTAMP_WSS_DATA */ |
| 947 |
case 0x50: /* S_CARR */ |
| 948 |
case 0x54: /* LINE21 */ |
| 949 |
case 0x58: /* LN_SEL */ |
| 950 |
case 0x5c: /* L21__WC_CTL */ |
| 951 |
case 0x60: /* HTRIGGER_VTRIGGER */ |
| 952 |
case 0x64: /* SAVID__EAVID */ |
| 953 |
case 0x68: /* FLEN__FAL */ |
| 954 |
case 0x6c: /* LAL__PHASE_RESET */ |
| 955 |
case 0x70: /* HS_INT_START_STOP_X */ |
| 956 |
case 0x74: /* HS_EXT_START_STOP_X */ |
| 957 |
case 0x78: /* VS_INT_START_X */ |
| 958 |
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */ |
| 959 |
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */ |
| 960 |
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */ |
| 961 |
case 0x88: /* VS_EXT_STOP_Y */ |
| 962 |
case 0x90: /* AVID_START_STOP_X */ |
| 963 |
case 0x94: /* AVID_START_STOP_Y */ |
| 964 |
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */ |
| 965 |
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */ |
| 966 |
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */ |
| 967 |
case 0xb0: /* TVDETGP_INT_START_STOP_X */ |
| 968 |
case 0xb4: /* TVDETGP_INT_START_STOP_Y */ |
| 969 |
case 0xb8: /* GEN_CTRL */ |
| 970 |
case 0xc4: /* DAC_TST__DAC_A */ |
| 971 |
case 0xc8: /* DAC_B__DAC_C */ |
| 972 |
break;
|
| 973 |
|
| 974 |
default:
|
| 975 |
OMAP_BAD_REG(addr); |
| 976 |
} |
| 977 |
} |
| 978 |
|
| 979 |
static CPUReadMemoryFunc *omap_venc1_readfn[] = {
|
| 980 |
omap_badwidth_read32, |
| 981 |
omap_badwidth_read32, |
| 982 |
omap_venc_read, |
| 983 |
}; |
| 984 |
|
| 985 |
static CPUWriteMemoryFunc *omap_venc1_writefn[] = {
|
| 986 |
omap_badwidth_write32, |
| 987 |
omap_badwidth_write32, |
| 988 |
omap_venc_write, |
| 989 |
}; |
| 990 |
|
| 991 |
static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr) |
| 992 |
{
|
| 993 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| 994 |
int offset = addr - s->im3_base;
|
| 995 |
|
| 996 |
switch (offset) {
|
| 997 |
case 0x0a8: /* SBIMERRLOGA */ |
| 998 |
case 0x0b0: /* SBIMERRLOG */ |
| 999 |
case 0x190: /* SBIMSTATE */ |
| 1000 |
case 0x198: /* SBTMSTATE_L */ |
| 1001 |
case 0x19c: /* SBTMSTATE_H */ |
| 1002 |
case 0x1a8: /* SBIMCONFIG_L */ |
| 1003 |
case 0x1ac: /* SBIMCONFIG_H */ |
| 1004 |
case 0x1f8: /* SBID_L */ |
| 1005 |
case 0x1fc: /* SBID_H */ |
| 1006 |
return 0; |
| 1007 |
|
| 1008 |
default:
|
| 1009 |
break;
|
| 1010 |
} |
| 1011 |
OMAP_BAD_REG(addr); |
| 1012 |
return 0; |
| 1013 |
} |
| 1014 |
|
| 1015 |
static void omap_im3_write(void *opaque, target_phys_addr_t addr, |
| 1016 |
uint32_t value) |
| 1017 |
{
|
| 1018 |
struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
| 1019 |
int offset = addr - s->im3_base;
|
| 1020 |
|
| 1021 |
switch (offset) {
|
| 1022 |
case 0x0b0: /* SBIMERRLOG */ |
| 1023 |
case 0x190: /* SBIMSTATE */ |
| 1024 |
case 0x198: /* SBTMSTATE_L */ |
| 1025 |
case 0x19c: /* SBTMSTATE_H */ |
| 1026 |
case 0x1a8: /* SBIMCONFIG_L */ |
| 1027 |
case 0x1ac: /* SBIMCONFIG_H */ |
| 1028 |
break;
|
| 1029 |
|
| 1030 |
default:
|
| 1031 |
OMAP_BAD_REG(addr); |
| 1032 |
} |
| 1033 |
} |
| 1034 |
|
| 1035 |
static CPUReadMemoryFunc *omap_im3_readfn[] = {
|
| 1036 |
omap_badwidth_read32, |
| 1037 |
omap_badwidth_read32, |
| 1038 |
omap_im3_read, |
| 1039 |
}; |
| 1040 |
|
| 1041 |
static CPUWriteMemoryFunc *omap_im3_writefn[] = {
|
| 1042 |
omap_badwidth_write32, |
| 1043 |
omap_badwidth_write32, |
| 1044 |
omap_im3_write, |
| 1045 |
}; |
| 1046 |
|
| 1047 |
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
| 1048 |
target_phys_addr_t l3_base, DisplayState *ds, |
| 1049 |
qemu_irq irq, qemu_irq drq, |
| 1050 |
omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
| 1051 |
omap_clk ick1, omap_clk ick2) |
| 1052 |
{
|
| 1053 |
int iomemtype[5]; |
| 1054 |
struct omap_dss_s *s = (struct omap_dss_s *) |
| 1055 |
qemu_mallocz(sizeof(struct omap_dss_s)); |
| 1056 |
|
| 1057 |
s->irq = irq; |
| 1058 |
s->drq = drq; |
| 1059 |
s->state = ds; |
| 1060 |
omap_dss_reset(s); |
| 1061 |
|
| 1062 |
iomemtype[0] = l4_register_io_memory(0, omap_diss1_readfn, |
| 1063 |
omap_diss1_writefn, s); |
| 1064 |
iomemtype[1] = l4_register_io_memory(0, omap_disc1_readfn, |
| 1065 |
omap_disc1_writefn, s); |
| 1066 |
iomemtype[2] = l4_register_io_memory(0, omap_rfbi1_readfn, |
| 1067 |
omap_rfbi1_writefn, s); |
| 1068 |
iomemtype[3] = l4_register_io_memory(0, omap_venc1_readfn, |
| 1069 |
omap_venc1_writefn, s); |
| 1070 |
iomemtype[4] = cpu_register_io_memory(0, omap_im3_readfn, |
| 1071 |
omap_im3_writefn, s); |
| 1072 |
s->diss_base = omap_l4_attach(ta, 0, iomemtype[0]); |
| 1073 |
s->disc_base = omap_l4_attach(ta, 1, iomemtype[1]); |
| 1074 |
s->rfbi_base = omap_l4_attach(ta, 2, iomemtype[2]); |
| 1075 |
s->venc_base = omap_l4_attach(ta, 3, iomemtype[3]); |
| 1076 |
s->im3_base = l3_base; |
| 1077 |
cpu_register_physical_memory(s->im3_base, 0x1000, iomemtype[4]); |
| 1078 |
|
| 1079 |
#if 0
|
| 1080 |
if (ds)
|
| 1081 |
graphic_console_init(ds, omap_update_display,
|
| 1082 |
omap_invalidate_display, omap_screen_dump, s);
|
| 1083 |
#endif
|
| 1084 |
|
| 1085 |
return s;
|
| 1086 |
} |
| 1087 |
|
| 1088 |
void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip) |
| 1089 |
{
|
| 1090 |
if (cs < 0 || cs > 1) |
| 1091 |
cpu_abort(cpu_single_env, "%s: wrong CS %i\n", __FUNCTION__, cs);
|
| 1092 |
s->rfbi.chip[cs] = chip; |
| 1093 |
} |