Revision c6dc6f63 target-i386/helper.c
b/target-i386/helper.c | ||
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#include "kvm.h" |
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|
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//#define DEBUG_MMU |
32 |
#include "qemu-option.h" |
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#include "qemu-config.h" |
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|
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/* feature flags taken from "Intel Processor Identification and the CPUID |
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* Instruction" and AMD's "CPUID Specification". In cases of disagreement |
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* between feature naming conventions, aliases may be added. |
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*/ |
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static const char *feature_name[] = { |
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"fpu", "vme", "de", "pse", |
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"tsc", "msr", "pae", "mce", |
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"cx8", "apic", NULL, "sep", |
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"mtrr", "pge", "mca", "cmov", |
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"pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, |
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NULL, "ds" /* Intel dts */, "acpi", "mmx", |
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"fxsr", "sse", "sse2", "ss", |
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"ht" /* Intel htt */, "tm", "ia64", "pbe", |
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}; |
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static const char *ext_feature_name[] = { |
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"pni|sse3" /* Intel,AMD sse3 */, NULL, NULL, "monitor", |
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"ds_cpl", "vmx", NULL /* Linux smx */, "est", |
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"tm2", "ssse3", "cid", NULL, |
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NULL, "cx16", "xtpr", NULL, |
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NULL, NULL, "dca", "sse4.1|sse4_1", |
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"sse4.2|sse4_2", "x2apic", NULL, "popcnt", |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, "hypervisor", |
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}; |
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static const char *ext2_feature_name[] = { |
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"fpu", "vme", "de", "pse", |
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"tsc", "msr", "pae", "mce", |
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"cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall", |
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"mtrr", "pge", "mca", "cmov", |
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"pat", "pse36", NULL, NULL /* Linux mp */, |
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"nx" /* Intel xd */, NULL, "mmxext", "mmx", |
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"fxsr", "fxsr_opt" /* AMD ffxsr */, "pdpe1gb" /* AMD Page1GB */, "rdtscp", |
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NULL, "lm" /* Intel 64 */, "3dnowext", "3dnow", |
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}; |
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static const char *ext3_feature_name[] = { |
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"lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, |
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"cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse", |
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"3dnowprefetch", "osvw", NULL /* Linux ibs */, NULL, |
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"skinit", "wdt", NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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}; |
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|
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static const char *kvm_feature_name[] = { |
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"kvmclock", "kvm_nopiodelay", "kvm_mmu", NULL, NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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}; |
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|
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/* collects per-function cpuid data |
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*/ |
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typedef struct model_features_t { |
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uint32_t *guest_feat; |
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uint32_t *host_feat; |
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uint32_t check_feat; |
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const char **flag_names; |
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uint32_t cpuid; |
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} model_features_t; |
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|
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int check_cpuid = 0; |
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int enforce_cpuid = 0; |
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|
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static void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, |
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uint32_t *ebx, uint32_t *ecx, uint32_t *edx); |
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|
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#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c))) |
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|
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/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of |
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* a substring. ex if !NULL points to the first char after a substring, |
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* otherwise the string is assumed to sized by a terminating nul. |
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* Return lexical ordering of *s1:*s2. |
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*/ |
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static int sstrcmp(const char *s1, const char *e1, const char *s2, |
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const char *e2) |
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{ |
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for (;;) { |
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if (!*s1 || !*s2 || *s1 != *s2) |
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return (*s1 - *s2); |
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++s1, ++s2; |
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if (s1 == e1 && s2 == e2) |
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return (0); |
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else if (s1 == e1) |
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return (*s2); |
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else if (s2 == e2) |
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return (*s1); |
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} |
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} |
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|
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/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple |
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* '|' delimited (possibly empty) strings in which case search for a match |
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* within the alternatives proceeds left to right. Return 0 for success, |
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* non-zero otherwise. |
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*/ |
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static int altcmp(const char *s, const char *e, const char *altstr) |
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{ |
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const char *p, *q; |
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|
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for (q = p = altstr; ; ) { |
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while (*p && *p != '|') |
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++p; |
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if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p))) |
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return (0); |
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if (!*p) |
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return (1); |
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else |
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q = ++p; |
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} |
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} |
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|
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/* search featureset for flag *[s..e), if found set corresponding bit in |
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* *pval and return success, otherwise return zero |
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*/ |
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static int lookup_feature(uint32_t *pval, const char *s, const char *e, |
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const char **featureset) |
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{ |
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uint32_t mask; |
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const char **ppc; |
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|
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for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) |
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if (*ppc && !altcmp(s, e, *ppc)) { |
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*pval |= mask; |
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break; |
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} |
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return (mask ? 1 : 0); |
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} |
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|
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static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features, |
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uint32_t *ext_features, |
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uint32_t *ext2_features, |
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uint32_t *ext3_features, |
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uint32_t *kvm_features) |
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{ |
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if (!lookup_feature(features, flagname, NULL, feature_name) && |
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!lookup_feature(ext_features, flagname, NULL, ext_feature_name) && |
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!lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) && |
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!lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) && |
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!lookup_feature(kvm_features, flagname, NULL, kvm_feature_name)) |
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fprintf(stderr, "CPU feature %s not found\n", flagname); |
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} |
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|
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typedef struct x86_def_t { |
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struct x86_def_t *next; |
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const char *name; |
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uint32_t level; |
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uint32_t vendor1, vendor2, vendor3; |
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int family; |
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int model; |
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int stepping; |
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uint32_t features, ext_features, ext2_features, ext3_features, kvm_features; |
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uint32_t xlevel; |
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char model_id[48]; |
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int vendor_override; |
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uint32_t flags; |
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} x86_def_t; |
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|
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#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) |
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#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ |
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) |
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#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ |
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CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ |
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CPUID_PSE36 | CPUID_FXSR) |
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#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) |
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#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ |
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ |
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CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ |
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CPUID_PAE | CPUID_SEP | CPUID_APIC) |
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|
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/* maintains list of cpu model definitions |
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*/ |
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static x86_def_t *x86_defs = {NULL}; |
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|
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/* built-in cpu model definitions (deprecated) |
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*/ |
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static x86_def_t builtin_x86_defs[] = { |
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#ifdef TARGET_X86_64 |
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{ |
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.name = "qemu64", |
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.level = 4, |
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.vendor1 = CPUID_VENDOR_AMD_1, |
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.vendor2 = CPUID_VENDOR_AMD_2, |
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.vendor3 = CPUID_VENDOR_AMD_3, |
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.family = 6, |
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.model = 2, |
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.stepping = 3, |
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.features = PPRO_FEATURES | |
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/* these features are needed for Win64 and aren't fully implemented */ |
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CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
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/* this feature is needed for Solaris and isn't fully implemented */ |
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CPUID_PSE36, |
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, |
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.ext2_features = (PPRO_FEATURES & 0x0183F3FF) | |
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
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.ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | |
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CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, |
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.xlevel = 0x8000000A, |
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.model_id = "QEMU Virtual CPU version " QEMU_VERSION, |
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}, |
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{ |
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.name = "phenom", |
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.level = 5, |
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.vendor1 = CPUID_VENDOR_AMD_1, |
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.vendor2 = CPUID_VENDOR_AMD_2, |
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.vendor3 = CPUID_VENDOR_AMD_3, |
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.family = 16, |
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.model = 2, |
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.stepping = 3, |
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/* Missing: CPUID_VME, CPUID_HT */ |
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.features = PPRO_FEATURES | |
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CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
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CPUID_PSE36, |
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | |
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CPUID_EXT_POPCNT, |
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/* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ |
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.ext2_features = (PPRO_FEATURES & 0x0183F3FF) | |
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | |
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253 |
CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | |
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254 |
CPUID_EXT2_FFXSR, |
|
255 |
/* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, |
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256 |
CPUID_EXT3_CR8LEG, |
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257 |
CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, |
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CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ |
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259 |
.ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | |
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CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, |
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.xlevel = 0x8000001A, |
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262 |
.model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" |
|
263 |
}, |
|
264 |
{ |
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265 |
.name = "core2duo", |
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266 |
.level = 10, |
|
267 |
.family = 6, |
|
268 |
.model = 15, |
|
269 |
.stepping = 11, |
|
270 |
/* The original CPU also implements these features: |
|
271 |
CPUID_VME, CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT, |
|
272 |
CPUID_TM, CPUID_PBE */ |
|
273 |
.features = PPRO_FEATURES | |
|
274 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
|
275 |
CPUID_PSE36, |
|
276 |
/* The original CPU also implements these ext features: |
|
277 |
CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST, |
|
278 |
CPUID_EXT_TM2, CPUID_EXT_CX16, CPUID_EXT_XTPR, CPUID_EXT_PDCM */ |
|
279 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3, |
|
280 |
.ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
|
281 |
.ext3_features = CPUID_EXT3_LAHF_LM, |
|
282 |
.xlevel = 0x80000008, |
|
283 |
.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", |
|
284 |
}, |
|
285 |
{ |
|
286 |
.name = "kvm64", |
|
287 |
.level = 5, |
|
288 |
.vendor1 = CPUID_VENDOR_INTEL_1, |
|
289 |
.vendor2 = CPUID_VENDOR_INTEL_2, |
|
290 |
.vendor3 = CPUID_VENDOR_INTEL_3, |
|
291 |
.family = 15, |
|
292 |
.model = 6, |
|
293 |
.stepping = 1, |
|
294 |
/* Missing: CPUID_VME, CPUID_HT */ |
|
295 |
.features = PPRO_FEATURES | |
|
296 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
|
297 |
CPUID_PSE36, |
|
298 |
/* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ |
|
299 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16, |
|
300 |
/* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ |
|
301 |
.ext2_features = (PPRO_FEATURES & 0x0183F3FF) | |
|
302 |
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
|
303 |
/* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, |
|
304 |
CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, |
|
305 |
CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, |
|
306 |
CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ |
|
307 |
.ext3_features = 0, |
|
308 |
.xlevel = 0x80000008, |
|
309 |
.model_id = "Common KVM processor" |
|
310 |
}, |
|
311 |
#endif |
|
312 |
{ |
|
313 |
.name = "qemu32", |
|
314 |
.level = 4, |
|
315 |
.family = 6, |
|
316 |
.model = 3, |
|
317 |
.stepping = 3, |
|
318 |
.features = PPRO_FEATURES, |
|
319 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT, |
|
320 |
.xlevel = 0, |
|
321 |
.model_id = "QEMU Virtual CPU version " QEMU_VERSION, |
|
322 |
}, |
|
323 |
{ |
|
324 |
.name = "coreduo", |
|
325 |
.level = 10, |
|
326 |
.family = 6, |
|
327 |
.model = 14, |
|
328 |
.stepping = 8, |
|
329 |
/* The original CPU also implements these features: |
|
330 |
CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT, |
|
331 |
CPUID_TM, CPUID_PBE */ |
|
332 |
.features = PPRO_FEATURES | CPUID_VME | |
|
333 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA, |
|
334 |
/* The original CPU also implements these ext features: |
|
335 |
CPUID_EXT_VMX, CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_XTPR, |
|
336 |
CPUID_EXT_PDCM */ |
|
337 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, |
|
338 |
.ext2_features = CPUID_EXT2_NX, |
|
339 |
.xlevel = 0x80000008, |
|
340 |
.model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", |
|
341 |
}, |
|
342 |
{ |
|
343 |
.name = "486", |
|
344 |
.level = 0, |
|
345 |
.family = 4, |
|
346 |
.model = 0, |
|
347 |
.stepping = 0, |
|
348 |
.features = I486_FEATURES, |
|
349 |
.xlevel = 0, |
|
350 |
}, |
|
351 |
{ |
|
352 |
.name = "pentium", |
|
353 |
.level = 1, |
|
354 |
.family = 5, |
|
355 |
.model = 4, |
|
356 |
.stepping = 3, |
|
357 |
.features = PENTIUM_FEATURES, |
|
358 |
.xlevel = 0, |
|
359 |
}, |
|
360 |
{ |
|
361 |
.name = "pentium2", |
|
362 |
.level = 2, |
|
363 |
.family = 6, |
|
364 |
.model = 5, |
|
365 |
.stepping = 2, |
|
366 |
.features = PENTIUM2_FEATURES, |
|
367 |
.xlevel = 0, |
|
368 |
}, |
|
369 |
{ |
|
370 |
.name = "pentium3", |
|
371 |
.level = 2, |
|
372 |
.family = 6, |
|
373 |
.model = 7, |
|
374 |
.stepping = 3, |
|
375 |
.features = PENTIUM3_FEATURES, |
|
376 |
.xlevel = 0, |
|
377 |
}, |
|
378 |
{ |
|
379 |
.name = "athlon", |
|
380 |
.level = 2, |
|
381 |
.vendor1 = CPUID_VENDOR_AMD_1, |
|
382 |
.vendor2 = CPUID_VENDOR_AMD_2, |
|
383 |
.vendor3 = CPUID_VENDOR_AMD_3, |
|
384 |
.family = 6, |
|
385 |
.model = 2, |
|
386 |
.stepping = 3, |
|
387 |
.features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA, |
|
388 |
.ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, |
|
389 |
.xlevel = 0x80000008, |
|
390 |
/* XXX: put another string ? */ |
|
391 |
.model_id = "QEMU Virtual CPU version " QEMU_VERSION, |
|
392 |
}, |
|
393 |
{ |
|
394 |
.name = "n270", |
|
395 |
/* original is on level 10 */ |
|
396 |
.level = 5, |
|
397 |
.family = 6, |
|
398 |
.model = 28, |
|
399 |
.stepping = 2, |
|
400 |
.features = PPRO_FEATURES | |
|
401 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME, |
|
402 |
/* Missing: CPUID_DTS | CPUID_ACPI | CPUID_SS | |
|
403 |
* CPUID_HT | CPUID_TM | CPUID_PBE */ |
|
404 |
/* Some CPUs got no CPUID_SEP */ |
|
405 |
.ext_features = CPUID_EXT_MONITOR | |
|
406 |
CPUID_EXT_SSE3 /* PNI */ | CPUID_EXT_SSSE3, |
|
407 |
/* Missing: CPUID_EXT_DSCPL | CPUID_EXT_EST | |
|
408 |
* CPUID_EXT_TM2 | CPUID_EXT_XTPR */ |
|
409 |
.ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_NX, |
|
410 |
/* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */ |
|
411 |
.xlevel = 0x8000000A, |
|
412 |
.model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", |
|
413 |
}, |
|
414 |
}; |
|
415 |
|
|
416 |
static int cpu_x86_fill_model_id(char *str) |
|
417 |
{ |
|
418 |
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; |
|
419 |
int i; |
|
420 |
|
|
421 |
for (i = 0; i < 3; i++) { |
|
422 |
host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); |
|
423 |
memcpy(str + i * 16 + 0, &eax, 4); |
|
424 |
memcpy(str + i * 16 + 4, &ebx, 4); |
|
425 |
memcpy(str + i * 16 + 8, &ecx, 4); |
|
426 |
memcpy(str + i * 16 + 12, &edx, 4); |
|
427 |
} |
|
428 |
return 0; |
|
429 |
} |
|
430 |
|
|
431 |
static int cpu_x86_fill_host(x86_def_t *x86_cpu_def) |
|
432 |
{ |
|
433 |
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; |
|
434 |
|
|
435 |
x86_cpu_def->name = "host"; |
|
436 |
host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); |
|
437 |
x86_cpu_def->level = eax; |
|
438 |
x86_cpu_def->vendor1 = ebx; |
|
439 |
x86_cpu_def->vendor2 = edx; |
|
440 |
x86_cpu_def->vendor3 = ecx; |
|
441 |
|
|
442 |
host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); |
|
443 |
x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); |
|
444 |
x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); |
|
445 |
x86_cpu_def->stepping = eax & 0x0F; |
|
446 |
x86_cpu_def->ext_features = ecx; |
|
447 |
x86_cpu_def->features = edx; |
|
448 |
|
|
449 |
host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx); |
|
450 |
x86_cpu_def->xlevel = eax; |
|
451 |
|
|
452 |
host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx); |
|
453 |
x86_cpu_def->ext2_features = edx; |
|
454 |
x86_cpu_def->ext3_features = ecx; |
|
455 |
cpu_x86_fill_model_id(x86_cpu_def->model_id); |
|
456 |
x86_cpu_def->vendor_override = 0; |
|
457 |
|
|
458 |
return 0; |
|
459 |
} |
|
460 |
|
|
461 |
static int unavailable_host_feature(struct model_features_t *f, uint32_t mask) |
|
462 |
{ |
|
463 |
int i; |
|
464 |
|
|
465 |
for (i = 0; i < 32; ++i) |
|
466 |
if (1 << i & mask) { |
|
467 |
fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested" |
|
468 |
" flag '%s' [0x%08x]\n", |
|
469 |
f->cpuid >> 16, f->cpuid & 0xffff, |
|
470 |
f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask); |
|
471 |
break; |
|
472 |
} |
|
473 |
return 0; |
|
474 |
} |
|
475 |
|
|
476 |
/* best effort attempt to inform user requested cpu flags aren't making |
|
477 |
* their way to the guest. Note: ft[].check_feat ideally should be |
|
478 |
* specified via a guest_def field to suppress report of extraneous flags. |
|
479 |
*/ |
|
480 |
static int check_features_against_host(x86_def_t *guest_def) |
|
481 |
{ |
|
482 |
x86_def_t host_def; |
|
483 |
uint32_t mask; |
|
484 |
int rv, i; |
|
485 |
struct model_features_t ft[] = { |
|
486 |
{&guest_def->features, &host_def.features, |
|
487 |
~0, feature_name, 0x00000000}, |
|
488 |
{&guest_def->ext_features, &host_def.ext_features, |
|
489 |
~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001}, |
|
490 |
{&guest_def->ext2_features, &host_def.ext2_features, |
|
491 |
~PPRO_FEATURES, ext2_feature_name, 0x80000000}, |
|
492 |
{&guest_def->ext3_features, &host_def.ext3_features, |
|
493 |
~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}}; |
|
494 |
|
|
495 |
cpu_x86_fill_host(&host_def); |
|
496 |
for (rv = 0, i = 0; i < sizeof (ft) / sizeof (ft[0]); ++i) |
|
497 |
for (mask = 1; mask; mask <<= 1) |
|
498 |
if (ft[i].check_feat & mask && *ft[i].guest_feat & mask && |
|
499 |
!(*ft[i].host_feat & mask)) { |
|
500 |
unavailable_host_feature(&ft[i], mask); |
|
501 |
rv = 1; |
|
502 |
} |
|
503 |
return rv; |
|
504 |
} |
|
505 |
|
|
506 |
static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model) |
|
507 |
{ |
|
508 |
unsigned int i; |
|
509 |
x86_def_t *def; |
|
510 |
|
|
511 |
char *s = strdup(cpu_model); |
|
512 |
char *featurestr, *name = strtok(s, ","); |
|
513 |
uint32_t plus_features = 0, plus_ext_features = 0, plus_ext2_features = 0, plus_ext3_features = 0, plus_kvm_features = 0; |
|
514 |
uint32_t minus_features = 0, minus_ext_features = 0, minus_ext2_features = 0, minus_ext3_features = 0, minus_kvm_features = 0; |
|
515 |
uint32_t numvalue; |
|
516 |
|
|
517 |
for (def = x86_defs; def; def = def->next) |
|
518 |
if (!strcmp(name, def->name)) |
|
519 |
break; |
|
520 |
if (kvm_enabled() && strcmp(name, "host") == 0) { |
|
521 |
cpu_x86_fill_host(x86_cpu_def); |
|
522 |
} else if (!def) { |
|
523 |
goto error; |
|
524 |
} else { |
|
525 |
memcpy(x86_cpu_def, def, sizeof(*def)); |
|
526 |
} |
|
527 |
|
|
528 |
plus_kvm_features = ~0; /* not supported bits will be filtered out later */ |
|
529 |
|
|
530 |
add_flagname_to_bitmaps("hypervisor", &plus_features, |
|
531 |
&plus_ext_features, &plus_ext2_features, &plus_ext3_features, |
|
532 |
&plus_kvm_features); |
|
533 |
|
|
534 |
featurestr = strtok(NULL, ","); |
|
535 |
|
|
536 |
while (featurestr) { |
|
537 |
char *val; |
|
538 |
if (featurestr[0] == '+') { |
|
539 |
add_flagname_to_bitmaps(featurestr + 1, &plus_features, &plus_ext_features, &plus_ext2_features, &plus_ext3_features, &plus_kvm_features); |
|
540 |
} else if (featurestr[0] == '-') { |
|
541 |
add_flagname_to_bitmaps(featurestr + 1, &minus_features, &minus_ext_features, &minus_ext2_features, &minus_ext3_features, &minus_kvm_features); |
|
542 |
} else if ((val = strchr(featurestr, '='))) { |
|
543 |
*val = 0; val++; |
|
544 |
if (!strcmp(featurestr, "family")) { |
|
545 |
char *err; |
|
546 |
numvalue = strtoul(val, &err, 0); |
|
547 |
if (!*val || *err) { |
|
548 |
fprintf(stderr, "bad numerical value %s\n", val); |
|
549 |
goto error; |
|
550 |
} |
|
551 |
x86_cpu_def->family = numvalue; |
|
552 |
} else if (!strcmp(featurestr, "model")) { |
|
553 |
char *err; |
|
554 |
numvalue = strtoul(val, &err, 0); |
|
555 |
if (!*val || *err || numvalue > 0xff) { |
|
556 |
fprintf(stderr, "bad numerical value %s\n", val); |
|
557 |
goto error; |
|
558 |
} |
|
559 |
x86_cpu_def->model = numvalue; |
|
560 |
} else if (!strcmp(featurestr, "stepping")) { |
|
561 |
char *err; |
|
562 |
numvalue = strtoul(val, &err, 0); |
|
563 |
if (!*val || *err || numvalue > 0xf) { |
|
564 |
fprintf(stderr, "bad numerical value %s\n", val); |
|
565 |
goto error; |
|
566 |
} |
|
567 |
x86_cpu_def->stepping = numvalue ; |
|
568 |
} else if (!strcmp(featurestr, "level")) { |
|
569 |
char *err; |
|
570 |
numvalue = strtoul(val, &err, 0); |
|
571 |
if (!*val || *err) { |
|
572 |
fprintf(stderr, "bad numerical value %s\n", val); |
|
573 |
goto error; |
|
574 |
} |
|
575 |
x86_cpu_def->level = numvalue; |
|
576 |
} else if (!strcmp(featurestr, "xlevel")) { |
|
577 |
char *err; |
|
578 |
numvalue = strtoul(val, &err, 0); |
|
579 |
if (!*val || *err) { |
|
580 |
fprintf(stderr, "bad numerical value %s\n", val); |
|
581 |
goto error; |
|
582 |
} |
|
583 |
if (numvalue < 0x80000000) { |
|
584 |
numvalue += 0x80000000; |
|
585 |
} |
|
586 |
x86_cpu_def->xlevel = numvalue; |
|
587 |
} else if (!strcmp(featurestr, "vendor")) { |
|
588 |
if (strlen(val) != 12) { |
|
589 |
fprintf(stderr, "vendor string must be 12 chars long\n"); |
|
590 |
goto error; |
|
591 |
} |
|
592 |
x86_cpu_def->vendor1 = 0; |
|
593 |
x86_cpu_def->vendor2 = 0; |
|
594 |
x86_cpu_def->vendor3 = 0; |
|
595 |
for(i = 0; i < 4; i++) { |
|
596 |
x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i); |
|
597 |
x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i); |
|
598 |
x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i); |
|
599 |
} |
|
600 |
x86_cpu_def->vendor_override = 1; |
|
601 |
} else if (!strcmp(featurestr, "model_id")) { |
|
602 |
pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id), |
|
603 |
val); |
|
604 |
} else { |
|
605 |
fprintf(stderr, "unrecognized feature %s\n", featurestr); |
|
606 |
goto error; |
|
607 |
} |
|
608 |
} else if (!strcmp(featurestr, "check")) { |
|
609 |
check_cpuid = 1; |
|
610 |
} else if (!strcmp(featurestr, "enforce")) { |
|
611 |
check_cpuid = enforce_cpuid = 1; |
|
612 |
} else { |
|
613 |
fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr); |
|
614 |
goto error; |
|
615 |
} |
|
616 |
featurestr = strtok(NULL, ","); |
|
617 |
} |
|
618 |
x86_cpu_def->features |= plus_features; |
|
619 |
x86_cpu_def->ext_features |= plus_ext_features; |
|
620 |
x86_cpu_def->ext2_features |= plus_ext2_features; |
|
621 |
x86_cpu_def->ext3_features |= plus_ext3_features; |
|
622 |
x86_cpu_def->kvm_features |= plus_kvm_features; |
|
623 |
x86_cpu_def->features &= ~minus_features; |
|
624 |
x86_cpu_def->ext_features &= ~minus_ext_features; |
|
625 |
x86_cpu_def->ext2_features &= ~minus_ext2_features; |
|
626 |
x86_cpu_def->ext3_features &= ~minus_ext3_features; |
|
627 |
x86_cpu_def->kvm_features &= ~minus_kvm_features; |
|
628 |
if (check_cpuid) { |
|
629 |
if (check_features_against_host(x86_cpu_def) && enforce_cpuid) |
|
630 |
goto error; |
|
631 |
} |
|
632 |
free(s); |
|
633 |
return 0; |
|
634 |
|
|
635 |
error: |
|
636 |
free(s); |
|
637 |
return -1; |
|
638 |
} |
|
639 |
|
|
640 |
/* generate a composite string into buf of all cpuid names in featureset |
|
641 |
* selected by fbits. indicate truncation at bufsize in the event of overflow. |
|
642 |
* if flags, suppress names undefined in featureset. |
|
643 |
*/ |
|
644 |
static void listflags(char *buf, int bufsize, uint32_t fbits, |
|
645 |
const char **featureset, uint32_t flags) |
|
646 |
{ |
|
647 |
const char **p = &featureset[31]; |
|
648 |
char *q, *b, bit; |
|
649 |
int nc; |
|
650 |
|
|
651 |
b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL; |
|
652 |
*buf = '\0'; |
|
653 |
for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit) |
|
654 |
if (fbits & 1 << bit && (*p || !flags)) { |
|
655 |
if (*p) |
|
656 |
nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p); |
|
657 |
else |
|
658 |
nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit); |
|
659 |
if (bufsize <= nc) { |
|
660 |
if (b) { |
|
661 |
memcpy(b, "...", sizeof("...")); |
|
662 |
} |
|
663 |
return; |
|
664 |
} |
|
665 |
q += nc; |
|
666 |
bufsize -= nc; |
|
667 |
} |
|
668 |
} |
|
669 |
|
|
670 |
/* generate CPU information: |
|
671 |
* -? list model names |
|
672 |
* -?model list model names/IDs |
|
673 |
* -?dump output all model (x86_def_t) data |
|
674 |
* -?cpuid list all recognized cpuid flag names |
|
675 |
*/ |
|
676 |
void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
|
677 |
const char *optarg) |
|
678 |
{ |
|
679 |
unsigned char model = !strcmp("?model", optarg); |
|
680 |
unsigned char dump = !strcmp("?dump", optarg); |
|
681 |
unsigned char cpuid = !strcmp("?cpuid", optarg); |
|
682 |
x86_def_t *def; |
|
683 |
char buf[256]; |
|
684 |
|
|
685 |
if (cpuid) { |
|
686 |
(*cpu_fprintf)(f, "Recognized CPUID flags:\n"); |
|
687 |
listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1); |
|
688 |
(*cpu_fprintf)(f, " f_edx: %s\n", buf); |
|
689 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1); |
|
690 |
(*cpu_fprintf)(f, " f_ecx: %s\n", buf); |
|
691 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1); |
|
692 |
(*cpu_fprintf)(f, " extf_edx: %s\n", buf); |
|
693 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1); |
|
694 |
(*cpu_fprintf)(f, " extf_ecx: %s\n", buf); |
|
695 |
return; |
|
696 |
} |
|
697 |
for (def = x86_defs; def; def = def->next) { |
|
698 |
snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name); |
|
699 |
if (model || dump) { |
|
700 |
(*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id); |
|
701 |
} else { |
|
702 |
(*cpu_fprintf)(f, "x86 %16s\n", buf); |
|
703 |
} |
|
704 |
if (dump) { |
|
705 |
memcpy(buf, &def->vendor1, sizeof (def->vendor1)); |
|
706 |
memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2)); |
|
707 |
memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3)); |
|
708 |
buf[12] = '\0'; |
|
709 |
(*cpu_fprintf)(f, |
|
710 |
" family %d model %d stepping %d level %d xlevel 0x%x" |
|
711 |
" vendor \"%s\"\n", |
|
712 |
def->family, def->model, def->stepping, def->level, |
|
713 |
def->xlevel, buf); |
|
714 |
listflags(buf, sizeof (buf), def->features, feature_name, 0); |
|
715 |
(*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features, |
|
716 |
buf); |
|
717 |
listflags(buf, sizeof (buf), def->ext_features, ext_feature_name, |
|
718 |
0); |
|
719 |
(*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features, |
|
720 |
buf); |
|
721 |
listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name, |
|
722 |
0); |
|
723 |
(*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n", |
|
724 |
def->ext2_features, buf); |
|
725 |
listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name, |
|
726 |
0); |
|
727 |
(*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n", |
|
728 |
def->ext3_features, buf); |
|
729 |
(*cpu_fprintf)(f, "\n"); |
|
730 |
} |
|
731 |
} |
|
732 |
} |
|
733 |
|
|
734 |
static int cpu_x86_register (CPUX86State *env, const char *cpu_model) |
|
735 |
{ |
|
736 |
x86_def_t def1, *def = &def1; |
|
737 |
|
|
738 |
if (cpu_x86_find_by_name(def, cpu_model) < 0) |
|
739 |
return -1; |
|
740 |
if (def->vendor1) { |
|
741 |
env->cpuid_vendor1 = def->vendor1; |
|
742 |
env->cpuid_vendor2 = def->vendor2; |
|
743 |
env->cpuid_vendor3 = def->vendor3; |
|
744 |
} else { |
|
745 |
env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1; |
|
746 |
env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2; |
|
747 |
env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3; |
|
748 |
} |
|
749 |
env->cpuid_vendor_override = def->vendor_override; |
|
750 |
env->cpuid_level = def->level; |
|
751 |
if (def->family > 0x0f) |
|
752 |
env->cpuid_version = 0xf00 | ((def->family - 0x0f) << 20); |
|
753 |
else |
|
754 |
env->cpuid_version = def->family << 8; |
|
755 |
env->cpuid_version |= ((def->model & 0xf) << 4) | ((def->model >> 4) << 16); |
|
756 |
env->cpuid_version |= def->stepping; |
|
757 |
env->cpuid_features = def->features; |
|
758 |
env->pat = 0x0007040600070406ULL; |
|
759 |
env->cpuid_ext_features = def->ext_features; |
|
760 |
env->cpuid_ext2_features = def->ext2_features; |
|
761 |
env->cpuid_xlevel = def->xlevel; |
|
762 |
env->cpuid_kvm_features = def->kvm_features; |
|
763 |
{ |
|
764 |
const char *model_id = def->model_id; |
|
765 |
int c, len, i; |
|
766 |
if (!model_id) |
|
767 |
model_id = ""; |
|
768 |
len = strlen(model_id); |
|
769 |
for(i = 0; i < 48; i++) { |
|
770 |
if (i >= len) |
|
771 |
c = '\0'; |
|
772 |
else |
|
773 |
c = (uint8_t)model_id[i]; |
|
774 |
env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); |
|
775 |
} |
|
776 |
} |
|
777 |
return 0; |
|
778 |
} |
|
779 |
|
|
780 |
#if !defined(CONFIG_USER_ONLY) |
|
781 |
/* copy vendor id string to 32 bit register, nul pad as needed |
|
782 |
*/ |
|
783 |
static void cpyid(const char *s, uint32_t *id) |
|
784 |
{ |
|
785 |
char *d = (char *)id; |
|
786 |
char i; |
|
787 |
|
|
788 |
for (i = sizeof (*id); i--; ) |
|
789 |
*d++ = *s ? *s++ : '\0'; |
|
790 |
} |
|
791 |
|
|
792 |
/* interpret radix and convert from string to arbitrary scalar, |
|
793 |
* otherwise flag failure |
|
794 |
*/ |
|
795 |
#define setscalar(pval, str, perr) \ |
|
796 |
{ \ |
|
797 |
char *pend; \ |
|
798 |
unsigned long ul; \ |
|
799 |
\ |
|
800 |
ul = strtoul(str, &pend, 0); \ |
|
801 |
*str && !*pend ? (*pval = ul) : (*perr = 1); \ |
|
802 |
} |
|
803 |
|
|
804 |
/* map cpuid options to feature bits, otherwise return failure |
|
805 |
* (option tags in *str are delimited by whitespace) |
|
806 |
*/ |
|
807 |
static void setfeatures(uint32_t *pval, const char *str, |
|
808 |
const char **featureset, int *perr) |
|
809 |
{ |
|
810 |
const char *p, *q; |
|
811 |
|
|
812 |
for (q = p = str; *p || *q; q = p) { |
|
813 |
while (iswhite(*p)) |
|
814 |
q = ++p; |
|
815 |
while (*p && !iswhite(*p)) |
|
816 |
++p; |
|
817 |
if (!*q && !*p) |
|
818 |
return; |
|
819 |
if (!lookup_feature(pval, q, p, featureset)) { |
|
820 |
fprintf(stderr, "error: feature \"%.*s\" not available in set\n", |
|
821 |
(int)(p - q), q); |
|
822 |
*perr = 1; |
|
823 |
return; |
|
824 |
} |
|
825 |
} |
|
826 |
} |
|
827 |
|
|
828 |
/* map config file options to x86_def_t form |
|
829 |
*/ |
|
830 |
static int cpudef_setfield(const char *name, const char *str, void *opaque) |
|
831 |
{ |
|
832 |
x86_def_t *def = opaque; |
|
833 |
int err = 0; |
|
834 |
|
|
835 |
if (!strcmp(name, "name")) { |
|
836 |
def->name = strdup(str); |
|
837 |
} else if (!strcmp(name, "model_id")) { |
|
838 |
strncpy(def->model_id, str, sizeof (def->model_id)); |
|
839 |
} else if (!strcmp(name, "level")) { |
|
840 |
setscalar(&def->level, str, &err) |
|
841 |
} else if (!strcmp(name, "vendor")) { |
|
842 |
cpyid(&str[0], &def->vendor1); |
|
843 |
cpyid(&str[4], &def->vendor2); |
|
844 |
cpyid(&str[8], &def->vendor3); |
|
845 |
} else if (!strcmp(name, "family")) { |
|
846 |
setscalar(&def->family, str, &err) |
|
847 |
} else if (!strcmp(name, "model")) { |
|
848 |
setscalar(&def->model, str, &err) |
|
849 |
} else if (!strcmp(name, "stepping")) { |
|
850 |
setscalar(&def->stepping, str, &err) |
|
851 |
} else if (!strcmp(name, "feature_edx")) { |
|
852 |
setfeatures(&def->features, str, feature_name, &err); |
|
853 |
} else if (!strcmp(name, "feature_ecx")) { |
|
854 |
setfeatures(&def->ext_features, str, ext_feature_name, &err); |
|
855 |
} else if (!strcmp(name, "extfeature_edx")) { |
|
856 |
setfeatures(&def->ext2_features, str, ext2_feature_name, &err); |
|
857 |
} else if (!strcmp(name, "extfeature_ecx")) { |
|
858 |
setfeatures(&def->ext3_features, str, ext3_feature_name, &err); |
|
859 |
} else if (!strcmp(name, "xlevel")) { |
|
860 |
setscalar(&def->xlevel, str, &err) |
|
861 |
} else { |
|
862 |
fprintf(stderr, "error: unknown option [%s = %s]\n", name, str); |
|
863 |
return (1); |
|
864 |
} |
|
865 |
if (err) { |
|
866 |
fprintf(stderr, "error: bad option value [%s = %s]\n", name, str); |
|
867 |
return (1); |
|
868 |
} |
|
869 |
return (0); |
|
870 |
} |
|
871 |
|
|
872 |
/* register config file entry as x86_def_t |
|
873 |
*/ |
|
874 |
static int cpudef_register(QemuOpts *opts, void *opaque) |
|
875 |
{ |
|
876 |
x86_def_t *def = qemu_mallocz(sizeof (x86_def_t)); |
|
877 |
|
|
878 |
qemu_opt_foreach(opts, cpudef_setfield, def, 1); |
|
879 |
def->next = x86_defs; |
|
880 |
x86_defs = def; |
|
881 |
return (0); |
|
882 |
} |
|
883 |
#endif /* !CONFIG_USER_ONLY */ |
|
884 |
|
|
885 |
/* register "cpudef" models defined in configuration file. Here we first |
|
886 |
* preload any built-in definitions |
|
887 |
*/ |
|
888 |
void x86_cpudef_setup(void) |
|
889 |
{ |
|
890 |
int i; |
|
891 |
|
|
892 |
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) { |
|
893 |
builtin_x86_defs[i].next = x86_defs; |
|
894 |
builtin_x86_defs[i].flags = 1; |
|
895 |
x86_defs = &builtin_x86_defs[i]; |
|
896 |
} |
|
897 |
#if !defined(CONFIG_USER_ONLY) |
|
898 |
qemu_opts_foreach(&qemu_cpudef_opts, cpudef_register, NULL, 0); |
|
899 |
#endif |
|
900 |
} |
|
901 | 32 |
|
902 | 33 |
/* NOTE: must be called outside the CPU execute loop */ |
903 | 34 |
void cpu_reset(CPUX86State *env) |
... | ... | |
1954 | 1085 |
} |
1955 | 1086 |
} |
1956 | 1087 |
|
1957 |
static void host_cpuid(uint32_t function, uint32_t count, |
|
1958 |
uint32_t *eax, uint32_t *ebx, |
|
1959 |
uint32_t *ecx, uint32_t *edx) |
|
1960 |
{ |
|
1961 |
#if defined(CONFIG_KVM) |
|
1962 |
uint32_t vec[4]; |
|
1963 |
|
|
1964 |
#ifdef __x86_64__ |
|
1965 |
asm volatile("cpuid" |
|
1966 |
: "=a"(vec[0]), "=b"(vec[1]), |
|
1967 |
"=c"(vec[2]), "=d"(vec[3]) |
|
1968 |
: "0"(function), "c"(count) : "cc"); |
|
1969 |
#else |
|
1970 |
asm volatile("pusha \n\t" |
|
1971 |
"cpuid \n\t" |
|
1972 |
"mov %%eax, 0(%2) \n\t" |
|
1973 |
"mov %%ebx, 4(%2) \n\t" |
|
1974 |
"mov %%ecx, 8(%2) \n\t" |
|
1975 |
"mov %%edx, 12(%2) \n\t" |
|
1976 |
"popa" |
|
1977 |
: : "a"(function), "c"(count), "S"(vec) |
|
1978 |
: "memory", "cc"); |
|
1979 |
#endif |
|
1980 |
|
|
1981 |
if (eax) |
|
1982 |
*eax = vec[0]; |
|
1983 |
if (ebx) |
|
1984 |
*ebx = vec[1]; |
|
1985 |
if (ecx) |
|
1986 |
*ecx = vec[2]; |
|
1987 |
if (edx) |
|
1988 |
*edx = vec[3]; |
|
1989 |
#endif |
|
1990 |
} |
|
1991 |
|
|
1992 |
static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx, |
|
1993 |
uint32_t *ecx, uint32_t *edx) |
|
1994 |
{ |
|
1995 |
*ebx = env->cpuid_vendor1; |
|
1996 |
*edx = env->cpuid_vendor2; |
|
1997 |
*ecx = env->cpuid_vendor3; |
|
1998 |
|
|
1999 |
/* sysenter isn't supported on compatibility mode on AMD, syscall |
|
2000 |
* isn't supported in compatibility mode on Intel. |
|
2001 |
* Normally we advertise the actual cpu vendor, but you can override |
|
2002 |
* this if you want to use KVM's sysenter/syscall emulation |
|
2003 |
* in compatibility mode and when doing cross vendor migration |
|
2004 |
*/ |
|
2005 |
if (kvm_enabled() && env->cpuid_vendor_override) { |
|
2006 |
host_cpuid(0, 0, NULL, ebx, ecx, edx); |
|
2007 |
} |
|
2008 |
} |
|
2009 |
|
|
2010 |
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, |
|
2011 |
uint32_t *eax, uint32_t *ebx, |
|
2012 |
uint32_t *ecx, uint32_t *edx) |
|
2013 |
{ |
|
2014 |
/* test if maximum index reached */ |
|
2015 |
if (index & 0x80000000) { |
|
2016 |
if (index > env->cpuid_xlevel) |
|
2017 |
index = env->cpuid_level; |
|
2018 |
} else { |
|
2019 |
if (index > env->cpuid_level) |
|
2020 |
index = env->cpuid_level; |
|
2021 |
} |
|
2022 |
|
|
2023 |
switch(index) { |
|
2024 |
case 0: |
|
2025 |
*eax = env->cpuid_level; |
|
2026 |
get_cpuid_vendor(env, ebx, ecx, edx); |
|
2027 |
break; |
|
2028 |
case 1: |
|
2029 |
*eax = env->cpuid_version; |
|
2030 |
*ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ |
|
2031 |
*ecx = env->cpuid_ext_features; |
|
2032 |
*edx = env->cpuid_features; |
|
2033 |
if (env->nr_cores * env->nr_threads > 1) { |
|
2034 |
*ebx |= (env->nr_cores * env->nr_threads) << 16; |
|
2035 |
*edx |= 1 << 28; /* HTT bit */ |
|
2036 |
} |
|
2037 |
break; |
|
2038 |
case 2: |
|
2039 |
/* cache info: needed for Pentium Pro compatibility */ |
|
2040 |
*eax = 1; |
|
2041 |
*ebx = 0; |
|
2042 |
*ecx = 0; |
|
2043 |
*edx = 0x2c307d; |
|
2044 |
break; |
|
2045 |
case 4: |
|
2046 |
/* cache info: needed for Core compatibility */ |
|
2047 |
if (env->nr_cores > 1) { |
|
2048 |
*eax = (env->nr_cores - 1) << 26; |
|
2049 |
} else { |
|
2050 |
*eax = 0; |
|
2051 |
} |
|
2052 |
switch (count) { |
|
2053 |
case 0: /* L1 dcache info */ |
|
2054 |
*eax |= 0x0000121; |
|
2055 |
*ebx = 0x1c0003f; |
|
2056 |
*ecx = 0x000003f; |
|
2057 |
*edx = 0x0000001; |
|
2058 |
break; |
|
2059 |
case 1: /* L1 icache info */ |
|
2060 |
*eax |= 0x0000122; |
|
2061 |
*ebx = 0x1c0003f; |
|
2062 |
*ecx = 0x000003f; |
|
2063 |
*edx = 0x0000001; |
|
2064 |
break; |
|
2065 |
case 2: /* L2 cache info */ |
|
2066 |
*eax |= 0x0000143; |
|
2067 |
if (env->nr_threads > 1) { |
|
2068 |
*eax |= (env->nr_threads - 1) << 14; |
|
2069 |
} |
|
2070 |
*ebx = 0x3c0003f; |
|
2071 |
*ecx = 0x0000fff; |
|
2072 |
*edx = 0x0000001; |
|
2073 |
break; |
|
2074 |
default: /* end of info */ |
|
2075 |
*eax = 0; |
|
2076 |
*ebx = 0; |
|
2077 |
*ecx = 0; |
|
2078 |
*edx = 0; |
|
2079 |
break; |
|
2080 |
} |
|
2081 |
break; |
|
2082 |
case 5: |
|
2083 |
/* mwait info: needed for Core compatibility */ |
|
2084 |
*eax = 0; /* Smallest monitor-line size in bytes */ |
|
2085 |
*ebx = 0; /* Largest monitor-line size in bytes */ |
|
2086 |
*ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; |
|
2087 |
*edx = 0; |
|
2088 |
break; |
|
2089 |
case 6: |
|
2090 |
/* Thermal and Power Leaf */ |
|
2091 |
*eax = 0; |
|
2092 |
*ebx = 0; |
|
2093 |
*ecx = 0; |
|
2094 |
*edx = 0; |
|
2095 |
break; |
|
2096 |
case 9: |
|
2097 |
/* Direct Cache Access Information Leaf */ |
|
2098 |
*eax = 0; /* Bits 0-31 in DCA_CAP MSR */ |
|
2099 |
*ebx = 0; |
|
2100 |
*ecx = 0; |
|
2101 |
*edx = 0; |
|
2102 |
break; |
|
2103 |
case 0xA: |
|
2104 |
/* Architectural Performance Monitoring Leaf */ |
|
2105 |
*eax = 0; |
|
2106 |
*ebx = 0; |
|
2107 |
*ecx = 0; |
|
2108 |
*edx = 0; |
|
2109 |
break; |
|
2110 |
case 0x80000000: |
|
2111 |
*eax = env->cpuid_xlevel; |
|
2112 |
*ebx = env->cpuid_vendor1; |
|
2113 |
*edx = env->cpuid_vendor2; |
|
2114 |
*ecx = env->cpuid_vendor3; |
|
2115 |
break; |
|
2116 |
case 0x80000001: |
|
2117 |
*eax = env->cpuid_version; |
|
2118 |
*ebx = 0; |
|
2119 |
*ecx = env->cpuid_ext3_features; |
|
2120 |
*edx = env->cpuid_ext2_features; |
|
2121 |
|
|
2122 |
/* The Linux kernel checks for the CMPLegacy bit and |
|
2123 |
* discards multiple thread information if it is set. |
|
2124 |
* So dont set it here for Intel to make Linux guests happy. |
|
2125 |
*/ |
|
2126 |
if (env->nr_cores * env->nr_threads > 1) { |
|
2127 |
uint32_t tebx, tecx, tedx; |
|
2128 |
get_cpuid_vendor(env, &tebx, &tecx, &tedx); |
|
2129 |
if (tebx != CPUID_VENDOR_INTEL_1 || |
|
2130 |
tedx != CPUID_VENDOR_INTEL_2 || |
|
2131 |
tecx != CPUID_VENDOR_INTEL_3) { |
|
2132 |
*ecx |= 1 << 1; /* CmpLegacy bit */ |
|
2133 |
} |
|
2134 |
} |
|
2135 |
|
|
2136 |
if (kvm_enabled()) { |
|
2137 |
/* Nested SVM not yet supported in upstream QEMU */ |
|
2138 |
*ecx &= ~CPUID_EXT3_SVM; |
|
2139 |
} |
|
2140 |
break; |
|
2141 |
case 0x80000002: |
|
2142 |
case 0x80000003: |
|
2143 |
case 0x80000004: |
|
2144 |
*eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; |
|
2145 |
*ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; |
|
2146 |
*ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; |
|
2147 |
*edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; |
|
2148 |
break; |
|
2149 |
case 0x80000005: |
|
2150 |
/* cache info (L1 cache) */ |
|
2151 |
*eax = 0x01ff01ff; |
|
2152 |
*ebx = 0x01ff01ff; |
|
2153 |
*ecx = 0x40020140; |
|
2154 |
*edx = 0x40020140; |
|
2155 |
break; |
|
2156 |
case 0x80000006: |
|
2157 |
/* cache info (L2 cache) */ |
|
2158 |
*eax = 0; |
|
2159 |
*ebx = 0x42004200; |
|
2160 |
*ecx = 0x02008140; |
|
2161 |
*edx = 0; |
|
2162 |
break; |
|
2163 |
case 0x80000008: |
|
2164 |
/* virtual & phys address size in low 2 bytes. */ |
|
2165 |
/* XXX: This value must match the one used in the MMU code. */ |
|
2166 |
if (env->cpuid_ext2_features & CPUID_EXT2_LM) { |
|
2167 |
/* 64 bit processor */ |
|
2168 |
/* XXX: The physical address space is limited to 42 bits in exec.c. */ |
|
2169 |
*eax = 0x00003028; /* 48 bits virtual, 40 bits physical */ |
|
2170 |
} else { |
|
2171 |
if (env->cpuid_features & CPUID_PSE36) |
|
2172 |
*eax = 0x00000024; /* 36 bits physical */ |
|
2173 |
else |
|
2174 |
*eax = 0x00000020; /* 32 bits physical */ |
|
2175 |
} |
|
2176 |
*ebx = 0; |
|
2177 |
*ecx = 0; |
|
2178 |
*edx = 0; |
|
2179 |
if (env->nr_cores * env->nr_threads > 1) { |
|
2180 |
*ecx |= (env->nr_cores * env->nr_threads) - 1; |
|
2181 |
} |
|
2182 |
break; |
|
2183 |
case 0x8000000A: |
|
2184 |
*eax = 0x00000001; /* SVM Revision */ |
|
2185 |
*ebx = 0x00000010; /* nr of ASIDs */ |
|
2186 |
*ecx = 0; |
|
2187 |
*edx = 0; /* optional features */ |
|
2188 |
break; |
|
2189 |
default: |
|
2190 |
/* reserved values: zero */ |
|
2191 |
*eax = 0; |
|
2192 |
*ebx = 0; |
|
2193 |
*ecx = 0; |
|
2194 |
*edx = 0; |
|
2195 |
break; |
|
2196 |
} |
|
2197 |
} |
|
2198 |
|
|
2199 |
|
|
2200 | 1088 |
int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
2201 | 1089 |
target_ulong *base, unsigned int *limit, |
2202 | 1090 |
unsigned int *flags) |
Also available in: Unified diff