root / target-ppc / op_helper_mem.h @ c7697e1f
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/*
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* PowerPC emulation micro-operations helpers for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* Multiple word / string load and store */
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static always_inline target_ulong glue(ld32r, MEMSUFFIX) (target_ulong EA)
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{
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uint32_t tmp = glue(ldl, MEMSUFFIX)(EA); |
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return ((tmp & 0xFF000000UL) >> 24) | ((tmp & 0x00FF0000UL) >> 8) | |
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((tmp & 0x0000FF00UL) << 8) | ((tmp & 0x000000FFUL) << 24); |
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} |
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static always_inline void glue(st32r, MEMSUFFIX) (target_ulong EA, |
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target_ulong data) |
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{
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uint32_t tmp = |
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((data & 0xFF000000UL) >> 24) | ((data & 0x00FF0000UL) >> 8) | |
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((data & 0x0000FF00UL) << 8) | ((data & 0x000000FFUL) << 24); |
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glue(stl, MEMSUFFIX)(EA, tmp); |
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} |
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void glue(do_lmw, MEMSUFFIX) (int dst) |
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{
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for (; dst < 32; dst++, T0 += 4) { |
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env->gpr[dst] = glue(ldl, MEMSUFFIX)((uint32_t)T0); |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_lmw_64, MEMSUFFIX) (int dst) |
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{
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for (; dst < 32; dst++, T0 += 4) { |
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env->gpr[dst] = glue(ldl, MEMSUFFIX)((uint64_t)T0); |
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} |
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} |
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#endif
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void glue(do_stmw, MEMSUFFIX) (int src) |
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{
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for (; src < 32; src++, T0 += 4) { |
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glue(stl, MEMSUFFIX)((uint32_t)T0, env->gpr[src]); |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_stmw_64, MEMSUFFIX) (int src) |
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{
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for (; src < 32; src++, T0 += 4) { |
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glue(stl, MEMSUFFIX)((uint64_t)T0, env->gpr[src]); |
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} |
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} |
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#endif
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void glue(do_lmw_le, MEMSUFFIX) (int dst) |
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{
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for (; dst < 32; dst++, T0 += 4) { |
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env->gpr[dst] = glue(ld32r, MEMSUFFIX)((uint32_t)T0); |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_lmw_le_64, MEMSUFFIX) (int dst) |
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{
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for (; dst < 32; dst++, T0 += 4) { |
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env->gpr[dst] = glue(ld32r, MEMSUFFIX)((uint64_t)T0); |
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} |
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} |
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#endif
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void glue(do_stmw_le, MEMSUFFIX) (int src) |
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{
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for (; src < 32; src++, T0 += 4) { |
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glue(st32r, MEMSUFFIX)((uint32_t)T0, env->gpr[src]); |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_stmw_le_64, MEMSUFFIX) (int src) |
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{
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for (; src < 32; src++, T0 += 4) { |
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glue(st32r, MEMSUFFIX)((uint64_t)T0, env->gpr[src]); |
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} |
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} |
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#endif
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void glue(do_lsw, MEMSUFFIX) (int dst) |
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{
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uint32_t tmp; |
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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env->gpr[dst++] = glue(ldl, MEMSUFFIX)((uint32_t)T0); |
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if (unlikely(dst == 32)) |
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dst = 0;
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} |
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if (unlikely(T1 != 0)) { |
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tmp = 0;
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) { |
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tmp |= glue(ldub, MEMSUFFIX)((uint32_t)T0) << sh; |
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} |
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env->gpr[dst] = tmp; |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_lsw_64, MEMSUFFIX) (int dst) |
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{
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uint32_t tmp; |
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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env->gpr[dst++] = glue(ldl, MEMSUFFIX)((uint64_t)T0); |
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if (unlikely(dst == 32)) |
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dst = 0;
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} |
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if (unlikely(T1 != 0)) { |
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tmp = 0;
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) { |
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tmp |= glue(ldub, MEMSUFFIX)((uint64_t)T0) << sh; |
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} |
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env->gpr[dst] = tmp; |
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} |
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} |
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#endif
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void glue(do_stsw, MEMSUFFIX) (int src) |
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{
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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glue(stl, MEMSUFFIX)((uint32_t)T0, env->gpr[src++]); |
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if (unlikely(src == 32)) |
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src = 0;
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} |
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if (unlikely(T1 != 0)) { |
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) |
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glue(stb, MEMSUFFIX)((uint32_t)T0, (env->gpr[src] >> sh) & 0xFF);
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_stsw_64, MEMSUFFIX) (int src) |
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{
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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glue(stl, MEMSUFFIX)((uint64_t)T0, env->gpr[src++]); |
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if (unlikely(src == 32)) |
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src = 0;
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} |
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if (unlikely(T1 != 0)) { |
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for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) |
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glue(stb, MEMSUFFIX)((uint64_t)T0, (env->gpr[src] >> sh) & 0xFF);
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} |
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} |
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#endif
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void glue(do_lsw_le, MEMSUFFIX) (int dst) |
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{
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uint32_t tmp; |
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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env->gpr[dst++] = glue(ld32r, MEMSUFFIX)((uint32_t)T0); |
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if (unlikely(dst == 32)) |
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dst = 0;
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} |
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if (unlikely(T1 != 0)) { |
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tmp = 0;
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8) { |
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tmp |= glue(ldub, MEMSUFFIX)((uint32_t)T0) << sh; |
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} |
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env->gpr[dst] = tmp; |
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_lsw_le_64, MEMSUFFIX) (int dst) |
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{
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uint32_t tmp; |
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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env->gpr[dst++] = glue(ld32r, MEMSUFFIX)((uint64_t)T0); |
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if (unlikely(dst == 32)) |
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dst = 0;
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} |
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if (unlikely(T1 != 0)) { |
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tmp = 0;
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8) { |
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tmp |= glue(ldub, MEMSUFFIX)((uint64_t)T0) << sh; |
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} |
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env->gpr[dst] = tmp; |
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} |
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} |
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#endif
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void glue(do_stsw_le, MEMSUFFIX) (int src) |
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{
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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glue(st32r, MEMSUFFIX)((uint32_t)T0, env->gpr[src++]); |
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if (unlikely(src == 32)) |
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src = 0;
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} |
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if (unlikely(T1 != 0)) { |
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8) |
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glue(stb, MEMSUFFIX)((uint32_t)T0, (env->gpr[src] >> sh) & 0xFF);
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} |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_stsw_le_64, MEMSUFFIX) (int src) |
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{
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int sh;
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for (; T1 > 3; T1 -= 4, T0 += 4) { |
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glue(st32r, MEMSUFFIX)((uint64_t)T0, env->gpr[src++]); |
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if (unlikely(src == 32)) |
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src = 0;
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} |
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if (unlikely(T1 != 0)) { |
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for (sh = 0; T1 > 0; T1--, T0++, sh += 8) |
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glue(stb, MEMSUFFIX)((uint64_t)T0, (env->gpr[src] >> sh) & 0xFF);
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} |
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} |
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#endif
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/* Instruction cache invalidation helper */
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void glue(do_icbi, MEMSUFFIX) (void) |
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{
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uint32_t tmp; |
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/* Invalidate one cache line :
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* PowerPC specification says this is to be treated like a load
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* (not a fetch) by the MMU. To be sure it will be so,
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* do the load "by hand".
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*/
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tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0); |
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T0 &= ~(env->icache_line_size - 1);
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tb_invalidate_page_range((uint32_t)T0, |
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(uint32_t)(T0 + env->icache_line_size)); |
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} |
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#if defined(TARGET_PPC64)
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void glue(do_icbi_64, MEMSUFFIX) (void) |
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{
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uint64_t tmp; |
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/* Invalidate one cache line :
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* PowerPC specification says this is to be treated like a load
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* (not a fetch) by the MMU. To be sure it will be so,
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* do the load "by hand".
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*/
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tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0); |
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T0 &= ~(env->icache_line_size - 1);
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tb_invalidate_page_range((uint64_t)T0, |
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(uint64_t)(T0 + env->icache_line_size)); |
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} |
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#endif
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void glue(do_dcbz, MEMSUFFIX) (void) |
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{
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int dcache_line_size = env->dcache_line_size;
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/* XXX: should be 970 specific (?) */
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if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) |
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dcache_line_size = 32;
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0); |
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if (dcache_line_size >= 64) { |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x2CUL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x30UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0); |
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if (dcache_line_size >= 128) { |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x40UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x44UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x48UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x4CUL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x50UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x54UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x58UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x5CUL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x60UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x64UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x68UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x6CUL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x70UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x74UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x78UL), 0); |
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glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x7CUL), 0); |
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} |
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} |
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} |
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|
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#if defined(TARGET_PPC64)
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void glue(do_dcbz_64, MEMSUFFIX) (void) |
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{
|
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int dcache_line_size = env->dcache_line_size;
|
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|
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/* XXX: should be 970 specific (?) */
|
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if (((env->spr[SPR_970_HID5] >> 6) & 0x3) == 0x2) |
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dcache_line_size = 32;
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glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0); |
| 331 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0); |
| 332 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0); |
| 333 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0); |
| 334 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0); |
| 335 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0); |
| 336 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0); |
| 337 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0); |
| 338 |
if (dcache_line_size >= 64) { |
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glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0); |
| 340 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0); |
| 341 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0); |
| 342 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x2CUL), 0); |
| 343 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x30UL), 0); |
| 344 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0); |
| 345 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0); |
| 346 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0); |
| 347 |
if (dcache_line_size >= 128) { |
| 348 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x40UL), 0); |
| 349 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x44UL), 0); |
| 350 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x48UL), 0); |
| 351 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x4CUL), 0); |
| 352 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x50UL), 0); |
| 353 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x54UL), 0); |
| 354 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x58UL), 0); |
| 355 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x5CUL), 0); |
| 356 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x60UL), 0); |
| 357 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x64UL), 0); |
| 358 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x68UL), 0); |
| 359 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x6CUL), 0); |
| 360 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x70UL), 0); |
| 361 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x74UL), 0); |
| 362 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x78UL), 0); |
| 363 |
glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x7CUL), 0); |
| 364 |
} |
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} |
| 366 |
} |
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#endif
|
| 368 |
|
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/* PowerPC 601 specific instructions (POWER bridge) */
|
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// XXX: to be tested
|
| 371 |
void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb) |
| 372 |
{
|
| 373 |
int i, c, d, reg;
|
| 374 |
|
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d = 24;
|
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reg = dest; |
| 377 |
for (i = 0; i < T1; i++) { |
| 378 |
c = glue(ldub, MEMSUFFIX)((uint32_t)T0++); |
| 379 |
/* ra (if not 0) and rb are never modified */
|
| 380 |
if (likely(reg != rb && (ra == 0 || reg != ra))) { |
| 381 |
env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
|
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} |
| 383 |
if (unlikely(c == T2))
|
| 384 |
break;
|
| 385 |
if (likely(d != 0)) { |
| 386 |
d -= 8;
|
| 387 |
} else {
|
| 388 |
d = 24;
|
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reg++; |
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reg = reg & 0x1F;
|
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} |
| 392 |
} |
| 393 |
T0 = i; |
| 394 |
} |
| 395 |
|
| 396 |
/* XXX: TAGs are not managed */
|
| 397 |
void glue(do_POWER2_lfq, MEMSUFFIX) (void) |
| 398 |
{
|
| 399 |
FT0 = glue(ldfq, MEMSUFFIX)((uint32_t)T0); |
| 400 |
FT1 = glue(ldfq, MEMSUFFIX)((uint32_t)(T0 + 4));
|
| 401 |
} |
| 402 |
|
| 403 |
static always_inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA) |
| 404 |
{
|
| 405 |
union {
|
| 406 |
double d;
|
| 407 |
uint64_t u; |
| 408 |
} u; |
| 409 |
|
| 410 |
u.d = glue(ldfq, MEMSUFFIX)(EA); |
| 411 |
u.u = ((u.u & 0xFF00000000000000ULL) >> 56) | |
| 412 |
((u.u & 0x00FF000000000000ULL) >> 40) | |
| 413 |
((u.u & 0x0000FF0000000000ULL) >> 24) | |
| 414 |
((u.u & 0x000000FF00000000ULL) >> 8) | |
| 415 |
((u.u & 0x00000000FF000000ULL) << 8) | |
| 416 |
((u.u & 0x0000000000FF0000ULL) << 24) | |
| 417 |
((u.u & 0x000000000000FF00ULL) << 40) | |
| 418 |
((u.u & 0x00000000000000FFULL) << 56); |
| 419 |
|
| 420 |
return u.d;
|
| 421 |
} |
| 422 |
|
| 423 |
void glue(do_POWER2_lfq_le, MEMSUFFIX) (void) |
| 424 |
{
|
| 425 |
FT0 = glue(ldfqr, MEMSUFFIX)((uint32_t)(T0 + 4));
|
| 426 |
FT1 = glue(ldfqr, MEMSUFFIX)((uint32_t)T0); |
| 427 |
} |
| 428 |
|
| 429 |
void glue(do_POWER2_stfq, MEMSUFFIX) (void) |
| 430 |
{
|
| 431 |
glue(stfq, MEMSUFFIX)((uint32_t)T0, FT0); |
| 432 |
glue(stfq, MEMSUFFIX)((uint32_t)(T0 + 4), FT1);
|
| 433 |
} |
| 434 |
|
| 435 |
static always_inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d) |
| 436 |
{
|
| 437 |
union {
|
| 438 |
double d;
|
| 439 |
uint64_t u; |
| 440 |
} u; |
| 441 |
|
| 442 |
u.d = d; |
| 443 |
u.u = ((u.u & 0xFF00000000000000ULL) >> 56) | |
| 444 |
((u.u & 0x00FF000000000000ULL) >> 40) | |
| 445 |
((u.u & 0x0000FF0000000000ULL) >> 24) | |
| 446 |
((u.u & 0x000000FF00000000ULL) >> 8) | |
| 447 |
((u.u & 0x00000000FF000000ULL) << 8) | |
| 448 |
((u.u & 0x0000000000FF0000ULL) << 24) | |
| 449 |
((u.u & 0x000000000000FF00ULL) << 40) | |
| 450 |
((u.u & 0x00000000000000FFULL) << 56); |
| 451 |
glue(stfq, MEMSUFFIX)(EA, u.d); |
| 452 |
} |
| 453 |
|
| 454 |
void glue(do_POWER2_stfq_le, MEMSUFFIX) (void) |
| 455 |
{
|
| 456 |
glue(stfqr, MEMSUFFIX)((uint32_t)(T0 + 4), FT0);
|
| 457 |
glue(stfqr, MEMSUFFIX)((uint32_t)T0, FT1); |
| 458 |
} |
| 459 |
|
| 460 |
#undef MEMSUFFIX
|