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1
/*
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 *  PowerPC emulation for qemu: main translation routines.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20
#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
25

    
26
#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
29

    
30
/* Include definitions for instructions classes and implementations flags */
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//#define DO_SINGLE_STEP
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//#define PPC_DEBUG_DISAS
33
//#define DEBUG_MEMORY_ACCESSES
34
//#define DO_PPC_STATISTICS
35

    
36
/*****************************************************************************/
37
/* Code translation helpers                                                  */
38
#if defined(USE_DIRECT_JUMP)
39
#define TBPARAM(x)
40
#else
41
#define TBPARAM(x) (long)(x)
42
#endif
43

    
44
enum {
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#define DEF(s, n, copy_size) INDEX_op_ ## s,
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#include "opc.h"
47
#undef DEF
48
    NB_OPS,
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};
50

    
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
53

    
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#include "gen-op.h"
55

    
56
static always_inline void gen_set_T0 (target_ulong val)
57
{
58
#if defined(TARGET_PPC64)
59
    if (val >> 32)
60
        gen_op_set_T0_64(val >> 32, val);
61
    else
62
#endif
63
        gen_op_set_T0(val);
64
}
65

    
66
static always_inline void gen_set_T1 (target_ulong val)
67
{
68
#if defined(TARGET_PPC64)
69
    if (val >> 32)
70
        gen_op_set_T1_64(val >> 32, val);
71
    else
72
#endif
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        gen_op_set_T1(val);
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}
75

    
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#define GEN8(func, NAME)                                                      \
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static GenOpFunc *NAME ## _table [8] = {                                      \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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};                                                                            \
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static always_inline void func (int n)                                        \
82
{                                                                             \
83
    NAME ## _table[n]();                                                      \
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}
85

    
86
#define GEN16(func, NAME)                                                     \
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static GenOpFunc *NAME ## _table [16] = {                                     \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
92
};                                                                            \
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static always_inline void func (int n)                                        \
94
{                                                                             \
95
    NAME ## _table[n]();                                                      \
96
}
97

    
98
#define GEN32(func, NAME)                                                     \
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static GenOpFunc *NAME ## _table [32] = {                                     \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
102
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
106
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
107
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
108
};                                                                            \
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static always_inline void func (int n)                                        \
110
{                                                                             \
111
    NAME ## _table[n]();                                                      \
112
}
113

    
114
/* Condition register moves */
115
GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
116
GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
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GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
118
GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
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120
/* Floating point condition and status register moves */
121
GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
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GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
123
GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
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static always_inline void gen_op_store_T0_fpscri (int n, uint8_t param)
125
{
126
    gen_op_set_T0(param);
127
    gen_op_store_T0_fpscr(n);
128
}
129

    
130
/* General purpose registers moves */
131
GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
132
GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
133
GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
134

    
135
GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
136
GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
137
#if 0 // unused
138
GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
139
#endif
140

    
141
/* floating point registers moves */
142
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
143
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
144
GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
145
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
146
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
147
#if 0 // unused
148
GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
149
#endif
150

    
151
/* internal defines */
152
typedef struct DisasContext {
153
    struct TranslationBlock *tb;
154
    target_ulong nip;
155
    uint32_t opcode;
156
    uint32_t exception;
157
    /* Routine used to access memory */
158
    int mem_idx;
159
    /* Translation flags */
160
#if !defined(CONFIG_USER_ONLY)
161
    int supervisor;
162
#endif
163
#if defined(TARGET_PPC64)
164
    int sf_mode;
165
#endif
166
    int fpu_enabled;
167
    int altivec_enabled;
168
#if defined(TARGET_PPCEMB)
169
    int spe_enabled;
170
#endif
171
    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
172
    int singlestep_enabled;
173
    int dcache_line_size;
174
} DisasContext;
175

    
176
struct opc_handler_t {
177
    /* invalid bits */
178
    uint32_t inval;
179
    /* instruction type */
180
    uint64_t type;
181
    /* handler */
182
    void (*handler)(DisasContext *ctx);
183
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
184
    const unsigned char *oname;
185
#endif
186
#if defined(DO_PPC_STATISTICS)
187
    uint64_t count;
188
#endif
189
};
190

    
191
static always_inline void gen_set_Rc0 (DisasContext *ctx)
192
{
193
#if defined(TARGET_PPC64)
194
    if (ctx->sf_mode)
195
        gen_op_cmpi_64(0);
196
    else
197
#endif
198
        gen_op_cmpi(0);
199
    gen_op_set_Rc0();
200
}
201

    
202
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
203
{
204
#if defined(TARGET_PPC64)
205
    if (ctx->sf_mode)
206
        gen_op_update_nip_64(nip >> 32, nip);
207
    else
208
#endif
209
        gen_op_update_nip(nip);
210
}
211

    
212
#define GEN_EXCP(ctx, excp, error)                                            \
213
do {                                                                          \
214
    if ((ctx)->exception == POWERPC_EXCP_NONE) {                              \
215
        gen_update_nip(ctx, (ctx)->nip);                                      \
216
    }                                                                         \
217
    gen_op_raise_exception_err((excp), (error));                              \
218
    ctx->exception = (excp);                                                  \
219
} while (0)
220

    
221
#define GEN_EXCP_INVAL(ctx)                                                   \
222
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
223
         POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
224

    
225
#define GEN_EXCP_PRIVOPC(ctx)                                                 \
226
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
227
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
228

    
229
#define GEN_EXCP_PRIVREG(ctx)                                                 \
230
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
231
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
232

    
233
#define GEN_EXCP_NO_FP(ctx)                                                   \
234
GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
235

    
236
#define GEN_EXCP_NO_AP(ctx)                                                   \
237
GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
238

    
239
#define GEN_EXCP_NO_VR(ctx)                                                   \
240
GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
241

    
242
/* Stop translation */
243
static always_inline void GEN_STOP (DisasContext *ctx)
244
{
245
    gen_update_nip(ctx, ctx->nip);
246
    ctx->exception = POWERPC_EXCP_STOP;
247
}
248

    
249
/* No need to update nip here, as execution flow will change */
250
static always_inline void GEN_SYNC (DisasContext *ctx)
251
{
252
    ctx->exception = POWERPC_EXCP_SYNC;
253
}
254

    
255
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
256
static void gen_##name (DisasContext *ctx);                                   \
257
GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
258
static void gen_##name (DisasContext *ctx)
259

    
260
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
261
static void gen_##name (DisasContext *ctx);                                   \
262
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \
263
static void gen_##name (DisasContext *ctx)
264

    
265

    
266
typedef struct opcode_t {
267
    unsigned char opc1, opc2, opc3;
268
#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
269
    unsigned char pad[5];
270
#else
271
    unsigned char pad[1];
272
#endif
273
    opc_handler_t handler;
274
    const unsigned char *oname;
275
} opcode_t;
276

    
277
/*****************************************************************************/
278
/***                           Instruction decoding                        ***/
279
#define EXTRACT_HELPER(name, shift, nb)                                       \
280
static always_inline uint32_t name (uint32_t opcode)                          \
281
{                                                                             \
282
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
283
}
284

    
285
#define EXTRACT_SHELPER(name, shift, nb)                                      \
286
static always_inline int32_t name (uint32_t opcode)                           \
287
{                                                                             \
288
    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
289
}
290

    
291
/* Opcode part 1 */
292
EXTRACT_HELPER(opc1, 26, 6);
293
/* Opcode part 2 */
294
EXTRACT_HELPER(opc2, 1, 5);
295
/* Opcode part 3 */
296
EXTRACT_HELPER(opc3, 6, 5);
297
/* Update Cr0 flags */
298
EXTRACT_HELPER(Rc, 0, 1);
299
/* Destination */
300
EXTRACT_HELPER(rD, 21, 5);
301
/* Source */
302
EXTRACT_HELPER(rS, 21, 5);
303
/* First operand */
304
EXTRACT_HELPER(rA, 16, 5);
305
/* Second operand */
306
EXTRACT_HELPER(rB, 11, 5);
307
/* Third operand */
308
EXTRACT_HELPER(rC, 6, 5);
309
/***                               Get CRn                                 ***/
310
EXTRACT_HELPER(crfD, 23, 3);
311
EXTRACT_HELPER(crfS, 18, 3);
312
EXTRACT_HELPER(crbD, 21, 5);
313
EXTRACT_HELPER(crbA, 16, 5);
314
EXTRACT_HELPER(crbB, 11, 5);
315
/* SPR / TBL */
316
EXTRACT_HELPER(_SPR, 11, 10);
317
static always_inline uint32_t SPR (uint32_t opcode)
318
{
319
    uint32_t sprn = _SPR(opcode);
320

    
321
    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
322
}
323
/***                              Get constants                            ***/
324
EXTRACT_HELPER(IMM, 12, 8);
325
/* 16 bits signed immediate value */
326
EXTRACT_SHELPER(SIMM, 0, 16);
327
/* 16 bits unsigned immediate value */
328
EXTRACT_HELPER(UIMM, 0, 16);
329
/* Bit count */
330
EXTRACT_HELPER(NB, 11, 5);
331
/* Shift count */
332
EXTRACT_HELPER(SH, 11, 5);
333
/* Mask start */
334
EXTRACT_HELPER(MB, 6, 5);
335
/* Mask end */
336
EXTRACT_HELPER(ME, 1, 5);
337
/* Trap operand */
338
EXTRACT_HELPER(TO, 21, 5);
339

    
340
EXTRACT_HELPER(CRM, 12, 8);
341
EXTRACT_HELPER(FM, 17, 8);
342
EXTRACT_HELPER(SR, 16, 4);
343
EXTRACT_HELPER(FPIMM, 20, 4);
344

    
345
/***                            Jump target decoding                       ***/
346
/* Displacement */
347
EXTRACT_SHELPER(d, 0, 16);
348
/* Immediate address */
349
static always_inline target_ulong LI (uint32_t opcode)
350
{
351
    return (opcode >> 0) & 0x03FFFFFC;
352
}
353

    
354
static always_inline uint32_t BD (uint32_t opcode)
355
{
356
    return (opcode >> 0) & 0xFFFC;
357
}
358

    
359
EXTRACT_HELPER(BO, 21, 5);
360
EXTRACT_HELPER(BI, 16, 5);
361
/* Absolute/relative address */
362
EXTRACT_HELPER(AA, 1, 1);
363
/* Link */
364
EXTRACT_HELPER(LK, 0, 1);
365

    
366
/* Create a mask between <start> and <end> bits */
367
static always_inline target_ulong MASK (uint32_t start, uint32_t end)
368
{
369
    target_ulong ret;
370

    
371
#if defined(TARGET_PPC64)
372
    if (likely(start == 0)) {
373
        ret = (uint64_t)(-1ULL) << (63 - end);
374
    } else if (likely(end == 63)) {
375
        ret = (uint64_t)(-1ULL) >> start;
376
    }
377
#else
378
    if (likely(start == 0)) {
379
        ret = (uint32_t)(-1ULL) << (31  - end);
380
    } else if (likely(end == 31)) {
381
        ret = (uint32_t)(-1ULL) >> start;
382
    }
383
#endif
384
    else {
385
        ret = (((target_ulong)(-1ULL)) >> (start)) ^
386
            (((target_ulong)(-1ULL) >> (end)) >> 1);
387
        if (unlikely(start > end))
388
            return ~ret;
389
    }
390

    
391
    return ret;
392
}
393

    
394
/*****************************************************************************/
395
/* PowerPC Instructions types definitions                                    */
396
enum {
397
    PPC_NONE          = 0x0000000000000000ULL,
398
    /* PowerPC base instructions set                                         */
399
    PPC_INSNS_BASE    = 0x0000000000000001ULL,
400
    /* integer operations instructions                                       */
401
#define PPC_INTEGER PPC_INSNS_BASE
402
    /* flow control instructions                                             */
403
#define PPC_FLOW    PPC_INSNS_BASE
404
    /* virtual memory instructions                                           */
405
#define PPC_MEM     PPC_INSNS_BASE
406
    /* ld/st with reservation instructions                                   */
407
#define PPC_RES     PPC_INSNS_BASE
408
    /* cache control instructions                                            */
409
#define PPC_CACHE   PPC_INSNS_BASE
410
    /* spr/msr access instructions                                           */
411
#define PPC_MISC    PPC_INSNS_BASE
412
    /* Optional floating point instructions                                  */
413
    PPC_FLOAT         = 0x0000000000000002ULL,
414
    PPC_FLOAT_FSQRT   = 0x0000000000000004ULL,
415
    PPC_FLOAT_FRES    = 0x0000000000000008ULL,
416
    PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL,
417
    PPC_FLOAT_FSEL    = 0x0000000000000020ULL,
418
    PPC_FLOAT_STFIWX  = 0x0000000000000040ULL,
419
    /* external control instructions                                         */
420
    PPC_EXTERN        = 0x0000000000000080ULL,
421
    /* segment register access instructions                                  */
422
    PPC_SEGMENT       = 0x0000000000000100ULL,
423
    /* Optional cache control instruction                                    */
424
    PPC_CACHE_DCBA    = 0x0000000000000200ULL,
425
    /* Optional memory control instructions                                  */
426
    PPC_MEM_TLBIA     = 0x0000000000000400ULL,
427
    PPC_MEM_TLBIE     = 0x0000000000000800ULL,
428
    PPC_MEM_TLBSYNC   = 0x0000000000001000ULL,
429
    /* eieio & sync                                                          */
430
    PPC_MEM_SYNC      = 0x0000000000002000ULL,
431
    /* PowerPC 6xx TLB management instructions                               */
432
    PPC_6xx_TLB       = 0x0000000000004000ULL,
433
    /* Altivec support                                                       */
434
    PPC_ALTIVEC       = 0x0000000000008000ULL,
435
    /* Time base mftb instruction                                            */
436
    PPC_MFTB          = 0x0000000000010000ULL,
437
    /* Embedded PowerPC dedicated instructions                               */
438
    PPC_EMB_COMMON    = 0x0000000000020000ULL,
439
    /* PowerPC 40x exception model                                           */
440
    PPC_40x_EXCP      = 0x0000000000040000ULL,
441
    /* PowerPC 40x TLB management instructions                               */
442
    PPC_40x_TLB       = 0x0000000000080000ULL,
443
    /* PowerPC 405 Mac instructions                                          */
444
    PPC_405_MAC       = 0x0000000000100000ULL,
445
    /* PowerPC 440 specific instructions                                     */
446
    PPC_440_SPEC      = 0x0000000000200000ULL,
447
    /* Power-to-PowerPC bridge (601)                                         */
448
    PPC_POWER_BR      = 0x0000000000400000ULL,
449
    /* PowerPC 602 specific                                                  */
450
    PPC_602_SPEC      = 0x0000000000800000ULL,
451
    /* Deprecated instructions                                               */
452
    /* Original POWER instruction set                                        */
453
    PPC_POWER         = 0x0000000001000000ULL,
454
    /* POWER2 instruction set extension                                      */
455
    PPC_POWER2        = 0x0000000002000000ULL,
456
    /* Power RTC support                                                     */
457
    PPC_POWER_RTC     = 0x0000000004000000ULL,
458
    /* 64 bits PowerPC instruction set                                       */
459
    PPC_64B           = 0x0000000008000000ULL,
460
    /* 64 bits hypervisor extensions                                         */
461
    PPC_64H           = 0x0000000010000000ULL,
462
    /* segment register access instructions for PowerPC 64 "bridge"          */
463
    PPC_SEGMENT_64B   = 0x0000000020000000ULL,
464
    /* BookE (embedded) PowerPC specification                                */
465
    PPC_BOOKE         = 0x0000000040000000ULL,
466
    /* eieio                                                                 */
467
    PPC_MEM_EIEIO     = 0x0000000080000000ULL,
468
    /* e500 vector instructions                                              */
469
    PPC_E500_VECTOR   = 0x0000000100000000ULL,
470
    /* PowerPC 4xx dedicated instructions                                    */
471
    PPC_4xx_COMMON    = 0x0000000200000000ULL,
472
    /* PowerPC 2.03 specification extensions                                 */
473
    PPC_203           = 0x0000000400000000ULL,
474
    /* PowerPC 2.03 SPE extension                                            */
475
    PPC_SPE           = 0x0000000800000000ULL,
476
    /* PowerPC 2.03 SPE floating-point extension                             */
477
    PPC_SPEFPU        = 0x0000001000000000ULL,
478
    /* SLB management                                                        */
479
    PPC_SLBI          = 0x0000002000000000ULL,
480
    /* PowerPC 40x ibct instructions                                         */
481
    PPC_40x_ICBT      = 0x0000004000000000ULL,
482
    /* PowerPC 74xx TLB management instructions                              */
483
    PPC_74xx_TLB      = 0x0000008000000000ULL,
484
    /* More BookE (embedded) instructions...                                 */
485
    PPC_BOOKE_EXT     = 0x0000010000000000ULL,
486
    /* rfmci is not implemented in all BookE PowerPC                         */
487
    PPC_RFMCI         = 0x0000020000000000ULL,
488
    /* user-mode DCR access, implemented in PowerPC 460                      */
489
    PPC_DCRUX         = 0x0000040000000000ULL,
490
    /* New floating-point extensions (PowerPC 2.0x)                          */
491
    PPC_FLOAT_EXT     = 0x0000080000000000ULL,
492
    /* New wait instruction (PowerPC 2.0x)                                   */
493
    PPC_WAIT          = 0x0000100000000000ULL,
494
    /* New 64 bits extensions (PowerPC 2.0x)                                 */
495
    PPC_64BX          = 0x0000200000000000ULL,
496
    /* dcbz instruction with fixed cache line size                           */
497
    PPC_CACHE_DCBZ    = 0x0000400000000000ULL,
498
    /* dcbz instruction with tunable cache line size                         */
499
    PPC_CACHE_DCBZT   = 0x0000800000000000ULL,
500
};
501

    
502
/*****************************************************************************/
503
/* PowerPC instructions table                                                */
504
#if HOST_LONG_BITS == 64
505
#define OPC_ALIGN 8
506
#else
507
#define OPC_ALIGN 4
508
#endif
509
#if defined(__APPLE__)
510
#define OPCODES_SECTION                                                       \
511
    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
512
#else
513
#define OPCODES_SECTION                                                       \
514
    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
515
#endif
516

    
517
#if defined(DO_PPC_STATISTICS)
518
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
519
OPCODES_SECTION opcode_t opc_##name = {                                       \
520
    .opc1 = op1,                                                              \
521
    .opc2 = op2,                                                              \
522
    .opc3 = op3,                                                              \
523
    .pad  = { 0, },                                                           \
524
    .handler = {                                                              \
525
        .inval   = invl,                                                      \
526
        .type = _typ,                                                         \
527
        .handler = &gen_##name,                                               \
528
        .oname = stringify(name),                                             \
529
    },                                                                        \
530
    .oname = stringify(name),                                                 \
531
}
532
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
533
OPCODES_SECTION opcode_t opc_##name = {                                       \
534
    .opc1 = op1,                                                              \
535
    .opc2 = op2,                                                              \
536
    .opc3 = op3,                                                              \
537
    .pad  = { 0, },                                                           \
538
    .handler = {                                                              \
539
        .inval   = invl,                                                      \
540
        .type = _typ,                                                         \
541
        .handler = &gen_##name,                                               \
542
        .oname = onam,                                                        \
543
    },                                                                        \
544
    .oname = onam,                                                            \
545
}
546
#else
547
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
548
OPCODES_SECTION opcode_t opc_##name = {                                       \
549
    .opc1 = op1,                                                              \
550
    .opc2 = op2,                                                              \
551
    .opc3 = op3,                                                              \
552
    .pad  = { 0, },                                                           \
553
    .handler = {                                                              \
554
        .inval   = invl,                                                      \
555
        .type = _typ,                                                         \
556
        .handler = &gen_##name,                                               \
557
    },                                                                        \
558
    .oname = stringify(name),                                                 \
559
}
560
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
561
OPCODES_SECTION opcode_t opc_##name = {                                       \
562
    .opc1 = op1,                                                              \
563
    .opc2 = op2,                                                              \
564
    .opc3 = op3,                                                              \
565
    .pad  = { 0, },                                                           \
566
    .handler = {                                                              \
567
        .inval   = invl,                                                      \
568
        .type = _typ,                                                         \
569
        .handler = &gen_##name,                                               \
570
    },                                                                        \
571
    .oname = onam,                                                            \
572
}
573
#endif
574

    
575
#define GEN_OPCODE_MARK(name)                                                 \
576
OPCODES_SECTION opcode_t opc_##name = {                                       \
577
    .opc1 = 0xFF,                                                             \
578
    .opc2 = 0xFF,                                                             \
579
    .opc3 = 0xFF,                                                             \
580
    .pad  = { 0, },                                                           \
581
    .handler = {                                                              \
582
        .inval   = 0x00000000,                                                \
583
        .type = 0x00,                                                         \
584
        .handler = NULL,                                                      \
585
    },                                                                        \
586
    .oname = stringify(name),                                                 \
587
}
588

    
589
/* Start opcode list */
590
GEN_OPCODE_MARK(start);
591

    
592
/* Invalid instruction */
593
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
594
{
595
    GEN_EXCP_INVAL(ctx);
596
}
597

    
598
static opc_handler_t invalid_handler = {
599
    .inval   = 0xFFFFFFFF,
600
    .type    = PPC_NONE,
601
    .handler = gen_invalid,
602
};
603

    
604
/***                           Integer arithmetic                          ***/
605
#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type)                 \
606
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
607
{                                                                             \
608
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
609
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
610
    gen_op_##name();                                                          \
611
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
612
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
613
        gen_set_Rc0(ctx);                                                     \
614
}
615

    
616
#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type)               \
617
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
618
{                                                                             \
619
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
620
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
621
    gen_op_##name();                                                          \
622
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
623
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
624
        gen_set_Rc0(ctx);                                                     \
625
}
626

    
627
#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                        \
628
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
629
{                                                                             \
630
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
631
    gen_op_##name();                                                          \
632
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
633
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
634
        gen_set_Rc0(ctx);                                                     \
635
}
636
#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type)                      \
637
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
638
{                                                                             \
639
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
640
    gen_op_##name();                                                          \
641
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
642
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
643
        gen_set_Rc0(ctx);                                                     \
644
}
645

    
646
/* Two operands arithmetic functions */
647
#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type)                          \
648
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type)                    \
649
__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
650

    
651
/* Two operands arithmetic functions with no overflow allowed */
652
#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type)                          \
653
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
654

    
655
/* One operand arithmetic functions */
656
#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                          \
657
__GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                                \
658
__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
659

    
660
#if defined(TARGET_PPC64)
661
#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type)              \
662
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
663
{                                                                             \
664
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
665
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
666
    if (ctx->sf_mode)                                                         \
667
        gen_op_##name##_64();                                                 \
668
    else                                                                      \
669
        gen_op_##name();                                                      \
670
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
671
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
672
        gen_set_Rc0(ctx);                                                     \
673
}
674

    
675
#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type)            \
676
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
677
{                                                                             \
678
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
679
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
680
    if (ctx->sf_mode)                                                         \
681
        gen_op_##name##_64();                                                 \
682
    else                                                                      \
683
        gen_op_##name();                                                      \
684
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
685
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
686
        gen_set_Rc0(ctx);                                                     \
687
}
688

    
689
#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                     \
690
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
691
{                                                                             \
692
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
693
    if (ctx->sf_mode)                                                         \
694
        gen_op_##name##_64();                                                 \
695
    else                                                                      \
696
        gen_op_##name();                                                      \
697
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
698
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
699
        gen_set_Rc0(ctx);                                                     \
700
}
701
#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type)                   \
702
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
703
{                                                                             \
704
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
705
    if (ctx->sf_mode)                                                         \
706
        gen_op_##name##_64();                                                 \
707
    else                                                                      \
708
        gen_op_##name();                                                      \
709
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
710
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
711
        gen_set_Rc0(ctx);                                                     \
712
}
713

    
714
/* Two operands arithmetic functions */
715
#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type)                       \
716
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type)                 \
717
__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
718

    
719
/* Two operands arithmetic functions with no overflow allowed */
720
#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type)                       \
721
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
722

    
723
/* One operand arithmetic functions */
724
#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                       \
725
__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                             \
726
__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
727
#else
728
#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
729
#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
730
#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
731
#endif
732

    
733
/* add    add.    addo    addo.    */
734
static always_inline void gen_op_addo (void)
735
{
736
    gen_op_move_T2_T0();
737
    gen_op_add();
738
    gen_op_check_addo();
739
}
740
#if defined(TARGET_PPC64)
741
#define gen_op_add_64 gen_op_add
742
static always_inline void gen_op_addo_64 (void)
743
{
744
    gen_op_move_T2_T0();
745
    gen_op_add();
746
    gen_op_check_addo_64();
747
}
748
#endif
749
GEN_INT_ARITH2_64 (add,    0x1F, 0x0A, 0x08, PPC_INTEGER);
750
/* addc   addc.   addco   addco.   */
751
static always_inline void gen_op_addc (void)
752
{
753
    gen_op_move_T2_T0();
754
    gen_op_add();
755
    gen_op_check_addc();
756
}
757
static always_inline void gen_op_addco (void)
758
{
759
    gen_op_move_T2_T0();
760
    gen_op_add();
761
    gen_op_check_addc();
762
    gen_op_check_addo();
763
}
764
#if defined(TARGET_PPC64)
765
static always_inline void gen_op_addc_64 (void)
766
{
767
    gen_op_move_T2_T0();
768
    gen_op_add();
769
    gen_op_check_addc_64();
770
}
771
static always_inline void gen_op_addco_64 (void)
772
{
773
    gen_op_move_T2_T0();
774
    gen_op_add();
775
    gen_op_check_addc_64();
776
    gen_op_check_addo_64();
777
}
778
#endif
779
GEN_INT_ARITH2_64 (addc,   0x1F, 0x0A, 0x00, PPC_INTEGER);
780
/* adde   adde.   addeo   addeo.   */
781
static always_inline void gen_op_addeo (void)
782
{
783
    gen_op_move_T2_T0();
784
    gen_op_adde();
785
    gen_op_check_addo();
786
}
787
#if defined(TARGET_PPC64)
788
static always_inline void gen_op_addeo_64 (void)
789
{
790
    gen_op_move_T2_T0();
791
    gen_op_adde_64();
792
    gen_op_check_addo_64();
793
}
794
#endif
795
GEN_INT_ARITH2_64 (adde,   0x1F, 0x0A, 0x04, PPC_INTEGER);
796
/* addme  addme.  addmeo  addmeo.  */
797
static always_inline void gen_op_addme (void)
798
{
799
    gen_op_move_T1_T0();
800
    gen_op_add_me();
801
}
802
#if defined(TARGET_PPC64)
803
static always_inline void gen_op_addme_64 (void)
804
{
805
    gen_op_move_T1_T0();
806
    gen_op_add_me_64();
807
}
808
#endif
809
GEN_INT_ARITH1_64 (addme,  0x1F, 0x0A, 0x07, PPC_INTEGER);
810
/* addze  addze.  addzeo  addzeo.  */
811
static always_inline void gen_op_addze (void)
812
{
813
    gen_op_move_T2_T0();
814
    gen_op_add_ze();
815
    gen_op_check_addc();
816
}
817
static always_inline void gen_op_addzeo (void)
818
{
819
    gen_op_move_T2_T0();
820
    gen_op_add_ze();
821
    gen_op_check_addc();
822
    gen_op_check_addo();
823
}
824
#if defined(TARGET_PPC64)
825
static always_inline void gen_op_addze_64 (void)
826
{
827
    gen_op_move_T2_T0();
828
    gen_op_add_ze();
829
    gen_op_check_addc_64();
830
}
831
static always_inline void gen_op_addzeo_64 (void)
832
{
833
    gen_op_move_T2_T0();
834
    gen_op_add_ze();
835
    gen_op_check_addc_64();
836
    gen_op_check_addo_64();
837
}
838
#endif
839
GEN_INT_ARITH1_64 (addze,  0x1F, 0x0A, 0x06, PPC_INTEGER);
840
/* divw   divw.   divwo   divwo.   */
841
GEN_INT_ARITH2 (divw,   0x1F, 0x0B, 0x0F, PPC_INTEGER);
842
/* divwu  divwu.  divwuo  divwuo.  */
843
GEN_INT_ARITH2 (divwu,  0x1F, 0x0B, 0x0E, PPC_INTEGER);
844
/* mulhw  mulhw.                   */
845
GEN_INT_ARITHN (mulhw,  0x1F, 0x0B, 0x02, PPC_INTEGER);
846
/* mulhwu mulhwu.                  */
847
GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
848
/* mullw  mullw.  mullwo  mullwo.  */
849
GEN_INT_ARITH2 (mullw,  0x1F, 0x0B, 0x07, PPC_INTEGER);
850
/* neg    neg.    nego    nego.    */
851
GEN_INT_ARITH1_64 (neg,    0x1F, 0x08, 0x03, PPC_INTEGER);
852
/* subf   subf.   subfo   subfo.   */
853
static always_inline void gen_op_subfo (void)
854
{
855
    gen_op_move_T2_T0();
856
    gen_op_subf();
857
    gen_op_check_subfo();
858
}
859
#if defined(TARGET_PPC64)
860
#define gen_op_subf_64 gen_op_subf
861
static always_inline void gen_op_subfo_64 (void)
862
{
863
    gen_op_move_T2_T0();
864
    gen_op_subf();
865
    gen_op_check_subfo_64();
866
}
867
#endif
868
GEN_INT_ARITH2_64 (subf,   0x1F, 0x08, 0x01, PPC_INTEGER);
869
/* subfc  subfc.  subfco  subfco.  */
870
static always_inline void gen_op_subfc (void)
871
{
872
    gen_op_subf();
873
    gen_op_check_subfc();
874
}
875
static always_inline void gen_op_subfco (void)
876
{
877
    gen_op_move_T2_T0();
878
    gen_op_subf();
879
    gen_op_check_subfc();
880
    gen_op_check_subfo();
881
}
882
#if defined(TARGET_PPC64)
883
static always_inline void gen_op_subfc_64 (void)
884
{
885
    gen_op_subf();
886
    gen_op_check_subfc_64();
887
}
888
static always_inline void gen_op_subfco_64 (void)
889
{
890
    gen_op_move_T2_T0();
891
    gen_op_subf();
892
    gen_op_check_subfc_64();
893
    gen_op_check_subfo_64();
894
}
895
#endif
896
GEN_INT_ARITH2_64 (subfc,  0x1F, 0x08, 0x00, PPC_INTEGER);
897
/* subfe  subfe.  subfeo  subfeo.  */
898
static always_inline void gen_op_subfeo (void)
899
{
900
    gen_op_move_T2_T0();
901
    gen_op_subfe();
902
    gen_op_check_subfo();
903
}
904
#if defined(TARGET_PPC64)
905
#define gen_op_subfe_64 gen_op_subfe
906
static always_inline void gen_op_subfeo_64 (void)
907
{
908
    gen_op_move_T2_T0();
909
    gen_op_subfe_64();
910
    gen_op_check_subfo_64();
911
}
912
#endif
913
GEN_INT_ARITH2_64 (subfe,  0x1F, 0x08, 0x04, PPC_INTEGER);
914
/* subfme subfme. subfmeo subfmeo. */
915
GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
916
/* subfze subfze. subfzeo subfzeo. */
917
GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
918
/* addi */
919
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
920
{
921
    target_long simm = SIMM(ctx->opcode);
922

    
923
    if (rA(ctx->opcode) == 0) {
924
        /* li case */
925
        gen_set_T0(simm);
926
    } else {
927
        gen_op_load_gpr_T0(rA(ctx->opcode));
928
        if (likely(simm != 0))
929
            gen_op_addi(simm);
930
    }
931
    gen_op_store_T0_gpr(rD(ctx->opcode));
932
}
933
/* addic */
934
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
935
{
936
    target_long simm = SIMM(ctx->opcode);
937

    
938
    gen_op_load_gpr_T0(rA(ctx->opcode));
939
    if (likely(simm != 0)) {
940
        gen_op_move_T2_T0();
941
        gen_op_addi(simm);
942
#if defined(TARGET_PPC64)
943
        if (ctx->sf_mode)
944
            gen_op_check_addc_64();
945
        else
946
#endif
947
            gen_op_check_addc();
948
    } else {
949
        gen_op_clear_xer_ca();
950
    }
951
    gen_op_store_T0_gpr(rD(ctx->opcode));
952
}
953
/* addic. */
954
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
955
{
956
    target_long simm = SIMM(ctx->opcode);
957

    
958
    gen_op_load_gpr_T0(rA(ctx->opcode));
959
    if (likely(simm != 0)) {
960
        gen_op_move_T2_T0();
961
        gen_op_addi(simm);
962
#if defined(TARGET_PPC64)
963
        if (ctx->sf_mode)
964
            gen_op_check_addc_64();
965
        else
966
#endif
967
            gen_op_check_addc();
968
    } else {
969
        gen_op_clear_xer_ca();
970
    }
971
    gen_op_store_T0_gpr(rD(ctx->opcode));
972
    gen_set_Rc0(ctx);
973
}
974
/* addis */
975
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
976
{
977
    target_long simm = SIMM(ctx->opcode);
978

    
979
    if (rA(ctx->opcode) == 0) {
980
        /* lis case */
981
        gen_set_T0(simm << 16);
982
    } else {
983
        gen_op_load_gpr_T0(rA(ctx->opcode));
984
        if (likely(simm != 0))
985
            gen_op_addi(simm << 16);
986
    }
987
    gen_op_store_T0_gpr(rD(ctx->opcode));
988
}
989
/* mulli */
990
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
991
{
992
    gen_op_load_gpr_T0(rA(ctx->opcode));
993
    gen_op_mulli(SIMM(ctx->opcode));
994
    gen_op_store_T0_gpr(rD(ctx->opcode));
995
}
996
/* subfic */
997
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
998
{
999
    gen_op_load_gpr_T0(rA(ctx->opcode));
1000
#if defined(TARGET_PPC64)
1001
    if (ctx->sf_mode)
1002
        gen_op_subfic_64(SIMM(ctx->opcode));
1003
    else
1004
#endif
1005
        gen_op_subfic(SIMM(ctx->opcode));
1006
    gen_op_store_T0_gpr(rD(ctx->opcode));
1007
}
1008

    
1009
#if defined(TARGET_PPC64)
1010
/* mulhd  mulhd.                   */
1011
GEN_INT_ARITHN (mulhd,  0x1F, 0x09, 0x02, PPC_64B);
1012
/* mulhdu mulhdu.                  */
1013
GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
1014
/* mulld  mulld.  mulldo  mulldo.  */
1015
GEN_INT_ARITH2 (mulld,  0x1F, 0x09, 0x07, PPC_64B);
1016
/* divd   divd.   divdo   divdo.   */
1017
GEN_INT_ARITH2 (divd,   0x1F, 0x09, 0x0F, PPC_64B);
1018
/* divdu  divdu.  divduo  divduo.  */
1019
GEN_INT_ARITH2 (divdu,  0x1F, 0x09, 0x0E, PPC_64B);
1020
#endif
1021

    
1022
/***                           Integer comparison                          ***/
1023
#if defined(TARGET_PPC64)
1024
#define GEN_CMP(name, opc, type)                                              \
1025
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1026
{                                                                             \
1027
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1028
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1029
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))                           \
1030
        gen_op_##name##_64();                                                 \
1031
    else                                                                      \
1032
        gen_op_##name();                                                      \
1033
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
1034
}
1035
#else
1036
#define GEN_CMP(name, opc, type)                                              \
1037
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1038
{                                                                             \
1039
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1040
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1041
    gen_op_##name();                                                          \
1042
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
1043
}
1044
#endif
1045

    
1046
/* cmp */
1047
GEN_CMP(cmp, 0x00, PPC_INTEGER);
1048
/* cmpi */
1049
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1050
{
1051
    gen_op_load_gpr_T0(rA(ctx->opcode));
1052
#if defined(TARGET_PPC64)
1053
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1054
        gen_op_cmpi_64(SIMM(ctx->opcode));
1055
    else
1056
#endif
1057
        gen_op_cmpi(SIMM(ctx->opcode));
1058
    gen_op_store_T0_crf(crfD(ctx->opcode));
1059
}
1060
/* cmpl */
1061
GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1062
/* cmpli */
1063
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1064
{
1065
    gen_op_load_gpr_T0(rA(ctx->opcode));
1066
#if defined(TARGET_PPC64)
1067
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1068
        gen_op_cmpli_64(UIMM(ctx->opcode));
1069
    else
1070
#endif
1071
        gen_op_cmpli(UIMM(ctx->opcode));
1072
    gen_op_store_T0_crf(crfD(ctx->opcode));
1073
}
1074

    
1075
/* isel (PowerPC 2.03 specification) */
1076
GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
1077
{
1078
    uint32_t bi = rC(ctx->opcode);
1079
    uint32_t mask;
1080

    
1081
    if (rA(ctx->opcode) == 0) {
1082
        gen_set_T0(0);
1083
    } else {
1084
        gen_op_load_gpr_T1(rA(ctx->opcode));
1085
    }
1086
    gen_op_load_gpr_T2(rB(ctx->opcode));
1087
    mask = 1 << (3 - (bi & 0x03));
1088
    gen_op_load_crf_T0(bi >> 2);
1089
    gen_op_test_true(mask);
1090
    gen_op_isel();
1091
    gen_op_store_T0_gpr(rD(ctx->opcode));
1092
}
1093

    
1094
/***                            Integer logical                            ***/
1095
#define __GEN_LOGICAL2(name, opc2, opc3, type)                                \
1096
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type)                         \
1097
{                                                                             \
1098
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
1099
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1100
    gen_op_##name();                                                          \
1101
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1102
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1103
        gen_set_Rc0(ctx);                                                     \
1104
}
1105
#define GEN_LOGICAL2(name, opc, type)                                         \
1106
__GEN_LOGICAL2(name, 0x1C, opc, type)
1107

    
1108
#define GEN_LOGICAL1(name, opc, type)                                         \
1109
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)                          \
1110
{                                                                             \
1111
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
1112
    gen_op_##name();                                                          \
1113
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1114
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1115
        gen_set_Rc0(ctx);                                                     \
1116
}
1117

    
1118
/* and & and. */
1119
GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1120
/* andc & andc. */
1121
GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1122
/* andi. */
1123
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1124
{
1125
    gen_op_load_gpr_T0(rS(ctx->opcode));
1126
    gen_op_andi_T0(UIMM(ctx->opcode));
1127
    gen_op_store_T0_gpr(rA(ctx->opcode));
1128
    gen_set_Rc0(ctx);
1129
}
1130
/* andis. */
1131
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1132
{
1133
    gen_op_load_gpr_T0(rS(ctx->opcode));
1134
    gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1135
    gen_op_store_T0_gpr(rA(ctx->opcode));
1136
    gen_set_Rc0(ctx);
1137
}
1138

    
1139
/* cntlzw */
1140
GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1141
/* eqv & eqv. */
1142
GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1143
/* extsb & extsb. */
1144
GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1145
/* extsh & extsh. */
1146
GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1147
/* nand & nand. */
1148
GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1149
/* nor & nor. */
1150
GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1151

    
1152
/* or & or. */
1153
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1154
{
1155
    int rs, ra, rb;
1156

    
1157
    rs = rS(ctx->opcode);
1158
    ra = rA(ctx->opcode);
1159
    rb = rB(ctx->opcode);
1160
    /* Optimisation for mr. ri case */
1161
    if (rs != ra || rs != rb) {
1162
        gen_op_load_gpr_T0(rs);
1163
        if (rs != rb) {
1164
            gen_op_load_gpr_T1(rb);
1165
            gen_op_or();
1166
        }
1167
        gen_op_store_T0_gpr(ra);
1168
        if (unlikely(Rc(ctx->opcode) != 0))
1169
            gen_set_Rc0(ctx);
1170
    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1171
        gen_op_load_gpr_T0(rs);
1172
        gen_set_Rc0(ctx);
1173
#if defined(TARGET_PPC64)
1174
    } else {
1175
        switch (rs) {
1176
        case 1:
1177
            /* Set process priority to low */
1178
            gen_op_store_pri(2);
1179
            break;
1180
        case 6:
1181
            /* Set process priority to medium-low */
1182
            gen_op_store_pri(3);
1183
            break;
1184
        case 2:
1185
            /* Set process priority to normal */
1186
            gen_op_store_pri(4);
1187
            break;
1188
#if !defined(CONFIG_USER_ONLY)
1189
        case 31:
1190
            if (ctx->supervisor > 0) {
1191
                /* Set process priority to very low */
1192
                gen_op_store_pri(1);
1193
            }
1194
            break;
1195
        case 5:
1196
            if (ctx->supervisor > 0) {
1197
                /* Set process priority to medium-hight */
1198
                gen_op_store_pri(5);
1199
            }
1200
            break;
1201
        case 3:
1202
            if (ctx->supervisor > 0) {
1203
                /* Set process priority to high */
1204
                gen_op_store_pri(6);
1205
            }
1206
            break;
1207
#if defined(TARGET_PPC64H)
1208
        case 7:
1209
            if (ctx->supervisor > 1) {
1210
                /* Set process priority to very high */
1211
                gen_op_store_pri(7);
1212
            }
1213
            break;
1214
#endif
1215
#endif
1216
        default:
1217
            /* nop */
1218
            break;
1219
        }
1220
#endif
1221
    }
1222
}
1223

    
1224
/* orc & orc. */
1225
GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1226
/* xor & xor. */
1227
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1228
{
1229
    gen_op_load_gpr_T0(rS(ctx->opcode));
1230
    /* Optimisation for "set to zero" case */
1231
    if (rS(ctx->opcode) != rB(ctx->opcode)) {
1232
        gen_op_load_gpr_T1(rB(ctx->opcode));
1233
        gen_op_xor();
1234
    } else {
1235
        gen_op_reset_T0();
1236
    }
1237
    gen_op_store_T0_gpr(rA(ctx->opcode));
1238
    if (unlikely(Rc(ctx->opcode) != 0))
1239
        gen_set_Rc0(ctx);
1240
}
1241
/* ori */
1242
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1243
{
1244
    target_ulong uimm = UIMM(ctx->opcode);
1245

    
1246
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1247
        /* NOP */
1248
        /* XXX: should handle special NOPs for POWER series */
1249
        return;
1250
    }
1251
    gen_op_load_gpr_T0(rS(ctx->opcode));
1252
    if (likely(uimm != 0))
1253
        gen_op_ori(uimm);
1254
    gen_op_store_T0_gpr(rA(ctx->opcode));
1255
}
1256
/* oris */
1257
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1258
{
1259
    target_ulong uimm = UIMM(ctx->opcode);
1260

    
1261
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1262
        /* NOP */
1263
        return;
1264
    }
1265
    gen_op_load_gpr_T0(rS(ctx->opcode));
1266
    if (likely(uimm != 0))
1267
        gen_op_ori(uimm << 16);
1268
    gen_op_store_T0_gpr(rA(ctx->opcode));
1269
}
1270
/* xori */
1271
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1272
{
1273
    target_ulong uimm = UIMM(ctx->opcode);
1274

    
1275
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1276
        /* NOP */
1277
        return;
1278
    }
1279
    gen_op_load_gpr_T0(rS(ctx->opcode));
1280
    if (likely(uimm != 0))
1281
        gen_op_xori(uimm);
1282
    gen_op_store_T0_gpr(rA(ctx->opcode));
1283
}
1284

    
1285
/* xoris */
1286
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1287
{
1288
    target_ulong uimm = UIMM(ctx->opcode);
1289

    
1290
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1291
        /* NOP */
1292
        return;
1293
    }
1294
    gen_op_load_gpr_T0(rS(ctx->opcode));
1295
    if (likely(uimm != 0))
1296
        gen_op_xori(uimm << 16);
1297
    gen_op_store_T0_gpr(rA(ctx->opcode));
1298
}
1299

    
1300
/* popcntb : PowerPC 2.03 specification */
1301
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
1302
{
1303
    gen_op_load_gpr_T0(rS(ctx->opcode));
1304
#if defined(TARGET_PPC64)
1305
    if (ctx->sf_mode)
1306
        gen_op_popcntb_64();
1307
    else
1308
#endif
1309
        gen_op_popcntb();
1310
    gen_op_store_T0_gpr(rA(ctx->opcode));
1311
}
1312

    
1313
#if defined(TARGET_PPC64)
1314
/* extsw & extsw. */
1315
GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1316
/* cntlzd */
1317
GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1318
#endif
1319

    
1320
/***                             Integer rotate                            ***/
1321
/* rlwimi & rlwimi. */
1322
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1323
{
1324
    target_ulong mask;
1325
    uint32_t mb, me, sh;
1326

    
1327
    mb = MB(ctx->opcode);
1328
    me = ME(ctx->opcode);
1329
    sh = SH(ctx->opcode);
1330
    if (likely(sh == 0)) {
1331
        if (likely(mb == 0 && me == 31)) {
1332
            gen_op_load_gpr_T0(rS(ctx->opcode));
1333
            goto do_store;
1334
        } else if (likely(mb == 31 && me == 0)) {
1335
            gen_op_load_gpr_T0(rA(ctx->opcode));
1336
            goto do_store;
1337
        }
1338
        gen_op_load_gpr_T0(rS(ctx->opcode));
1339
        gen_op_load_gpr_T1(rA(ctx->opcode));
1340
        goto do_mask;
1341
    }
1342
    gen_op_load_gpr_T0(rS(ctx->opcode));
1343
    gen_op_load_gpr_T1(rA(ctx->opcode));
1344
    gen_op_rotli32_T0(SH(ctx->opcode));
1345
 do_mask:
1346
#if defined(TARGET_PPC64)
1347
    mb += 32;
1348
    me += 32;
1349
#endif
1350
    mask = MASK(mb, me);
1351
    gen_op_andi_T0(mask);
1352
    gen_op_andi_T1(~mask);
1353
    gen_op_or();
1354
 do_store:
1355
    gen_op_store_T0_gpr(rA(ctx->opcode));
1356
    if (unlikely(Rc(ctx->opcode) != 0))
1357
        gen_set_Rc0(ctx);
1358
}
1359
/* rlwinm & rlwinm. */
1360
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1361
{
1362
    uint32_t mb, me, sh;
1363

    
1364
    sh = SH(ctx->opcode);
1365
    mb = MB(ctx->opcode);
1366
    me = ME(ctx->opcode);
1367
    gen_op_load_gpr_T0(rS(ctx->opcode));
1368
    if (likely(sh == 0)) {
1369
        goto do_mask;
1370
    }
1371
    if (likely(mb == 0)) {
1372
        if (likely(me == 31)) {
1373
            gen_op_rotli32_T0(sh);
1374
            goto do_store;
1375
        } else if (likely(me == (31 - sh))) {
1376
            gen_op_sli_T0(sh);
1377
            goto do_store;
1378
        }
1379
    } else if (likely(me == 31)) {
1380
        if (likely(sh == (32 - mb))) {
1381
            gen_op_srli_T0(mb);
1382
            goto do_store;
1383
        }
1384
    }
1385
    gen_op_rotli32_T0(sh);
1386
 do_mask:
1387
#if defined(TARGET_PPC64)
1388
    mb += 32;
1389
    me += 32;
1390
#endif
1391
    gen_op_andi_T0(MASK(mb, me));
1392
 do_store:
1393
    gen_op_store_T0_gpr(rA(ctx->opcode));
1394
    if (unlikely(Rc(ctx->opcode) != 0))
1395
        gen_set_Rc0(ctx);
1396
}
1397
/* rlwnm & rlwnm. */
1398
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1399
{
1400
    uint32_t mb, me;
1401

    
1402
    mb = MB(ctx->opcode);
1403
    me = ME(ctx->opcode);
1404
    gen_op_load_gpr_T0(rS(ctx->opcode));
1405
    gen_op_load_gpr_T1(rB(ctx->opcode));
1406
    gen_op_rotl32_T0_T1();
1407
    if (unlikely(mb != 0 || me != 31)) {
1408
#if defined(TARGET_PPC64)
1409
        mb += 32;
1410
        me += 32;
1411
#endif
1412
        gen_op_andi_T0(MASK(mb, me));
1413
    }
1414
    gen_op_store_T0_gpr(rA(ctx->opcode));
1415
    if (unlikely(Rc(ctx->opcode) != 0))
1416
        gen_set_Rc0(ctx);
1417
}
1418

    
1419
#if defined(TARGET_PPC64)
1420
#define GEN_PPC64_R2(name, opc1, opc2)                                        \
1421
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1422
{                                                                             \
1423
    gen_##name(ctx, 0);                                                       \
1424
}                                                                             \
1425
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1426
             PPC_64B)                                                         \
1427
{                                                                             \
1428
    gen_##name(ctx, 1);                                                       \
1429
}
1430
#define GEN_PPC64_R4(name, opc1, opc2)                                        \
1431
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1432
{                                                                             \
1433
    gen_##name(ctx, 0, 0);                                                    \
1434
}                                                                             \
1435
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
1436
             PPC_64B)                                                         \
1437
{                                                                             \
1438
    gen_##name(ctx, 0, 1);                                                    \
1439
}                                                                             \
1440
GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1441
             PPC_64B)                                                         \
1442
{                                                                             \
1443
    gen_##name(ctx, 1, 0);                                                    \
1444
}                                                                             \
1445
GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
1446
             PPC_64B)                                                         \
1447
{                                                                             \
1448
    gen_##name(ctx, 1, 1);                                                    \
1449
}
1450

    
1451
static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1452
{
1453
    if (mask >> 32)
1454
        gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1455
    else
1456
        gen_op_andi_T0(mask);
1457
}
1458

    
1459
static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1460
{
1461
    if (mask >> 32)
1462
        gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1463
    else
1464
        gen_op_andi_T1(mask);
1465
}
1466

    
1467
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1468
                                      uint32_t me, uint32_t sh)
1469
{
1470
    gen_op_load_gpr_T0(rS(ctx->opcode));
1471
    if (likely(sh == 0)) {
1472
        goto do_mask;
1473
    }
1474
    if (likely(mb == 0)) {
1475
        if (likely(me == 63)) {
1476
            gen_op_rotli64_T0(sh);
1477
            goto do_store;
1478
        } else if (likely(me == (63 - sh))) {
1479
            gen_op_sli_T0(sh);
1480
            goto do_store;
1481
        }
1482
    } else if (likely(me == 63)) {
1483
        if (likely(sh == (64 - mb))) {
1484
            gen_op_srli_T0_64(mb);
1485
            goto do_store;
1486
        }
1487
    }
1488
    gen_op_rotli64_T0(sh);
1489
 do_mask:
1490
    gen_andi_T0_64(ctx, MASK(mb, me));
1491
 do_store:
1492
    gen_op_store_T0_gpr(rA(ctx->opcode));
1493
    if (unlikely(Rc(ctx->opcode) != 0))
1494
        gen_set_Rc0(ctx);
1495
}
1496
/* rldicl - rldicl. */
1497
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1498
{
1499
    uint32_t sh, mb;
1500

    
1501
    sh = SH(ctx->opcode) | (shn << 5);
1502
    mb = MB(ctx->opcode) | (mbn << 5);
1503
    gen_rldinm(ctx, mb, 63, sh);
1504
}
1505
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1506
/* rldicr - rldicr. */
1507
static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1508
{
1509
    uint32_t sh, me;
1510

    
1511
    sh = SH(ctx->opcode) | (shn << 5);
1512
    me = MB(ctx->opcode) | (men << 5);
1513
    gen_rldinm(ctx, 0, me, sh);
1514
}
1515
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1516
/* rldic - rldic. */
1517
static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1518
{
1519
    uint32_t sh, mb;
1520

    
1521
    sh = SH(ctx->opcode) | (shn << 5);
1522
    mb = MB(ctx->opcode) | (mbn << 5);
1523
    gen_rldinm(ctx, mb, 63 - sh, sh);
1524
}
1525
GEN_PPC64_R4(rldic, 0x1E, 0x04);
1526

    
1527
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1528
                                     uint32_t me)
1529
{
1530
    gen_op_load_gpr_T0(rS(ctx->opcode));
1531
    gen_op_load_gpr_T1(rB(ctx->opcode));
1532
    gen_op_rotl64_T0_T1();
1533
    if (unlikely(mb != 0 || me != 63)) {
1534
        gen_andi_T0_64(ctx, MASK(mb, me));
1535
    }
1536
    gen_op_store_T0_gpr(rA(ctx->opcode));
1537
    if (unlikely(Rc(ctx->opcode) != 0))
1538
        gen_set_Rc0(ctx);
1539
}
1540

    
1541
/* rldcl - rldcl. */
1542
static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1543
{
1544
    uint32_t mb;
1545

    
1546
    mb = MB(ctx->opcode) | (mbn << 5);
1547
    gen_rldnm(ctx, mb, 63);
1548
}
1549
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1550
/* rldcr - rldcr. */
1551
static always_inline void gen_rldcr (DisasContext *ctx, int men)
1552
{
1553
    uint32_t me;
1554

    
1555
    me = MB(ctx->opcode) | (men << 5);
1556
    gen_rldnm(ctx, 0, me);
1557
}
1558
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1559
/* rldimi - rldimi. */
1560
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1561
{
1562
    uint64_t mask;
1563
    uint32_t sh, mb;
1564

    
1565
    sh = SH(ctx->opcode) | (shn << 5);
1566
    mb = MB(ctx->opcode) | (mbn << 5);
1567
    if (likely(sh == 0)) {
1568
        if (likely(mb == 0)) {
1569
            gen_op_load_gpr_T0(rS(ctx->opcode));
1570
            goto do_store;
1571
        } else if (likely(mb == 63)) {
1572
            gen_op_load_gpr_T0(rA(ctx->opcode));
1573
            goto do_store;
1574
        }
1575
        gen_op_load_gpr_T0(rS(ctx->opcode));
1576
        gen_op_load_gpr_T1(rA(ctx->opcode));
1577
        goto do_mask;
1578
    }
1579
    gen_op_load_gpr_T0(rS(ctx->opcode));
1580
    gen_op_load_gpr_T1(rA(ctx->opcode));
1581
    gen_op_rotli64_T0(sh);
1582
 do_mask:
1583
    mask = MASK(mb, 63 - sh);
1584
    gen_andi_T0_64(ctx, mask);
1585
    gen_andi_T1_64(ctx, ~mask);
1586
    gen_op_or();
1587
 do_store:
1588
    gen_op_store_T0_gpr(rA(ctx->opcode));
1589
    if (unlikely(Rc(ctx->opcode) != 0))
1590
        gen_set_Rc0(ctx);
1591
}
1592
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1593
#endif
1594

    
1595
/***                             Integer shift                             ***/
1596
/* slw & slw. */
1597
__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1598
/* sraw & sraw. */
1599
__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1600
/* srawi & srawi. */
1601
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1602
{
1603
    int mb, me;
1604
    gen_op_load_gpr_T0(rS(ctx->opcode));
1605
    if (SH(ctx->opcode) != 0) {
1606
        gen_op_move_T1_T0();
1607
        mb = 32 - SH(ctx->opcode);
1608
        me = 31;
1609
#if defined(TARGET_PPC64)
1610
        mb += 32;
1611
        me += 32;
1612
#endif
1613
        gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1614
    }
1615
    gen_op_store_T0_gpr(rA(ctx->opcode));
1616
    if (unlikely(Rc(ctx->opcode) != 0))
1617
        gen_set_Rc0(ctx);
1618
}
1619
/* srw & srw. */
1620
__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1621

    
1622
#if defined(TARGET_PPC64)
1623
/* sld & sld. */
1624
__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1625
/* srad & srad. */
1626
__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1627
/* sradi & sradi. */
1628
static always_inline void gen_sradi (DisasContext *ctx, int n)
1629
{
1630
    uint64_t mask;
1631
    int sh, mb, me;
1632

    
1633
    gen_op_load_gpr_T0(rS(ctx->opcode));
1634
    sh = SH(ctx->opcode) + (n << 5);
1635
    if (sh != 0) {
1636
        gen_op_move_T1_T0();
1637
        mb = 64 - SH(ctx->opcode);
1638
        me = 63;
1639
        mask = MASK(mb, me);
1640
        gen_op_sradi(sh, mask >> 32, mask);
1641
    }
1642
    gen_op_store_T0_gpr(rA(ctx->opcode));
1643
    if (unlikely(Rc(ctx->opcode) != 0))
1644
        gen_set_Rc0(ctx);
1645
}
1646
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1647
{
1648
    gen_sradi(ctx, 0);
1649
}
1650
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1651
{
1652
    gen_sradi(ctx, 1);
1653
}
1654
/* srd & srd. */
1655
__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1656
#endif
1657

    
1658
/***                       Floating-Point arithmetic                       ***/
1659
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, type)                     \
1660
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)                        \
1661
{                                                                             \
1662
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1663
        GEN_EXCP_NO_FP(ctx);                                                  \
1664
        return;                                                               \
1665
    }                                                                         \
1666
    gen_op_reset_scrfx();                                                     \
1667
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1668
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
1669
    gen_op_load_fpr_FT2(rB(ctx->opcode));                                     \
1670
    gen_op_f##op();                                                           \
1671
    if (isfloat) {                                                            \
1672
        gen_op_frsp();                                                        \
1673
    }                                                                         \
1674
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1675
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1676
        gen_op_set_Rc1();                                                     \
1677
}
1678

    
1679
#define GEN_FLOAT_ACB(name, op2, type)                                        \
1680
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, type);                               \
1681
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, type);
1682

    
1683
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat)                     \
1684
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
1685
{                                                                             \
1686
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1687
        GEN_EXCP_NO_FP(ctx);                                                  \
1688
        return;                                                               \
1689
    }                                                                         \
1690
    gen_op_reset_scrfx();                                                     \
1691
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1692
    gen_op_load_fpr_FT1(rB(ctx->opcode));                                     \
1693
    gen_op_f##op();                                                           \
1694
    if (isfloat) {                                                            \
1695
        gen_op_frsp();                                                        \
1696
    }                                                                         \
1697
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1698
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1699
        gen_op_set_Rc1();                                                     \
1700
}
1701
#define GEN_FLOAT_AB(name, op2, inval)                                        \
1702
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0);                               \
1703
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
1704

    
1705
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat)                     \
1706
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT)                        \
1707
{                                                                             \
1708
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1709
        GEN_EXCP_NO_FP(ctx);                                                  \
1710
        return;                                                               \
1711
    }                                                                         \
1712
    gen_op_reset_scrfx();                                                     \
1713
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1714
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
1715
    gen_op_f##op();                                                           \
1716
    if (isfloat) {                                                            \
1717
        gen_op_frsp();                                                        \
1718
    }                                                                         \
1719
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1720
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1721
        gen_op_set_Rc1();                                                     \
1722
}
1723
#define GEN_FLOAT_AC(name, op2, inval)                                        \
1724
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0);                               \
1725
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
1726

    
1727
#define GEN_FLOAT_B(name, op2, op3, type)                                     \
1728
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)                        \
1729
{                                                                             \
1730
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1731
        GEN_EXCP_NO_FP(ctx);                                                  \
1732
        return;                                                               \
1733
    }                                                                         \
1734
    gen_op_reset_scrfx();                                                     \
1735
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
1736
    gen_op_f##name();                                                         \
1737
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1738
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1739
        gen_op_set_Rc1();                                                     \
1740
}
1741

    
1742
#define GEN_FLOAT_BS(name, op1, op2, type)                                    \
1743
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)                        \
1744
{                                                                             \
1745
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1746
        GEN_EXCP_NO_FP(ctx);                                                  \
1747
        return;                                                               \
1748
    }                                                                         \
1749
    gen_op_reset_scrfx();                                                     \
1750
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
1751
    gen_op_f##name();                                                         \
1752
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1753
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1754
        gen_op_set_Rc1();                                                     \
1755
}
1756

    
1757
/* fadd - fadds */
1758
GEN_FLOAT_AB(add, 0x15, 0x000007C0);
1759
/* fdiv - fdivs */
1760
GEN_FLOAT_AB(div, 0x12, 0x000007C0);
1761
/* fmul - fmuls */
1762
GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
1763

    
1764
/* fre */
1765
GEN_FLOAT_BS(re, 0x3F, 0x18, PPC_FLOAT_EXT);
1766

    
1767
/* fres */
1768
GEN_FLOAT_BS(res, 0x3B, 0x18, PPC_FLOAT_FRES);
1769

    
1770
/* frsqrte */
1771
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, PPC_FLOAT_FRSQRTE);
1772

    
1773
/* fsel */
1774
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, PPC_FLOAT_FSEL);
1775
/* fsub - fsubs */
1776
GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
1777
/* Optional: */
1778
/* fsqrt */
1779
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1780
{
1781
    if (unlikely(!ctx->fpu_enabled)) {
1782
        GEN_EXCP_NO_FP(ctx);
1783
        return;
1784
    }
1785
    gen_op_reset_scrfx();
1786
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1787
    gen_op_fsqrt();
1788
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1789
    if (unlikely(Rc(ctx->opcode) != 0))
1790
        gen_op_set_Rc1();
1791
}
1792

    
1793
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1794
{
1795
    if (unlikely(!ctx->fpu_enabled)) {
1796
        GEN_EXCP_NO_FP(ctx);
1797
        return;
1798
    }
1799
    gen_op_reset_scrfx();
1800
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1801
    gen_op_fsqrt();
1802
    gen_op_frsp();
1803
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1804
    if (unlikely(Rc(ctx->opcode) != 0))
1805
        gen_op_set_Rc1();
1806
}
1807

    
1808
/***                     Floating-Point multiply-and-add                   ***/
1809
/* fmadd - fmadds */
1810
GEN_FLOAT_ACB(madd, 0x1D, PPC_FLOAT);
1811
/* fmsub - fmsubs */
1812
GEN_FLOAT_ACB(msub, 0x1C, PPC_FLOAT);
1813
/* fnmadd - fnmadds */
1814
GEN_FLOAT_ACB(nmadd, 0x1F, PPC_FLOAT);
1815
/* fnmsub - fnmsubs */
1816
GEN_FLOAT_ACB(nmsub, 0x1E, PPC_FLOAT);
1817

    
1818
/***                     Floating-Point round & convert                    ***/
1819
/* fctiw */
1820
GEN_FLOAT_B(ctiw, 0x0E, 0x00, PPC_FLOAT);
1821
/* fctiwz */
1822
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, PPC_FLOAT);
1823
/* frsp */
1824
GEN_FLOAT_B(rsp, 0x0C, 0x00, PPC_FLOAT);
1825
#if defined(TARGET_PPC64)
1826
/* fcfid */
1827
GEN_FLOAT_B(cfid, 0x0E, 0x1A, PPC_64B);
1828
/* fctid */
1829
GEN_FLOAT_B(ctid, 0x0E, 0x19, PPC_64B);
1830
/* fctidz */
1831
GEN_FLOAT_B(ctidz, 0x0F, 0x19, PPC_64B);
1832
#endif
1833

    
1834
/* frin */
1835
GEN_FLOAT_B(rin, 0x08, 0x0C, PPC_FLOAT_EXT);
1836
/* friz */
1837
GEN_FLOAT_B(riz, 0x08, 0x0D, PPC_FLOAT_EXT);
1838
/* frip */
1839
GEN_FLOAT_B(rip, 0x08, 0x0E, PPC_FLOAT_EXT);
1840
/* frim */
1841
GEN_FLOAT_B(rim, 0x08, 0x0F, PPC_FLOAT_EXT);
1842

    
1843
/***                         Floating-Point compare                        ***/
1844
/* fcmpo */
1845
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1846
{
1847
    if (unlikely(!ctx->fpu_enabled)) {
1848
        GEN_EXCP_NO_FP(ctx);
1849
        return;
1850
    }
1851
    gen_op_reset_scrfx();
1852
    gen_op_load_fpr_FT0(rA(ctx->opcode));
1853
    gen_op_load_fpr_FT1(rB(ctx->opcode));
1854
    gen_op_fcmpo();
1855
    gen_op_store_T0_crf(crfD(ctx->opcode));
1856
}
1857

    
1858
/* fcmpu */
1859
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1860
{
1861
    if (unlikely(!ctx->fpu_enabled)) {
1862
        GEN_EXCP_NO_FP(ctx);
1863
        return;
1864
    }
1865
    gen_op_reset_scrfx();
1866
    gen_op_load_fpr_FT0(rA(ctx->opcode));
1867
    gen_op_load_fpr_FT1(rB(ctx->opcode));
1868
    gen_op_fcmpu();
1869
    gen_op_store_T0_crf(crfD(ctx->opcode));
1870
}
1871

    
1872
/***                         Floating-point move                           ***/
1873
/* fabs */
1874
GEN_FLOAT_B(abs, 0x08, 0x08, PPC_FLOAT);
1875

    
1876
/* fmr  - fmr. */
1877
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1878
{
1879
    if (unlikely(!ctx->fpu_enabled)) {
1880
        GEN_EXCP_NO_FP(ctx);
1881
        return;
1882
    }
1883
    gen_op_reset_scrfx();
1884
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1885
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1886
    if (unlikely(Rc(ctx->opcode) != 0))
1887
        gen_op_set_Rc1();
1888
}
1889

    
1890
/* fnabs */
1891
GEN_FLOAT_B(nabs, 0x08, 0x04, PPC_FLOAT);
1892
/* fneg */
1893
GEN_FLOAT_B(neg, 0x08, 0x01, PPC_FLOAT);
1894

    
1895
/***                  Floating-Point status & ctrl register                ***/
1896
/* mcrfs */
1897
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1898
{
1899
    if (unlikely(!ctx->fpu_enabled)) {
1900
        GEN_EXCP_NO_FP(ctx);
1901
        return;
1902
    }
1903
    gen_op_load_fpscr_T0(crfS(ctx->opcode));
1904
    gen_op_store_T0_crf(crfD(ctx->opcode));
1905
    gen_op_clear_fpscr(crfS(ctx->opcode));
1906
}
1907

    
1908
/* mffs */
1909
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1910
{
1911
    if (unlikely(!ctx->fpu_enabled)) {
1912
        GEN_EXCP_NO_FP(ctx);
1913
        return;
1914
    }
1915
    gen_op_load_fpscr();
1916
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1917
    if (unlikely(Rc(ctx->opcode) != 0))
1918
        gen_op_set_Rc1();
1919
}
1920

    
1921
/* mtfsb0 */
1922
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1923
{
1924
    uint8_t crb;
1925

    
1926
    if (unlikely(!ctx->fpu_enabled)) {
1927
        GEN_EXCP_NO_FP(ctx);
1928
        return;
1929
    }
1930
    crb = crbD(ctx->opcode) >> 2;
1931
    gen_op_load_fpscr_T0(crb);
1932
    gen_op_andi_T0(~(1 << (crbD(ctx->opcode) & 0x03)));
1933
    gen_op_store_T0_fpscr(crb);
1934
    if (unlikely(Rc(ctx->opcode) != 0))
1935
        gen_op_set_Rc1();
1936
}
1937

    
1938
/* mtfsb1 */
1939
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1940
{
1941
    uint8_t crb;
1942

    
1943
    if (unlikely(!ctx->fpu_enabled)) {
1944
        GEN_EXCP_NO_FP(ctx);
1945
        return;
1946
    }
1947
    crb = crbD(ctx->opcode) >> 2;
1948
    gen_op_load_fpscr_T0(crb);
1949
    gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1950
    gen_op_store_T0_fpscr(crb);
1951
    if (unlikely(Rc(ctx->opcode) != 0))
1952
        gen_op_set_Rc1();
1953
}
1954

    
1955
/* mtfsf */
1956
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1957
{
1958
    if (unlikely(!ctx->fpu_enabled)) {
1959
        GEN_EXCP_NO_FP(ctx);
1960
        return;
1961
    }
1962
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1963
    gen_op_store_fpscr(FM(ctx->opcode));
1964
    if (unlikely(Rc(ctx->opcode) != 0))
1965
        gen_op_set_Rc1();
1966
}
1967

    
1968
/* mtfsfi */
1969
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1970
{
1971
    if (unlikely(!ctx->fpu_enabled)) {
1972
        GEN_EXCP_NO_FP(ctx);
1973
        return;
1974
    }
1975
    gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1976
    if (unlikely(Rc(ctx->opcode) != 0))
1977
        gen_op_set_Rc1();
1978
}
1979

    
1980
/***                           Addressing modes                            ***/
1981
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
1982
static always_inline void gen_addr_imm_index (DisasContext *ctx,
1983
                                              target_long maskl)
1984
{
1985
    target_long simm = SIMM(ctx->opcode);
1986

    
1987
    simm &= ~maskl;
1988
    if (rA(ctx->opcode) == 0) {
1989
        gen_set_T0(simm);
1990
    } else {
1991
        gen_op_load_gpr_T0(rA(ctx->opcode));
1992
        if (likely(simm != 0))
1993
            gen_op_addi(simm);
1994
    }
1995
#ifdef DEBUG_MEMORY_ACCESSES
1996
    gen_op_print_mem_EA();
1997
#endif
1998
}
1999

    
2000
static always_inline void gen_addr_reg_index (DisasContext *ctx)
2001
{
2002
    if (rA(ctx->opcode) == 0) {
2003
        gen_op_load_gpr_T0(rB(ctx->opcode));
2004
    } else {
2005
        gen_op_load_gpr_T0(rA(ctx->opcode));
2006
        gen_op_load_gpr_T1(rB(ctx->opcode));
2007
        gen_op_add();
2008
    }
2009
#ifdef DEBUG_MEMORY_ACCESSES
2010
    gen_op_print_mem_EA();
2011
#endif
2012
}
2013

    
2014
static always_inline void gen_addr_register (DisasContext *ctx)
2015
{
2016
    if (rA(ctx->opcode) == 0) {
2017
        gen_op_reset_T0();
2018
    } else {
2019
        gen_op_load_gpr_T0(rA(ctx->opcode));
2020
    }
2021
#ifdef DEBUG_MEMORY_ACCESSES
2022
    gen_op_print_mem_EA();
2023
#endif
2024
}
2025

    
2026
/***                             Integer load                              ***/
2027
#define op_ldst(name)        (*gen_op_##name[ctx->mem_idx])()
2028
#if defined(CONFIG_USER_ONLY)
2029
#if defined(TARGET_PPC64)
2030
/* User mode only - 64 bits */
2031
#define OP_LD_TABLE(width)                                                    \
2032
static GenOpFunc *gen_op_l##width[] = {                                       \
2033
    &gen_op_l##width##_raw,                                                   \
2034
    &gen_op_l##width##_le_raw,                                                \
2035
    &gen_op_l##width##_64_raw,                                                \
2036
    &gen_op_l##width##_le_64_raw,                                             \
2037
};
2038
#define OP_ST_TABLE(width)                                                    \
2039
static GenOpFunc *gen_op_st##width[] = {                                      \
2040
    &gen_op_st##width##_raw,                                                  \
2041
    &gen_op_st##width##_le_raw,                                               \
2042
    &gen_op_st##width##_64_raw,                                               \
2043
    &gen_op_st##width##_le_64_raw,                                            \
2044
};
2045
/* Byte access routine are endian safe */
2046
#define gen_op_stb_le_64_raw gen_op_stb_64_raw
2047
#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2048
#else
2049
/* User mode only - 32 bits */
2050
#define OP_LD_TABLE(width)                                                    \
2051
static GenOpFunc *gen_op_l##width[] = {                                       \
2052
    &gen_op_l##width##_raw,                                                   \
2053
    &gen_op_l##width##_le_raw,                                                \
2054
};
2055
#define OP_ST_TABLE(width)                                                    \
2056
static GenOpFunc *gen_op_st##width[] = {                                      \
2057
    &gen_op_st##width##_raw,                                                  \
2058
    &gen_op_st##width##_le_raw,                                               \
2059
};
2060
#endif
2061
/* Byte access routine are endian safe */
2062
#define gen_op_stb_le_raw gen_op_stb_raw
2063
#define gen_op_lbz_le_raw gen_op_lbz_raw
2064
#else
2065
#if defined(TARGET_PPC64)
2066
#if defined(TARGET_PPC64H)
2067
/* Full system - 64 bits with hypervisor mode */
2068
#define OP_LD_TABLE(width)                                                    \
2069
static GenOpFunc *gen_op_l##width[] = {                                       \
2070
    &gen_op_l##width##_user,                                                  \
2071
    &gen_op_l##width##_le_user,                                               \
2072
    &gen_op_l##width##_64_user,                                               \
2073
    &gen_op_l##width##_le_64_user,                                            \
2074
    &gen_op_l##width##_kernel,                                                \
2075
    &gen_op_l##width##_le_kernel,                                             \
2076
    &gen_op_l##width##_64_kernel,                                             \
2077
    &gen_op_l##width##_le_64_kernel,                                          \
2078
    &gen_op_l##width##_hypv,                                                  \
2079
    &gen_op_l##width##_le_hypv,                                               \
2080
    &gen_op_l##width##_64_hypv,                                               \
2081
    &gen_op_l##width##_le_64_hypv,                                            \
2082
};
2083
#define OP_ST_TABLE(width)                                                    \
2084
static GenOpFunc *gen_op_st##width[] = {                                      \
2085
    &gen_op_st##width##_user,                                                 \
2086
    &gen_op_st##width##_le_user,                                              \
2087
    &gen_op_st##width##_64_user,                                              \
2088
    &gen_op_st##width##_le_64_user,                                           \
2089
    &gen_op_st##width##_kernel,                                               \
2090
    &gen_op_st##width##_le_kernel,                                            \
2091
    &gen_op_st##width##_64_kernel,                                            \
2092
    &gen_op_st##width##_le_64_kernel,                                         \
2093
    &gen_op_st##width##_hypv,                                                 \
2094
    &gen_op_st##width##_le_hypv,                                              \
2095
    &gen_op_st##width##_64_hypv,                                              \
2096
    &gen_op_st##width##_le_64_hypv,                                           \
2097
};
2098
/* Byte access routine are endian safe */
2099
#define gen_op_stb_le_hypv      gen_op_stb_64_hypv
2100
#define gen_op_lbz_le_hypv      gen_op_lbz_64_hypv
2101
#define gen_op_stb_le_64_hypv   gen_op_stb_64_hypv
2102
#define gen_op_lbz_le_64_hypv   gen_op_lbz_64_hypv
2103
#else
2104
/* Full system - 64 bits */
2105
#define OP_LD_TABLE(width)                                                    \
2106
static GenOpFunc *gen_op_l##width[] = {                                       \
2107
    &gen_op_l##width##_user,                                                  \
2108
    &gen_op_l##width##_le_user,                                               \
2109
    &gen_op_l##width##_64_user,                                               \
2110
    &gen_op_l##width##_le_64_user,                                            \
2111
    &gen_op_l##width##_kernel,                                                \
2112
    &gen_op_l##width##_le_kernel,                                             \
2113
    &gen_op_l##width##_64_kernel,                                             \
2114
    &gen_op_l##width##_le_64_kernel,                                          \
2115
};
2116
#define OP_ST_TABLE(width)                                                    \
2117
static GenOpFunc *gen_op_st##width[] = {                                      \
2118
    &gen_op_st##width##_user,                                                 \
2119
    &gen_op_st##width##_le_user,                                              \
2120
    &gen_op_st##width##_64_user,                                              \
2121
    &gen_op_st##width##_le_64_user,                                           \
2122
    &gen_op_st##width##_kernel,                                               \
2123
    &gen_op_st##width##_le_kernel,                                            \
2124
    &gen_op_st##width##_64_kernel,                                            \
2125
    &gen_op_st##width##_le_64_kernel,                                         \
2126
};
2127
#endif
2128
/* Byte access routine are endian safe */
2129
#define gen_op_stb_le_64_user   gen_op_stb_64_user
2130
#define gen_op_lbz_le_64_user   gen_op_lbz_64_user
2131
#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2132
#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2133
#else
2134
/* Full system - 32 bits */
2135
#define OP_LD_TABLE(width)                                                    \
2136
static GenOpFunc *gen_op_l##width[] = {                                       \
2137
    &gen_op_l##width##_user,                                                  \
2138
    &gen_op_l##width##_le_user,                                               \
2139
    &gen_op_l##width##_kernel,                                                \
2140
    &gen_op_l##width##_le_kernel,                                             \
2141
};
2142
#define OP_ST_TABLE(width)                                                    \
2143
static GenOpFunc *gen_op_st##width[] = {                                      \
2144
    &gen_op_st##width##_user,                                                 \
2145
    &gen_op_st##width##_le_user,                                              \
2146
    &gen_op_st##width##_kernel,                                               \
2147
    &gen_op_st##width##_le_kernel,                                            \
2148
};
2149
#endif
2150
/* Byte access routine are endian safe */
2151
#define gen_op_stb_le_user   gen_op_stb_user
2152
#define gen_op_lbz_le_user   gen_op_lbz_user
2153
#define gen_op_stb_le_kernel gen_op_stb_kernel
2154
#define gen_op_lbz_le_kernel gen_op_lbz_kernel
2155
#endif
2156

    
2157
#define GEN_LD(width, opc, type)                                              \
2158
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type)                      \
2159
{                                                                             \
2160
    gen_addr_imm_index(ctx, 0);                                               \
2161
    op_ldst(l##width);                                                        \
2162
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2163
}
2164

    
2165
#define GEN_LDU(width, opc, type)                                             \
2166
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
2167
{                                                                             \
2168
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2169
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2170
        GEN_EXCP_INVAL(ctx);                                                  \
2171
        return;                                                               \
2172
    }                                                                         \
2173
    if (type == PPC_64B)                                                      \
2174
        gen_addr_imm_index(ctx, 0x03);                                        \
2175
    else                                                                      \
2176
        gen_addr_imm_index(ctx, 0);                                           \
2177
    op_ldst(l##width);                                                        \
2178
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2179
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2180
}
2181

    
2182
#define GEN_LDUX(width, opc2, opc3, type)                                     \
2183
GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                 \
2184
{                                                                             \
2185
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2186
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2187
        GEN_EXCP_INVAL(ctx);                                                  \
2188
        return;                                                               \
2189
    }                                                                         \
2190
    gen_addr_reg_index(ctx);                                                  \
2191
    op_ldst(l##width);                                                        \
2192
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2193
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2194
}
2195

    
2196
#define GEN_LDX(width, opc2, opc3, type)                                      \
2197
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type)                  \
2198
{                                                                             \
2199
    gen_addr_reg_index(ctx);                                                  \
2200
    op_ldst(l##width);                                                        \
2201
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2202
}
2203

    
2204
#define GEN_LDS(width, op, type)                                              \
2205
OP_LD_TABLE(width);                                                           \
2206
GEN_LD(width, op | 0x20, type);                                               \
2207
GEN_LDU(width, op | 0x21, type);                                              \
2208
GEN_LDUX(width, 0x17, op | 0x01, type);                                       \
2209
GEN_LDX(width, 0x17, op | 0x00, type)
2210

    
2211
/* lbz lbzu lbzux lbzx */
2212
GEN_LDS(bz, 0x02, PPC_INTEGER);
2213
/* lha lhau lhaux lhax */
2214
GEN_LDS(ha, 0x0A, PPC_INTEGER);
2215
/* lhz lhzu lhzux lhzx */
2216
GEN_LDS(hz, 0x08, PPC_INTEGER);
2217
/* lwz lwzu lwzux lwzx */
2218
GEN_LDS(wz, 0x00, PPC_INTEGER);
2219
#if defined(TARGET_PPC64)
2220
OP_LD_TABLE(wa);
2221
OP_LD_TABLE(d);
2222
/* lwaux */
2223
GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2224
/* lwax */
2225
GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2226
/* ldux */
2227
GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2228
/* ldx */
2229
GEN_LDX(d, 0x15, 0x00, PPC_64B);
2230
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2231
{
2232
    if (Rc(ctx->opcode)) {
2233
        if (unlikely(rA(ctx->opcode) == 0 ||
2234
                     rA(ctx->opcode) == rD(ctx->opcode))) {
2235
            GEN_EXCP_INVAL(ctx);
2236
            return;
2237
        }
2238
    }
2239
    gen_addr_imm_index(ctx, 0x03);
2240
    if (ctx->opcode & 0x02) {
2241
        /* lwa (lwau is undefined) */
2242
        op_ldst(lwa);
2243
    } else {
2244
        /* ld - ldu */
2245
        op_ldst(ld);
2246
    }
2247
    gen_op_store_T1_gpr(rD(ctx->opcode));
2248
    if (Rc(ctx->opcode))
2249
        gen_op_store_T0_gpr(rA(ctx->opcode));
2250
}
2251
/* lq */
2252
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2253
{
2254
#if defined(CONFIG_USER_ONLY)
2255
    GEN_EXCP_PRIVOPC(ctx);
2256
#else
2257
    int ra, rd;
2258

    
2259
    /* Restore CPU state */
2260
    if (unlikely(ctx->supervisor == 0)) {
2261
        GEN_EXCP_PRIVOPC(ctx);
2262
        return;
2263
    }
2264
    ra = rA(ctx->opcode);
2265
    rd = rD(ctx->opcode);
2266
    if (unlikely((rd & 1) || rd == ra)) {
2267
        GEN_EXCP_INVAL(ctx);
2268
        return;
2269
    }
2270
    if (unlikely(ctx->mem_idx & 1)) {
2271
        /* Little-endian mode is not handled */
2272
        GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2273
        return;
2274
    }
2275
    gen_addr_imm_index(ctx, 0x0F);
2276
    op_ldst(ld);
2277
    gen_op_store_T1_gpr(rd);
2278
    gen_op_addi(8);
2279
    op_ldst(ld);
2280
    gen_op_store_T1_gpr(rd + 1);
2281
#endif
2282
}
2283
#endif
2284

    
2285
/***                              Integer store                            ***/
2286
#define GEN_ST(width, opc, type)                                              \
2287
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
2288
{                                                                             \
2289
    gen_addr_imm_index(ctx, 0);                                               \
2290
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2291
    op_ldst(st##width);                                                       \
2292
}
2293

    
2294
#define GEN_STU(width, opc, type)                                             \
2295
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
2296
{                                                                             \
2297
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2298
        GEN_EXCP_INVAL(ctx);                                                  \
2299
        return;                                                               \
2300
    }                                                                         \
2301
    if (type == PPC_64B)                                                      \
2302
        gen_addr_imm_index(ctx, 0x03);                                        \
2303
    else                                                                      \
2304
        gen_addr_imm_index(ctx, 0);                                           \
2305
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2306
    op_ldst(st##width);                                                       \
2307
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2308
}
2309

    
2310
#define GEN_STUX(width, opc2, opc3, type)                                     \
2311
GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                \
2312
{                                                                             \
2313
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2314
        GEN_EXCP_INVAL(ctx);                                                  \
2315
        return;                                                               \
2316
    }                                                                         \
2317
    gen_addr_reg_index(ctx);                                                  \
2318
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2319
    op_ldst(st##width);                                                       \
2320
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2321
}
2322

    
2323
#define GEN_STX(width, opc2, opc3, type)                                      \
2324
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
2325
{                                                                             \
2326
    gen_addr_reg_index(ctx);                                                  \
2327
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2328
    op_ldst(st##width);                                                       \
2329
}
2330

    
2331
#define GEN_STS(width, op, type)                                              \
2332
OP_ST_TABLE(width);                                                           \
2333
GEN_ST(width, op | 0x20, type);                                               \
2334
GEN_STU(width, op | 0x21, type);                                              \
2335
GEN_STUX(width, 0x17, op | 0x01, type);                                       \
2336
GEN_STX(width, 0x17, op | 0x00, type)
2337

    
2338
/* stb stbu stbux stbx */
2339
GEN_STS(b, 0x06, PPC_INTEGER);
2340
/* sth sthu sthux sthx */
2341
GEN_STS(h, 0x0C, PPC_INTEGER);
2342
/* stw stwu stwux stwx */
2343
GEN_STS(w, 0x04, PPC_INTEGER);
2344
#if defined(TARGET_PPC64)
2345
OP_ST_TABLE(d);
2346
GEN_STUX(d, 0x15, 0x05, PPC_64B);
2347
GEN_STX(d, 0x15, 0x04, PPC_64B);
2348
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2349
{
2350
    int rs;
2351

    
2352
    rs = rS(ctx->opcode);
2353
    if ((ctx->opcode & 0x3) == 0x2) {
2354
#if defined(CONFIG_USER_ONLY)
2355
        GEN_EXCP_PRIVOPC(ctx);
2356
#else
2357
        /* stq */
2358
        if (unlikely(ctx->supervisor == 0)) {
2359
            GEN_EXCP_PRIVOPC(ctx);
2360
            return;
2361
        }
2362
        if (unlikely(rs & 1)) {
2363
            GEN_EXCP_INVAL(ctx);
2364
            return;
2365
        }
2366
        if (unlikely(ctx->mem_idx & 1)) {
2367
            /* Little-endian mode is not handled */
2368
            GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2369
            return;
2370
        }
2371
        gen_addr_imm_index(ctx, 0x03);
2372
        gen_op_load_gpr_T1(rs);
2373
        op_ldst(std);
2374
        gen_op_addi(8);
2375
        gen_op_load_gpr_T1(rs + 1);
2376
        op_ldst(std);
2377
#endif
2378
    } else {
2379
        /* std / stdu */
2380
        if (Rc(ctx->opcode)) {
2381
            if (unlikely(rA(ctx->opcode) == 0)) {
2382
                GEN_EXCP_INVAL(ctx);
2383
                return;
2384
            }
2385
        }
2386
        gen_addr_imm_index(ctx, 0x03);
2387
        gen_op_load_gpr_T1(rs);
2388
        op_ldst(std);
2389
        if (Rc(ctx->opcode))
2390
            gen_op_store_T0_gpr(rA(ctx->opcode));
2391
    }
2392
}
2393
#endif
2394
/***                Integer load and store with byte reverse               ***/
2395
/* lhbrx */
2396
OP_LD_TABLE(hbr);
2397
GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
2398
/* lwbrx */
2399
OP_LD_TABLE(wbr);
2400
GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
2401
/* sthbrx */
2402
OP_ST_TABLE(hbr);
2403
GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
2404
/* stwbrx */
2405
OP_ST_TABLE(wbr);
2406
GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
2407

    
2408
/***                    Integer load and store multiple                    ***/
2409
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2410
#if defined(CONFIG_USER_ONLY)
2411
/* User-mode only */
2412
static GenOpFunc1 *gen_op_lmw[] = {
2413
    &gen_op_lmw_raw,
2414
    &gen_op_lmw_le_raw,
2415
#if defined(TARGET_PPC64)
2416
    &gen_op_lmw_64_raw,
2417
    &gen_op_lmw_le_64_raw,
2418
#endif
2419
};
2420
static GenOpFunc1 *gen_op_stmw[] = {
2421
    &gen_op_stmw_raw,
2422
    &gen_op_stmw_le_raw,
2423
#if defined(TARGET_PPC64)
2424
    &gen_op_stmw_64_raw,
2425
    &gen_op_stmw_le_64_raw,
2426
#endif
2427
};
2428
#else
2429
#if defined(TARGET_PPC64)
2430
/* Full system - 64 bits mode */
2431
static GenOpFunc1 *gen_op_lmw[] = {
2432
    &gen_op_lmw_user,
2433
    &gen_op_lmw_le_user,
2434
    &gen_op_lmw_64_user,
2435
    &gen_op_lmw_le_64_user,
2436
    &gen_op_lmw_kernel,
2437
    &gen_op_lmw_le_kernel,
2438
    &gen_op_lmw_64_kernel,
2439
    &gen_op_lmw_le_64_kernel,
2440
#if defined(TARGET_PPC64H)
2441
    &gen_op_lmw_hypv,
2442
    &gen_op_lmw_le_hypv,
2443
    &gen_op_lmw_64_hypv,
2444
    &gen_op_lmw_le_64_hypv,
2445
#endif
2446
};
2447
static GenOpFunc1 *gen_op_stmw[] = {
2448
    &gen_op_stmw_user,
2449
    &gen_op_stmw_le_user,
2450
    &gen_op_stmw_64_user,
2451
    &gen_op_stmw_le_64_user,
2452
    &gen_op_stmw_kernel,
2453
    &gen_op_stmw_le_kernel,
2454
    &gen_op_stmw_64_kernel,
2455
    &gen_op_stmw_le_64_kernel,
2456
#if defined(TARGET_PPC64H)
2457
    &gen_op_stmw_hypv,
2458
    &gen_op_stmw_le_hypv,
2459
    &gen_op_stmw_64_hypv,
2460
    &gen_op_stmw_le_64_hypv,
2461
#endif
2462
};
2463
#else
2464
/* Full system - 32 bits mode */
2465
static GenOpFunc1 *gen_op_lmw[] = {
2466
    &gen_op_lmw_user,
2467
    &gen_op_lmw_le_user,
2468
    &gen_op_lmw_kernel,
2469
    &gen_op_lmw_le_kernel,
2470
};
2471
static GenOpFunc1 *gen_op_stmw[] = {
2472
    &gen_op_stmw_user,
2473
    &gen_op_stmw_le_user,
2474
    &gen_op_stmw_kernel,
2475
    &gen_op_stmw_le_kernel,
2476
};
2477
#endif
2478
#endif
2479

    
2480
/* lmw */
2481
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2482
{
2483
    /* NIP cannot be restored if the memory exception comes from an helper */
2484
    gen_update_nip(ctx, ctx->nip - 4);
2485
    gen_addr_imm_index(ctx, 0);
2486
    op_ldstm(lmw, rD(ctx->opcode));
2487
}
2488

    
2489
/* stmw */
2490
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2491
{
2492
    /* NIP cannot be restored if the memory exception comes from an helper */
2493
    gen_update_nip(ctx, ctx->nip - 4);
2494
    gen_addr_imm_index(ctx, 0);
2495
    op_ldstm(stmw, rS(ctx->opcode));
2496
}
2497

    
2498
/***                    Integer load and store strings                     ***/
2499
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2500
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2501
#if defined(CONFIG_USER_ONLY)
2502
/* User-mode only */
2503
static GenOpFunc1 *gen_op_lswi[] = {
2504
    &gen_op_lswi_raw,
2505
    &gen_op_lswi_le_raw,
2506
#if defined(TARGET_PPC64)
2507
    &gen_op_lswi_64_raw,
2508
    &gen_op_lswi_le_64_raw,
2509
#endif
2510
};
2511
static GenOpFunc3 *gen_op_lswx[] = {
2512
    &gen_op_lswx_raw,
2513
    &gen_op_lswx_le_raw,
2514
#if defined(TARGET_PPC64)
2515
    &gen_op_lswx_64_raw,
2516
    &gen_op_lswx_le_64_raw,
2517
#endif
2518
};
2519
static GenOpFunc1 *gen_op_stsw[] = {
2520
    &gen_op_stsw_raw,
2521
    &gen_op_stsw_le_raw,
2522
#if defined(TARGET_PPC64)
2523
    &gen_op_stsw_64_raw,
2524
    &gen_op_stsw_le_64_raw,
2525
#endif
2526
};
2527
#else
2528
#if defined(TARGET_PPC64)
2529
/* Full system - 64 bits mode */
2530
static GenOpFunc1 *gen_op_lswi[] = {
2531
    &gen_op_lswi_user,
2532
    &gen_op_lswi_le_user,
2533
    &gen_op_lswi_64_user,
2534
    &gen_op_lswi_le_64_user,
2535
    &gen_op_lswi_kernel,
2536
    &gen_op_lswi_le_kernel,
2537
    &gen_op_lswi_64_kernel,
2538
    &gen_op_lswi_le_64_kernel,
2539
#if defined(TARGET_PPC64H)
2540
    &gen_op_lswi_hypv,
2541
    &gen_op_lswi_le_hypv,
2542
    &gen_op_lswi_64_hypv,
2543
    &gen_op_lswi_le_64_hypv,
2544
#endif
2545
};
2546
static GenOpFunc3 *gen_op_lswx[] = {
2547
    &gen_op_lswx_user,
2548
    &gen_op_lswx_le_user,
2549
    &gen_op_lswx_64_user,
2550
    &gen_op_lswx_le_64_user,
2551
    &gen_op_lswx_kernel,
2552
    &gen_op_lswx_le_kernel,
2553
    &gen_op_lswx_64_kernel,
2554
    &gen_op_lswx_le_64_kernel,
2555
#if defined(TARGET_PPC64H)
2556
    &gen_op_lswx_hypv,
2557
    &gen_op_lswx_le_hypv,
2558
    &gen_op_lswx_64_hypv,
2559
    &gen_op_lswx_le_64_hypv,
2560
#endif
2561
};
2562
static GenOpFunc1 *gen_op_stsw[] = {
2563
    &gen_op_stsw_user,
2564
    &gen_op_stsw_le_user,
2565
    &gen_op_stsw_64_user,
2566
    &gen_op_stsw_le_64_user,
2567
    &gen_op_stsw_kernel,
2568
    &gen_op_stsw_le_kernel,
2569
    &gen_op_stsw_64_kernel,
2570
    &gen_op_stsw_le_64_kernel,
2571
#if defined(TARGET_PPC64H)
2572
    &gen_op_stsw_hypv,
2573
    &gen_op_stsw_le_hypv,
2574
    &gen_op_stsw_64_hypv,
2575
    &gen_op_stsw_le_64_hypv,
2576
#endif
2577
};
2578
#else
2579
/* Full system - 32 bits mode */
2580
static GenOpFunc1 *gen_op_lswi[] = {
2581
    &gen_op_lswi_user,
2582
    &gen_op_lswi_le_user,
2583
    &gen_op_lswi_kernel,
2584
    &gen_op_lswi_le_kernel,
2585
};
2586
static GenOpFunc3 *gen_op_lswx[] = {
2587
    &gen_op_lswx_user,
2588
    &gen_op_lswx_le_user,
2589
    &gen_op_lswx_kernel,
2590
    &gen_op_lswx_le_kernel,
2591
};
2592
static GenOpFunc1 *gen_op_stsw[] = {
2593
    &gen_op_stsw_user,
2594
    &gen_op_stsw_le_user,
2595
    &gen_op_stsw_kernel,
2596
    &gen_op_stsw_le_kernel,
2597
};
2598
#endif
2599
#endif
2600

    
2601
/* lswi */
2602
/* PowerPC32 specification says we must generate an exception if
2603
 * rA is in the range of registers to be loaded.
2604
 * In an other hand, IBM says this is valid, but rA won't be loaded.
2605
 * For now, I'll follow the spec...
2606
 */
2607
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
2608
{
2609
    int nb = NB(ctx->opcode);
2610
    int start = rD(ctx->opcode);
2611
    int ra = rA(ctx->opcode);
2612
    int nr;
2613

    
2614
    if (nb == 0)
2615
        nb = 32;
2616
    nr = nb / 4;
2617
    if (unlikely(((start + nr) > 32  &&
2618
                  start <= ra && (start + nr - 32) > ra) ||
2619
                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2620
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2621
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2622
        return;
2623
    }
2624
    /* NIP cannot be restored if the memory exception comes from an helper */
2625
    gen_update_nip(ctx, ctx->nip - 4);
2626
    gen_addr_register(ctx);
2627
    gen_op_set_T1(nb);
2628
    op_ldsts(lswi, start);
2629
}
2630

    
2631
/* lswx */
2632
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
2633
{
2634
    int ra = rA(ctx->opcode);
2635
    int rb = rB(ctx->opcode);
2636

    
2637
    /* NIP cannot be restored if the memory exception comes from an helper */
2638
    gen_update_nip(ctx, ctx->nip - 4);
2639
    gen_addr_reg_index(ctx);
2640
    if (ra == 0) {
2641
        ra = rb;
2642
    }
2643
    gen_op_load_xer_bc();
2644
    op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
2645
}
2646

    
2647
/* stswi */
2648
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
2649
{
2650
    int nb = NB(ctx->opcode);
2651

    
2652
    /* NIP cannot be restored if the memory exception comes from an helper */
2653
    gen_update_nip(ctx, ctx->nip - 4);
2654
    gen_addr_register(ctx);
2655
    if (nb == 0)
2656
        nb = 32;
2657
    gen_op_set_T1(nb);
2658
    op_ldsts(stsw, rS(ctx->opcode));
2659
}
2660

    
2661
/* stswx */
2662
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
2663
{
2664
    /* NIP cannot be restored if the memory exception comes from an helper */
2665
    gen_update_nip(ctx, ctx->nip - 4);
2666
    gen_addr_reg_index(ctx);
2667
    gen_op_load_xer_bc();
2668
    op_ldsts(stsw, rS(ctx->opcode));
2669
}
2670

    
2671
/***                        Memory synchronisation                         ***/
2672
/* eieio */
2673
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
2674
{
2675
}
2676

    
2677
/* isync */
2678
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
2679
{
2680
    GEN_STOP(ctx);
2681
}
2682

    
2683
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2684
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2685
#if defined(CONFIG_USER_ONLY)
2686
/* User-mode only */
2687
static GenOpFunc *gen_op_lwarx[] = {
2688
    &gen_op_lwarx_raw,
2689
    &gen_op_lwarx_le_raw,
2690
#if defined(TARGET_PPC64)
2691
    &gen_op_lwarx_64_raw,
2692
    &gen_op_lwarx_le_64_raw,
2693
#endif
2694
};
2695
static GenOpFunc *gen_op_stwcx[] = {
2696
    &gen_op_stwcx_raw,
2697
    &gen_op_stwcx_le_raw,
2698
#if defined(TARGET_PPC64)
2699
    &gen_op_stwcx_64_raw,
2700
    &gen_op_stwcx_le_64_raw,
2701
#endif
2702
};
2703
#else
2704
#if defined(TARGET_PPC64)
2705
/* Full system - 64 bits mode */
2706
static GenOpFunc *gen_op_lwarx[] = {
2707
    &gen_op_lwarx_user,
2708
    &gen_op_lwarx_le_user,
2709
    &gen_op_lwarx_64_user,
2710
    &gen_op_lwarx_le_64_user,
2711
    &gen_op_lwarx_kernel,
2712
    &gen_op_lwarx_le_kernel,
2713
    &gen_op_lwarx_64_kernel,
2714
    &gen_op_lwarx_le_64_kernel,
2715
#if defined(TARGET_PPC64H)
2716
    &gen_op_lwarx_hypv,
2717
    &gen_op_lwarx_le_hypv,
2718
    &gen_op_lwarx_64_hypv,
2719
    &gen_op_lwarx_le_64_hypv,
2720
#endif
2721
};
2722
static GenOpFunc *gen_op_stwcx[] = {
2723
    &gen_op_stwcx_user,
2724
    &gen_op_stwcx_le_user,
2725
    &gen_op_stwcx_64_user,
2726
    &gen_op_stwcx_le_64_user,
2727
    &gen_op_stwcx_kernel,
2728
    &gen_op_stwcx_le_kernel,
2729
    &gen_op_stwcx_64_kernel,
2730
    &gen_op_stwcx_le_64_kernel,
2731
#if defined(TARGET_PPC64H)
2732
    &gen_op_stwcx_hypv,
2733
    &gen_op_stwcx_le_hypv,
2734
    &gen_op_stwcx_64_hypv,
2735
    &gen_op_stwcx_le_64_hypv,
2736
#endif
2737
};
2738
#else
2739
/* Full system - 32 bits mode */
2740
static GenOpFunc *gen_op_lwarx[] = {
2741
    &gen_op_lwarx_user,
2742
    &gen_op_lwarx_le_user,
2743
    &gen_op_lwarx_kernel,
2744
    &gen_op_lwarx_le_kernel,
2745
};
2746
static GenOpFunc *gen_op_stwcx[] = {
2747
    &gen_op_stwcx_user,
2748
    &gen_op_stwcx_le_user,
2749
    &gen_op_stwcx_kernel,
2750
    &gen_op_stwcx_le_kernel,
2751
};
2752
#endif
2753
#endif
2754

    
2755
/* lwarx */
2756
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2757
{
2758
    /* NIP cannot be restored if the memory exception comes from an helper */
2759
    gen_update_nip(ctx, ctx->nip - 4);
2760
    gen_addr_reg_index(ctx);
2761
    op_lwarx();
2762
    gen_op_store_T1_gpr(rD(ctx->opcode));
2763
}
2764

    
2765
/* stwcx. */
2766
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2767
{
2768
    /* NIP cannot be restored if the memory exception comes from an helper */
2769
    gen_update_nip(ctx, ctx->nip - 4);
2770
    gen_addr_reg_index(ctx);
2771
    gen_op_load_gpr_T1(rS(ctx->opcode));
2772
    op_stwcx();
2773
}
2774

    
2775
#if defined(TARGET_PPC64)
2776
#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2777
#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2778
#if defined(CONFIG_USER_ONLY)
2779
/* User-mode only */
2780
static GenOpFunc *gen_op_ldarx[] = {
2781
    &gen_op_ldarx_raw,
2782
    &gen_op_ldarx_le_raw,
2783
    &gen_op_ldarx_64_raw,
2784
    &gen_op_ldarx_le_64_raw,
2785
};
2786
static GenOpFunc *gen_op_stdcx[] = {
2787
    &gen_op_stdcx_raw,
2788
    &gen_op_stdcx_le_raw,
2789
    &gen_op_stdcx_64_raw,
2790
    &gen_op_stdcx_le_64_raw,
2791
};
2792
#else
2793
/* Full system */
2794
static GenOpFunc *gen_op_ldarx[] = {
2795
    &gen_op_ldarx_user,
2796
    &gen_op_ldarx_le_user,
2797
    &gen_op_ldarx_64_user,
2798
    &gen_op_ldarx_le_64_user,
2799
    &gen_op_ldarx_kernel,
2800
    &gen_op_ldarx_le_kernel,
2801
    &gen_op_ldarx_64_kernel,
2802
    &gen_op_ldarx_le_64_kernel,
2803
#if defined(TARGET_PPC64H)
2804
    &gen_op_ldarx_hypv,
2805
    &gen_op_ldarx_le_hypv,
2806
    &gen_op_ldarx_64_hypv,
2807
    &gen_op_ldarx_le_64_hypv,
2808
#endif
2809
};
2810
static GenOpFunc *gen_op_stdcx[] = {
2811
    &gen_op_stdcx_user,
2812
    &gen_op_stdcx_le_user,
2813
    &gen_op_stdcx_64_user,
2814
    &gen_op_stdcx_le_64_user,
2815
    &gen_op_stdcx_kernel,
2816
    &gen_op_stdcx_le_kernel,
2817
    &gen_op_stdcx_64_kernel,
2818
    &gen_op_stdcx_le_64_kernel,
2819
#if defined(TARGET_PPC64H)
2820
    &gen_op_stdcx_hypv,
2821
    &gen_op_stdcx_le_hypv,
2822
    &gen_op_stdcx_64_hypv,
2823
    &gen_op_stdcx_le_64_hypv,
2824
#endif
2825
};
2826
#endif
2827

    
2828
/* ldarx */
2829
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2830
{
2831
    /* NIP cannot be restored if the memory exception comes from an helper */
2832
    gen_update_nip(ctx, ctx->nip - 4);
2833
    gen_addr_reg_index(ctx);
2834
    op_ldarx();
2835
    gen_op_store_T1_gpr(rD(ctx->opcode));
2836
}
2837

    
2838
/* stdcx. */
2839
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2840
{
2841
    /* NIP cannot be restored if the memory exception comes from an helper */
2842
    gen_update_nip(ctx, ctx->nip - 4);
2843
    gen_addr_reg_index(ctx);
2844
    gen_op_load_gpr_T1(rS(ctx->opcode));
2845
    op_stdcx();
2846
}
2847
#endif /* defined(TARGET_PPC64) */
2848

    
2849
/* sync */
2850
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
2851
{
2852
}
2853

    
2854
/* wait */
2855
GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2856
{
2857
    /* Stop translation, as the CPU is supposed to sleep from now */
2858
    gen_op_wait();
2859
    GEN_EXCP(ctx, EXCP_HLT, 1);
2860
}
2861

    
2862
/***                         Floating-point load                           ***/
2863
#define GEN_LDF(width, opc, type)                                             \
2864
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type)                      \
2865
{                                                                             \
2866
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2867
        GEN_EXCP_NO_FP(ctx);                                                  \
2868
        return;                                                               \
2869
    }                                                                         \
2870
    gen_addr_imm_index(ctx, 0);                                               \
2871
    op_ldst(l##width);                                                        \
2872
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2873
}
2874

    
2875
#define GEN_LDUF(width, opc, type)                                            \
2876
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
2877
{                                                                             \
2878
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2879
        GEN_EXCP_NO_FP(ctx);                                                  \
2880
        return;                                                               \
2881
    }                                                                         \
2882
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2883
        GEN_EXCP_INVAL(ctx);                                                  \
2884
        return;                                                               \
2885
    }                                                                         \
2886
    gen_addr_imm_index(ctx, 0);                                               \
2887
    op_ldst(l##width);                                                        \
2888
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2889
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2890
}
2891

    
2892
#define GEN_LDUXF(width, opc, type)                                           \
2893
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                  \
2894
{                                                                             \
2895
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2896
        GEN_EXCP_NO_FP(ctx);                                                  \
2897
        return;                                                               \
2898
    }                                                                         \
2899
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2900
        GEN_EXCP_INVAL(ctx);                                                  \
2901
        return;                                                               \
2902
    }                                                                         \
2903
    gen_addr_reg_index(ctx);                                                  \
2904
    op_ldst(l##width);                                                        \
2905
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2906
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2907
}
2908

    
2909
#define GEN_LDXF(width, opc2, opc3, type)                                     \
2910
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type)                  \
2911
{                                                                             \
2912
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2913
        GEN_EXCP_NO_FP(ctx);                                                  \
2914
        return;                                                               \
2915
    }                                                                         \
2916
    gen_addr_reg_index(ctx);                                                  \
2917
    op_ldst(l##width);                                                        \
2918
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2919
}
2920

    
2921
#define GEN_LDFS(width, op, type)                                             \
2922
OP_LD_TABLE(width);                                                           \
2923
GEN_LDF(width, op | 0x20, type);                                              \
2924
GEN_LDUF(width, op | 0x21, type);                                             \
2925
GEN_LDUXF(width, op | 0x01, type);                                            \
2926
GEN_LDXF(width, 0x17, op | 0x00, type)
2927

    
2928
/* lfd lfdu lfdux lfdx */
2929
GEN_LDFS(fd, 0x12, PPC_FLOAT);
2930
/* lfs lfsu lfsux lfsx */
2931
GEN_LDFS(fs, 0x10, PPC_FLOAT);
2932

    
2933
/***                         Floating-point store                          ***/
2934
#define GEN_STF(width, opc, type)                                             \
2935
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
2936
{                                                                             \
2937
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2938
        GEN_EXCP_NO_FP(ctx);                                                  \
2939
        return;                                                               \
2940
    }                                                                         \
2941
    gen_addr_imm_index(ctx, 0);                                               \
2942
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2943
    op_ldst(st##width);                                                       \
2944
}
2945

    
2946
#define GEN_STUF(width, opc, type)                                            \
2947
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
2948
{                                                                             \
2949
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2950
        GEN_EXCP_NO_FP(ctx);                                                  \
2951
        return;                                                               \
2952
    }                                                                         \
2953
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2954
        GEN_EXCP_INVAL(ctx);                                                  \
2955
        return;                                                               \
2956
    }                                                                         \
2957
    gen_addr_imm_index(ctx, 0);                                               \
2958
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2959
    op_ldst(st##width);                                                       \
2960
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2961
}
2962

    
2963
#define GEN_STUXF(width, opc, type)                                           \
2964
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                 \
2965
{                                                                             \
2966
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2967
        GEN_EXCP_NO_FP(ctx);                                                  \
2968
        return;                                                               \
2969
    }                                                                         \
2970
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2971
        GEN_EXCP_INVAL(ctx);                                                  \
2972
        return;                                                               \
2973
    }                                                                         \
2974
    gen_addr_reg_index(ctx);                                                  \
2975
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2976
    op_ldst(st##width);                                                       \
2977
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2978
}
2979

    
2980
#define GEN_STXF(width, opc2, opc3, type)                                     \
2981
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
2982
{                                                                             \
2983
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2984
        GEN_EXCP_NO_FP(ctx);                                                  \
2985
        return;                                                               \
2986
    }                                                                         \
2987
    gen_addr_reg_index(ctx);                                                  \
2988
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
2989
    op_ldst(st##width);                                                       \
2990
}
2991

    
2992
#define GEN_STFS(width, op, type)                                             \
2993
OP_ST_TABLE(width);                                                           \
2994
GEN_STF(width, op | 0x20, type);                                              \
2995
GEN_STUF(width, op | 0x21, type);                                             \
2996
GEN_STUXF(width, op | 0x01, type);                                            \
2997
GEN_STXF(width, 0x17, op | 0x00, type)
2998

    
2999
/* stfd stfdu stfdux stfdx */
3000
GEN_STFS(fd, 0x16, PPC_FLOAT);
3001
/* stfs stfsu stfsux stfsx */
3002
GEN_STFS(fs, 0x14, PPC_FLOAT);
3003

    
3004
/* Optional: */
3005
/* stfiwx */
3006
OP_ST_TABLE(fiwx);
3007
GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3008

    
3009
/***                                Branch                                 ***/
3010
static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3011
                                       target_ulong dest)
3012
{
3013
    TranslationBlock *tb;
3014
    tb = ctx->tb;
3015
    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3016
        if (n == 0)
3017
            gen_op_goto_tb0(TBPARAM(tb));
3018
        else
3019
            gen_op_goto_tb1(TBPARAM(tb));
3020
        gen_set_T1(dest);
3021
#if defined(TARGET_PPC64)
3022
        if (ctx->sf_mode)
3023
            gen_op_b_T1_64();
3024
        else
3025
#endif
3026
            gen_op_b_T1();
3027
        gen_op_set_T0((long)tb + n);
3028
        if (ctx->singlestep_enabled)
3029
            gen_op_debug();
3030
        gen_op_exit_tb();
3031
    } else {
3032
        gen_set_T1(dest);
3033
#if defined(TARGET_PPC64)
3034
        if (ctx->sf_mode)
3035
            gen_op_b_T1_64();
3036
        else
3037
#endif
3038
            gen_op_b_T1();
3039
        gen_op_reset_T0();
3040
        if (ctx->singlestep_enabled)
3041
            gen_op_debug();
3042
        gen_op_exit_tb();
3043
    }
3044
}
3045

    
3046
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3047
{
3048
#if defined(TARGET_PPC64)
3049
    if (ctx->sf_mode != 0 && (nip >> 32))
3050
        gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3051
    else
3052
#endif
3053
        gen_op_setlr(ctx->nip);
3054
}
3055

    
3056
/* b ba bl bla */
3057
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3058
{
3059
    target_ulong li, target;
3060

    
3061
    /* sign extend LI */
3062
#if defined(TARGET_PPC64)
3063
    if (ctx->sf_mode)
3064
        li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3065
    else
3066
#endif
3067
        li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3068
    if (likely(AA(ctx->opcode) == 0))
3069
        target = ctx->nip + li - 4;
3070
    else
3071
        target = li;
3072
#if defined(TARGET_PPC64)
3073
    if (!ctx->sf_mode)
3074
        target = (uint32_t)target;
3075
#endif
3076
    if (LK(ctx->opcode))
3077
        gen_setlr(ctx, ctx->nip);
3078
    gen_goto_tb(ctx, 0, target);
3079
    ctx->exception = POWERPC_EXCP_BRANCH;
3080
}
3081

    
3082
#define BCOND_IM  0
3083
#define BCOND_LR  1
3084
#define BCOND_CTR 2
3085

    
3086
static always_inline void gen_bcond (DisasContext *ctx, int type)
3087
{
3088
    target_ulong target = 0;
3089
    target_ulong li;
3090
    uint32_t bo = BO(ctx->opcode);
3091
    uint32_t bi = BI(ctx->opcode);
3092
    uint32_t mask;
3093

    
3094
    if ((bo & 0x4) == 0)
3095
        gen_op_dec_ctr();
3096
    switch(type) {
3097
    case BCOND_IM:
3098
        li = (target_long)((int16_t)(BD(ctx->opcode)));
3099
        if (likely(AA(ctx->opcode) == 0)) {
3100
            target = ctx->nip + li - 4;
3101
        } else {
3102
            target = li;
3103
        }
3104
#if defined(TARGET_PPC64)
3105
        if (!ctx->sf_mode)
3106
            target = (uint32_t)target;
3107
#endif
3108
        break;
3109
    case BCOND_CTR:
3110
        gen_op_movl_T1_ctr();
3111
        break;
3112
    default:
3113
    case BCOND_LR:
3114
        gen_op_movl_T1_lr();
3115
        break;
3116
    }
3117
    if (LK(ctx->opcode))
3118
        gen_setlr(ctx, ctx->nip);
3119
    if (bo & 0x10) {
3120
        /* No CR condition */
3121
        switch (bo & 0x6) {
3122
        case 0:
3123
#if defined(TARGET_PPC64)
3124
            if (ctx->sf_mode)
3125
                gen_op_test_ctr_64();
3126
            else
3127
#endif
3128
                gen_op_test_ctr();
3129
            break;
3130
        case 2:
3131
#if defined(TARGET_PPC64)
3132
            if (ctx->sf_mode)
3133
                gen_op_test_ctrz_64();
3134
            else
3135
#endif
3136
                gen_op_test_ctrz();
3137
            break;
3138
        default:
3139
        case 4:
3140
        case 6:
3141
            if (type == BCOND_IM) {
3142
                gen_goto_tb(ctx, 0, target);
3143
                goto out;
3144
            } else {
3145
#if defined(TARGET_PPC64)
3146
                if (ctx->sf_mode)
3147
                    gen_op_b_T1_64();
3148
                else
3149
#endif
3150
                    gen_op_b_T1();
3151
                gen_op_reset_T0();
3152
                goto no_test;
3153
            }
3154
            break;
3155
        }
3156
    } else {
3157
        mask = 1 << (3 - (bi & 0x03));
3158
        gen_op_load_crf_T0(bi >> 2);
3159
        if (bo & 0x8) {
3160
            switch (bo & 0x6) {
3161
            case 0:
3162
#if defined(TARGET_PPC64)
3163
                if (ctx->sf_mode)
3164
                    gen_op_test_ctr_true_64(mask);
3165
                else
3166
#endif
3167
                    gen_op_test_ctr_true(mask);
3168
                break;
3169
            case 2:
3170
#if defined(TARGET_PPC64)
3171
                if (ctx->sf_mode)
3172
                    gen_op_test_ctrz_true_64(mask);
3173
                else
3174
#endif
3175
                    gen_op_test_ctrz_true(mask);
3176
                break;
3177
            default:
3178
            case 4:
3179
            case 6:
3180
                gen_op_test_true(mask);
3181
                break;
3182
            }
3183
        } else {
3184
            switch (bo & 0x6) {
3185
            case 0:
3186
#if defined(TARGET_PPC64)
3187
                if (ctx->sf_mode)
3188
                    gen_op_test_ctr_false_64(mask);
3189
                else
3190
#endif
3191
                    gen_op_test_ctr_false(mask);
3192
                break;
3193
            case 2:
3194
#if defined(TARGET_PPC64)
3195
                if (ctx->sf_mode)
3196
                    gen_op_test_ctrz_false_64(mask);
3197
                else
3198
#endif
3199
                    gen_op_test_ctrz_false(mask);
3200
                break;
3201
            default:
3202
            case 4:
3203
            case 6:
3204
                gen_op_test_false(mask);
3205
                break;
3206
            }
3207
        }
3208
    }
3209
    if (type == BCOND_IM) {
3210
        int l1 = gen_new_label();
3211
        gen_op_jz_T0(l1);
3212
        gen_goto_tb(ctx, 0, target);
3213
        gen_set_label(l1);
3214
        gen_goto_tb(ctx, 1, ctx->nip);
3215
    } else {
3216
#if defined(TARGET_PPC64)
3217
        if (ctx->sf_mode)
3218
            gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3219
        else
3220
#endif
3221
            gen_op_btest_T1(ctx->nip);
3222
        gen_op_reset_T0();
3223
    no_test:
3224
        if (ctx->singlestep_enabled)
3225
            gen_op_debug();
3226
        gen_op_exit_tb();
3227
    }
3228
 out:
3229
    ctx->exception = POWERPC_EXCP_BRANCH;
3230
}
3231

    
3232
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3233
{
3234
    gen_bcond(ctx, BCOND_IM);
3235
}
3236

    
3237
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3238
{
3239
    gen_bcond(ctx, BCOND_CTR);
3240
}
3241

    
3242
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3243
{
3244
    gen_bcond(ctx, BCOND_LR);
3245
}
3246

    
3247
/***                      Condition register logical                       ***/
3248
#define GEN_CRLOGIC(op, opc)                                                  \
3249
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                 \
3250
{                                                                             \
3251
    gen_op_load_crf_T0(crbA(ctx->opcode) >> 2);                               \
3252
    gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03));                         \
3253
    gen_op_load_crf_T1(crbB(ctx->opcode) >> 2);                               \
3254
    gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03));                         \
3255
    gen_op_##op();                                                            \
3256
    gen_op_load_crf_T1(crbD(ctx->opcode) >> 2);                               \
3257
    gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))),                \
3258
                     3 - (crbD(ctx->opcode) & 0x03));                         \
3259
    gen_op_store_T1_crf(crbD(ctx->opcode) >> 2);                              \
3260
}
3261

    
3262
/* crand */
3263
GEN_CRLOGIC(and, 0x08);
3264
/* crandc */
3265
GEN_CRLOGIC(andc, 0x04);
3266
/* creqv */
3267
GEN_CRLOGIC(eqv, 0x09);
3268
/* crnand */
3269
GEN_CRLOGIC(nand, 0x07);
3270
/* crnor */
3271
GEN_CRLOGIC(nor, 0x01);
3272
/* cror */
3273
GEN_CRLOGIC(or, 0x0E);
3274
/* crorc */
3275
GEN_CRLOGIC(orc, 0x0D);
3276
/* crxor */
3277
GEN_CRLOGIC(xor, 0x06);
3278
/* mcrf */
3279
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3280
{
3281
    gen_op_load_crf_T0(crfS(ctx->opcode));
3282
    gen_op_store_T0_crf(crfD(ctx->opcode));
3283
}
3284

    
3285
/***                           System linkage                              ***/
3286
/* rfi (supervisor only) */
3287
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3288
{
3289
#if defined(CONFIG_USER_ONLY)
3290
    GEN_EXCP_PRIVOPC(ctx);
3291
#else
3292
    /* Restore CPU state */
3293
    if (unlikely(!ctx->supervisor)) {
3294
        GEN_EXCP_PRIVOPC(ctx);
3295
        return;
3296
    }
3297
    gen_op_rfi();
3298
    GEN_SYNC(ctx);
3299
#endif
3300
}
3301

    
3302
#if defined(TARGET_PPC64)
3303
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3304
{
3305
#if defined(CONFIG_USER_ONLY)
3306
    GEN_EXCP_PRIVOPC(ctx);
3307
#else
3308
    /* Restore CPU state */
3309
    if (unlikely(!ctx->supervisor)) {
3310
        GEN_EXCP_PRIVOPC(ctx);
3311
        return;
3312
    }
3313
    gen_op_rfid();
3314
    GEN_SYNC(ctx);
3315
#endif
3316
}
3317
#endif
3318

    
3319
#if defined(TARGET_PPC64H)
3320
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
3321
{
3322
#if defined(CONFIG_USER_ONLY)
3323
    GEN_EXCP_PRIVOPC(ctx);
3324
#else
3325
    /* Restore CPU state */
3326
    if (unlikely(ctx->supervisor <= 1)) {
3327
        GEN_EXCP_PRIVOPC(ctx);
3328
        return;
3329
    }
3330
    gen_op_hrfid();
3331
    GEN_SYNC(ctx);
3332
#endif
3333
}
3334
#endif
3335

    
3336
/* sc */
3337
#if defined(CONFIG_USER_ONLY)
3338
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3339
#else
3340
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3341
#endif
3342
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3343
{
3344
    uint32_t lev;
3345

    
3346
    lev = (ctx->opcode >> 5) & 0x7F;
3347
    GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3348
}
3349

    
3350
/***                                Trap                                   ***/
3351
/* tw */
3352
GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3353
{
3354
    gen_op_load_gpr_T0(rA(ctx->opcode));
3355
    gen_op_load_gpr_T1(rB(ctx->opcode));
3356
    /* Update the nip since this might generate a trap exception */
3357
    gen_update_nip(ctx, ctx->nip);
3358
    gen_op_tw(TO(ctx->opcode));
3359
}
3360

    
3361
/* twi */
3362
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3363
{
3364
    gen_op_load_gpr_T0(rA(ctx->opcode));
3365
    gen_set_T1(SIMM(ctx->opcode));
3366
    /* Update the nip since this might generate a trap exception */
3367
    gen_update_nip(ctx, ctx->nip);
3368
    gen_op_tw(TO(ctx->opcode));
3369
}
3370

    
3371
#if defined(TARGET_PPC64)
3372
/* td */
3373
GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3374
{
3375
    gen_op_load_gpr_T0(rA(ctx->opcode));
3376
    gen_op_load_gpr_T1(rB(ctx->opcode));
3377
    /* Update the nip since this might generate a trap exception */
3378
    gen_update_nip(ctx, ctx->nip);
3379
    gen_op_td(TO(ctx->opcode));
3380
}
3381

    
3382
/* tdi */
3383
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3384
{
3385
    gen_op_load_gpr_T0(rA(ctx->opcode));
3386
    gen_set_T1(SIMM(ctx->opcode));
3387
    /* Update the nip since this might generate a trap exception */
3388
    gen_update_nip(ctx, ctx->nip);
3389
    gen_op_td(TO(ctx->opcode));
3390
}
3391
#endif
3392

    
3393
/***                          Processor control                            ***/
3394
/* mcrxr */
3395
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3396
{
3397
    gen_op_load_xer_cr();
3398
    gen_op_store_T0_crf(crfD(ctx->opcode));
3399
    gen_op_clear_xer_ov();
3400
    gen_op_clear_xer_ca();
3401
}
3402

    
3403
/* mfcr */
3404
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3405
{
3406
    uint32_t crm, crn;
3407

    
3408
    if (likely(ctx->opcode & 0x00100000)) {
3409
        crm = CRM(ctx->opcode);
3410
        if (likely((crm ^ (crm - 1)) == 0)) {
3411
            crn = ffs(crm);
3412
            gen_op_load_cro(7 - crn);
3413
        }
3414
    } else {
3415
        gen_op_load_cr();
3416
    }
3417
    gen_op_store_T0_gpr(rD(ctx->opcode));
3418
}
3419

    
3420
/* mfmsr */
3421
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3422
{
3423
#if defined(CONFIG_USER_ONLY)
3424
    GEN_EXCP_PRIVREG(ctx);
3425
#else
3426
    if (unlikely(!ctx->supervisor)) {
3427
        GEN_EXCP_PRIVREG(ctx);
3428
        return;
3429
    }
3430
    gen_op_load_msr();
3431
    gen_op_store_T0_gpr(rD(ctx->opcode));
3432
#endif
3433
}
3434

    
3435
#if 0
3436
#define SPR_NOACCESS ((void *)(-1))
3437
#else
3438
static void spr_noaccess (void *opaque, int sprn)
3439
{
3440
    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3441
    printf("ERROR: try to access SPR %d !\n", sprn);
3442
}
3443
#define SPR_NOACCESS (&spr_noaccess)
3444
#endif
3445

    
3446
/* mfspr */
3447
static always_inline void gen_op_mfspr (DisasContext *ctx)
3448
{
3449
    void (*read_cb)(void *opaque, int sprn);
3450
    uint32_t sprn = SPR(ctx->opcode);
3451

    
3452
#if !defined(CONFIG_USER_ONLY)
3453
#if defined(TARGET_PPC64H)
3454
    if (ctx->supervisor == 2)
3455
        read_cb = ctx->spr_cb[sprn].hea_read;
3456
    else
3457
#endif
3458
    if (ctx->supervisor)
3459
        read_cb = ctx->spr_cb[sprn].oea_read;
3460
    else
3461
#endif
3462
        read_cb = ctx->spr_cb[sprn].uea_read;
3463
    if (likely(read_cb != NULL)) {
3464
        if (likely(read_cb != SPR_NOACCESS)) {
3465
            (*read_cb)(ctx, sprn);
3466
            gen_op_store_T0_gpr(rD(ctx->opcode));
3467
        } else {
3468
            /* Privilege exception */
3469
            if (loglevel != 0) {
3470
                fprintf(logfile, "Trying to read privileged spr %d %03x\n",
3471
                        sprn, sprn);
3472
            }
3473
            printf("Trying to read privileged spr %d %03x\n", sprn, sprn);
3474
            GEN_EXCP_PRIVREG(ctx);
3475
        }
3476
    } else {
3477
        /* Not defined */
3478
        if (loglevel != 0) {
3479
            fprintf(logfile, "Trying to read invalid spr %d %03x\n",
3480
                    sprn, sprn);
3481
        }
3482
        printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
3483
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3484
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3485
    }
3486
}
3487

    
3488
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3489
{
3490
    gen_op_mfspr(ctx);
3491
}
3492

    
3493
/* mftb */
3494
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3495
{
3496
    gen_op_mfspr(ctx);
3497
}
3498

    
3499
/* mtcrf */
3500
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3501
{
3502
    uint32_t crm, crn;
3503

    
3504
    gen_op_load_gpr_T0(rS(ctx->opcode));
3505
    crm = CRM(ctx->opcode);
3506
    if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3507
        crn = ffs(crm);
3508
        gen_op_srli_T0(crn * 4);
3509
        gen_op_andi_T0(0xF);
3510
        gen_op_store_cro(7 - crn);
3511
    } else {
3512
        gen_op_store_cr(crm);
3513
    }
3514
}
3515

    
3516
/* mtmsr */
3517
#if defined(TARGET_PPC64)
3518
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3519
{
3520
#if defined(CONFIG_USER_ONLY)
3521
    GEN_EXCP_PRIVREG(ctx);
3522
#else
3523
    if (unlikely(!ctx->supervisor)) {
3524
        GEN_EXCP_PRIVREG(ctx);
3525
        return;
3526
    }
3527
    gen_op_load_gpr_T0(rS(ctx->opcode));
3528
    if (ctx->opcode & 0x00010000) {
3529
        /* Special form that does not need any synchronisation */
3530
        gen_op_update_riee();
3531
    } else {
3532
        /* XXX: we need to update nip before the store
3533
         *      if we enter power saving mode, we will exit the loop
3534
         *      directly from ppc_store_msr
3535
         */
3536
        gen_update_nip(ctx, ctx->nip);
3537
        gen_op_store_msr();
3538
        /* Must stop the translation as machine state (may have) changed */
3539
        /* Note that mtmsr is not always defined as context-synchronizing */
3540
        ctx->exception = POWERPC_EXCP_STOP;
3541
    }
3542
#endif
3543
}
3544
#endif
3545

    
3546
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3547
{
3548
#if defined(CONFIG_USER_ONLY)
3549
    GEN_EXCP_PRIVREG(ctx);
3550
#else
3551
    if (unlikely(!ctx->supervisor)) {
3552
        GEN_EXCP_PRIVREG(ctx);
3553
        return;
3554
    }
3555
    gen_op_load_gpr_T0(rS(ctx->opcode));
3556
    if (ctx->opcode & 0x00010000) {
3557
        /* Special form that does not need any synchronisation */
3558
        gen_op_update_riee();
3559
    } else {
3560
        /* XXX: we need to update nip before the store
3561
         *      if we enter power saving mode, we will exit the loop
3562
         *      directly from ppc_store_msr
3563
         */
3564
        gen_update_nip(ctx, ctx->nip);
3565
#if defined(TARGET_PPC64)
3566
        if (!ctx->sf_mode)
3567
            gen_op_store_msr_32();
3568
        else
3569
#endif
3570
            gen_op_store_msr();
3571
        /* Must stop the translation as machine state (may have) changed */
3572
        /* Note that mtmsrd is not always defined as context-synchronizing */
3573
        ctx->exception = POWERPC_EXCP_STOP;
3574
    }
3575
#endif
3576
}
3577

    
3578
/* mtspr */
3579
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3580
{
3581
    void (*write_cb)(void *opaque, int sprn);
3582
    uint32_t sprn = SPR(ctx->opcode);
3583

    
3584
#if !defined(CONFIG_USER_ONLY)
3585
#if defined(TARGET_PPC64H)
3586
    if (ctx->supervisor == 2)
3587
        write_cb = ctx->spr_cb[sprn].hea_write;
3588
    else
3589
#endif
3590
    if (ctx->supervisor)
3591
        write_cb = ctx->spr_cb[sprn].oea_write;
3592
    else
3593
#endif
3594
        write_cb = ctx->spr_cb[sprn].uea_write;
3595
    if (likely(write_cb != NULL)) {
3596
        if (likely(write_cb != SPR_NOACCESS)) {
3597
            gen_op_load_gpr_T0(rS(ctx->opcode));
3598
            (*write_cb)(ctx, sprn);
3599
        } else {
3600
            /* Privilege exception */
3601
            if (loglevel != 0) {
3602
                fprintf(logfile, "Trying to write privileged spr %d %03x\n",
3603
                        sprn, sprn);
3604
            }
3605
            printf("Trying to write privileged spr %d %03x\n", sprn, sprn);
3606
            GEN_EXCP_PRIVREG(ctx);
3607
        }
3608
    } else {
3609
        /* Not defined */
3610
        if (loglevel != 0) {
3611
            fprintf(logfile, "Trying to write invalid spr %d %03x\n",
3612
                    sprn, sprn);
3613
        }
3614
        printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
3615
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3616
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3617
    }
3618
}
3619

    
3620
/***                         Cache management                              ***/
3621
/* For now, all those will be implemented as nop:
3622
 * this is valid, regarding the PowerPC specs...
3623
 * We just have to flush tb while invalidating instruction cache lines...
3624
 */
3625
/* dcbf */
3626
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
3627
{
3628
    gen_addr_reg_index(ctx);
3629
    op_ldst(lbz);
3630
}
3631

    
3632
/* dcbi (Supervisor only) */
3633
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3634
{
3635
#if defined(CONFIG_USER_ONLY)
3636
    GEN_EXCP_PRIVOPC(ctx);
3637
#else
3638
    if (unlikely(!ctx->supervisor)) {
3639
        GEN_EXCP_PRIVOPC(ctx);
3640
        return;
3641
    }
3642
    gen_addr_reg_index(ctx);
3643
    /* XXX: specification says this should be treated as a store by the MMU */
3644
    //op_ldst(lbz);
3645
    op_ldst(stb);
3646
#endif
3647
}
3648

    
3649
/* dcdst */
3650
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
3651
{
3652
    /* XXX: specification say this is treated as a load by the MMU */
3653
    gen_addr_reg_index(ctx);
3654
    op_ldst(lbz);
3655
}
3656

    
3657
/* dcbt */
3658
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
3659
{
3660
    /* interpreted as no-op */
3661
    /* XXX: specification say this is treated as a load by the MMU
3662
     *      but does not generate any exception
3663
     */
3664
}
3665

    
3666
/* dcbtst */
3667
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3668
{
3669
    /* interpreted as no-op */
3670
    /* XXX: specification say this is treated as a load by the MMU
3671
     *      but does not generate any exception
3672
     */
3673
}
3674

    
3675
/* dcbz */
3676
#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3677
#if defined(CONFIG_USER_ONLY)
3678
/* User-mode only */
3679
static GenOpFunc *gen_op_dcbz[4][4] = {
3680
    {
3681
        &gen_op_dcbz_l32_raw,
3682
        &gen_op_dcbz_l32_raw,
3683
#if defined(TARGET_PPC64)
3684
        &gen_op_dcbz_l32_64_raw,
3685
        &gen_op_dcbz_l32_64_raw,
3686
#endif
3687
    },
3688
    {
3689
        &gen_op_dcbz_l64_raw,
3690
        &gen_op_dcbz_l64_raw,
3691
#if defined(TARGET_PPC64)
3692
        &gen_op_dcbz_l64_64_raw,
3693
        &gen_op_dcbz_l64_64_raw,
3694
#endif
3695
    },
3696
    {
3697
        &gen_op_dcbz_l128_raw,
3698
        &gen_op_dcbz_l128_raw,
3699
#if defined(TARGET_PPC64)
3700
        &gen_op_dcbz_l128_64_raw,
3701
        &gen_op_dcbz_l128_64_raw,
3702
#endif
3703
    },
3704
    {
3705
        &gen_op_dcbz_raw,
3706
        &gen_op_dcbz_raw,
3707
#if defined(TARGET_PPC64)
3708
        &gen_op_dcbz_64_raw,
3709
        &gen_op_dcbz_64_raw,
3710
#endif
3711
    },
3712
};
3713
#else
3714
#if defined(TARGET_PPC64)
3715
/* Full system - 64 bits mode */
3716
static GenOpFunc *gen_op_dcbz[4][12] = {
3717
    {
3718
        &gen_op_dcbz_l32_user,
3719
        &gen_op_dcbz_l32_user,
3720
        &gen_op_dcbz_l32_64_user,
3721
        &gen_op_dcbz_l32_64_user,
3722
        &gen_op_dcbz_l32_kernel,
3723
        &gen_op_dcbz_l32_kernel,
3724
        &gen_op_dcbz_l32_64_kernel,
3725
        &gen_op_dcbz_l32_64_kernel,
3726
#if defined(TARGET_PPC64H)
3727
        &gen_op_dcbz_l32_hypv,
3728
        &gen_op_dcbz_l32_hypv,
3729
        &gen_op_dcbz_l32_64_hypv,
3730
        &gen_op_dcbz_l32_64_hypv,
3731
#endif
3732
    },
3733
    {
3734
        &gen_op_dcbz_l64_user,
3735
        &gen_op_dcbz_l64_user,
3736
        &gen_op_dcbz_l64_64_user,
3737
        &gen_op_dcbz_l64_64_user,
3738
        &gen_op_dcbz_l64_kernel,
3739
        &gen_op_dcbz_l64_kernel,
3740
        &gen_op_dcbz_l64_64_kernel,
3741
        &gen_op_dcbz_l64_64_kernel,
3742
#if defined(TARGET_PPC64H)
3743
        &gen_op_dcbz_l64_hypv,
3744
        &gen_op_dcbz_l64_hypv,
3745
        &gen_op_dcbz_l64_64_hypv,
3746
        &gen_op_dcbz_l64_64_hypv,
3747
#endif
3748
    },
3749
    {
3750
        &gen_op_dcbz_l128_user,
3751
        &gen_op_dcbz_l128_user,
3752
        &gen_op_dcbz_l128_64_user,
3753
        &gen_op_dcbz_l128_64_user,
3754
        &gen_op_dcbz_l128_kernel,
3755
        &gen_op_dcbz_l128_kernel,
3756
        &gen_op_dcbz_l128_64_kernel,
3757
        &gen_op_dcbz_l128_64_kernel,
3758
#if defined(TARGET_PPC64H)
3759
        &gen_op_dcbz_l128_hypv,
3760
        &gen_op_dcbz_l128_hypv,
3761
        &gen_op_dcbz_l128_64_hypv,
3762
        &gen_op_dcbz_l128_64_hypv,
3763
#endif
3764
    },
3765
    {
3766
        &gen_op_dcbz_user,
3767
        &gen_op_dcbz_user,
3768
        &gen_op_dcbz_64_user,
3769
        &gen_op_dcbz_64_user,
3770
        &gen_op_dcbz_kernel,
3771
        &gen_op_dcbz_kernel,
3772
        &gen_op_dcbz_64_kernel,
3773
        &gen_op_dcbz_64_kernel,
3774
#if defined(TARGET_PPC64H)
3775
        &gen_op_dcbz_hypv,
3776
        &gen_op_dcbz_hypv,
3777
        &gen_op_dcbz_64_hypv,
3778
        &gen_op_dcbz_64_hypv,
3779
#endif
3780
    },
3781
};
3782
#else
3783
/* Full system - 32 bits mode */
3784
static GenOpFunc *gen_op_dcbz[4][4] = {
3785
    {
3786
        &gen_op_dcbz_l32_user,
3787
        &gen_op_dcbz_l32_user,
3788
        &gen_op_dcbz_l32_kernel,
3789
        &gen_op_dcbz_l32_kernel,
3790
    },
3791
    {
3792
        &gen_op_dcbz_l64_user,
3793
        &gen_op_dcbz_l64_user,
3794
        &gen_op_dcbz_l64_kernel,
3795
        &gen_op_dcbz_l64_kernel,
3796
    },
3797
    {
3798
        &gen_op_dcbz_l128_user,
3799
        &gen_op_dcbz_l128_user,
3800
        &gen_op_dcbz_l128_kernel,
3801
        &gen_op_dcbz_l128_kernel,
3802
    },
3803
    {
3804
        &gen_op_dcbz_user,
3805
        &gen_op_dcbz_user,
3806
        &gen_op_dcbz_kernel,
3807
        &gen_op_dcbz_kernel,
3808
    },
3809
};
3810
#endif
3811
#endif
3812

    
3813
static always_inline void handler_dcbz (DisasContext *ctx,
3814
                                        int dcache_line_size)
3815
{
3816
    int n;
3817

    
3818
    switch (dcache_line_size) {
3819
    case 32:
3820
        n = 0;
3821
        break;
3822
    case 64:
3823
        n = 1;
3824
        break;
3825
    case 128:
3826
        n = 2;
3827
        break;
3828
    default:
3829
        n = 3;
3830
        break;
3831
    }
3832
    op_dcbz(n);
3833
}
3834

    
3835
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3836
{
3837
    gen_addr_reg_index(ctx);
3838
    handler_dcbz(ctx, ctx->dcache_line_size);
3839
    gen_op_check_reservation();
3840
}
3841

    
3842
GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3843
{
3844
    gen_addr_reg_index(ctx);
3845
    if (ctx->opcode & 0x00200000)
3846
        handler_dcbz(ctx, ctx->dcache_line_size);
3847
    else
3848
        handler_dcbz(ctx, -1);
3849
    gen_op_check_reservation();
3850
}
3851

    
3852
/* icbi */
3853
#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3854
#if defined(CONFIG_USER_ONLY)
3855
/* User-mode only */
3856
static GenOpFunc *gen_op_icbi[] = {
3857
    &gen_op_icbi_raw,
3858
    &gen_op_icbi_raw,
3859
#if defined(TARGET_PPC64)
3860
    &gen_op_icbi_64_raw,
3861
    &gen_op_icbi_64_raw,
3862
#endif
3863
};
3864
#else
3865
/* Full system - 64 bits mode */
3866
#if defined(TARGET_PPC64)
3867
static GenOpFunc *gen_op_icbi[] = {
3868
    &gen_op_icbi_user,
3869
    &gen_op_icbi_user,
3870
    &gen_op_icbi_64_user,
3871
    &gen_op_icbi_64_user,
3872
    &gen_op_icbi_kernel,
3873
    &gen_op_icbi_kernel,
3874
    &gen_op_icbi_64_kernel,
3875
    &gen_op_icbi_64_kernel,
3876
#if defined(TARGET_PPC64H)
3877
    &gen_op_icbi_hypv,
3878
    &gen_op_icbi_hypv,
3879
    &gen_op_icbi_64_hypv,
3880
    &gen_op_icbi_64_hypv,
3881
#endif
3882
};
3883
#else
3884
/* Full system - 32 bits mode */
3885
static GenOpFunc *gen_op_icbi[] = {
3886
    &gen_op_icbi_user,
3887
    &gen_op_icbi_user,
3888
    &gen_op_icbi_kernel,
3889
    &gen_op_icbi_kernel,
3890
};
3891
#endif
3892
#endif
3893

    
3894
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
3895
{
3896
    /* NIP cannot be restored if the memory exception comes from an helper */
3897
    gen_update_nip(ctx, ctx->nip - 4);
3898
    gen_addr_reg_index(ctx);
3899
    op_icbi();
3900
}
3901

    
3902
/* Optional: */
3903
/* dcba */
3904
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
3905
{
3906
    /* interpreted as no-op */
3907
    /* XXX: specification say this is treated as a store by the MMU
3908
     *      but does not generate any exception
3909
     */
3910
}
3911

    
3912
/***                    Segment register manipulation                      ***/
3913
/* Supervisor only: */
3914
/* mfsr */
3915
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3916
{
3917
#if defined(CONFIG_USER_ONLY)
3918
    GEN_EXCP_PRIVREG(ctx);
3919
#else
3920
    if (unlikely(!ctx->supervisor)) {
3921
        GEN_EXCP_PRIVREG(ctx);
3922
        return;
3923
    }
3924
    gen_op_set_T1(SR(ctx->opcode));
3925
    gen_op_load_sr();
3926
    gen_op_store_T0_gpr(rD(ctx->opcode));
3927
#endif
3928
}
3929

    
3930
/* mfsrin */
3931
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
3932
{
3933
#if defined(CONFIG_USER_ONLY)
3934
    GEN_EXCP_PRIVREG(ctx);
3935
#else
3936
    if (unlikely(!ctx->supervisor)) {
3937
        GEN_EXCP_PRIVREG(ctx);
3938
        return;
3939
    }
3940
    gen_op_load_gpr_T1(rB(ctx->opcode));
3941
    gen_op_srli_T1(28);
3942
    gen_op_load_sr();
3943
    gen_op_store_T0_gpr(rD(ctx->opcode));
3944
#endif
3945
}
3946

    
3947
/* mtsr */
3948
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
3949
{
3950
#if defined(CONFIG_USER_ONLY)
3951
    GEN_EXCP_PRIVREG(ctx);
3952
#else
3953
    if (unlikely(!ctx->supervisor)) {
3954
        GEN_EXCP_PRIVREG(ctx);
3955
        return;
3956
    }
3957
    gen_op_load_gpr_T0(rS(ctx->opcode));
3958
    gen_op_set_T1(SR(ctx->opcode));
3959
    gen_op_store_sr();
3960
#endif
3961
}
3962

    
3963
/* mtsrin */
3964
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
3965
{
3966
#if defined(CONFIG_USER_ONLY)
3967
    GEN_EXCP_PRIVREG(ctx);
3968
#else
3969
    if (unlikely(!ctx->supervisor)) {
3970
        GEN_EXCP_PRIVREG(ctx);
3971
        return;
3972
    }
3973
    gen_op_load_gpr_T0(rS(ctx->opcode));
3974
    gen_op_load_gpr_T1(rB(ctx->opcode));
3975
    gen_op_srli_T1(28);
3976
    gen_op_store_sr();
3977
#endif
3978
}
3979

    
3980
#if defined(TARGET_PPC64)
3981
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3982
/* mfsr */
3983
GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
3984
{
3985
#if defined(CONFIG_USER_ONLY)
3986
    GEN_EXCP_PRIVREG(ctx);
3987
#else
3988
    if (unlikely(!ctx->supervisor)) {
3989
        GEN_EXCP_PRIVREG(ctx);
3990
        return;
3991
    }
3992
    gen_op_set_T1(SR(ctx->opcode));
3993
    gen_op_load_slb();
3994
    gen_op_store_T0_gpr(rD(ctx->opcode));
3995
#endif
3996
}
3997

    
3998
/* mfsrin */
3999
GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4000
             PPC_SEGMENT_64B)
4001
{
4002
#if defined(CONFIG_USER_ONLY)
4003
    GEN_EXCP_PRIVREG(ctx);
4004
#else
4005
    if (unlikely(!ctx->supervisor)) {
4006
        GEN_EXCP_PRIVREG(ctx);
4007
        return;
4008
    }
4009
    gen_op_load_gpr_T1(rB(ctx->opcode));
4010
    gen_op_srli_T1(28);
4011
    gen_op_load_slb();
4012
    gen_op_store_T0_gpr(rD(ctx->opcode));
4013
#endif
4014
}
4015

    
4016
/* mtsr */
4017
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4018
{
4019
#if defined(CONFIG_USER_ONLY)
4020
    GEN_EXCP_PRIVREG(ctx);
4021
#else
4022
    if (unlikely(!ctx->supervisor)) {
4023
        GEN_EXCP_PRIVREG(ctx);
4024
        return;
4025
    }
4026
    gen_op_load_gpr_T0(rS(ctx->opcode));
4027
    gen_op_set_T1(SR(ctx->opcode));
4028
    gen_op_store_slb();
4029
#endif
4030
}
4031

    
4032
/* mtsrin */
4033
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4034
             PPC_SEGMENT_64B)
4035
{
4036
#if defined(CONFIG_USER_ONLY)
4037
    GEN_EXCP_PRIVREG(ctx);
4038
#else
4039
    if (unlikely(!ctx->supervisor)) {
4040
        GEN_EXCP_PRIVREG(ctx);
4041
        return;
4042
    }
4043
    gen_op_load_gpr_T0(rS(ctx->opcode));
4044
    gen_op_load_gpr_T1(rB(ctx->opcode));
4045
    gen_op_srli_T1(28);
4046
    gen_op_store_slb();
4047
#endif
4048
}
4049
#endif /* defined(TARGET_PPC64) */
4050

    
4051
/***                      Lookaside buffer management                      ***/
4052
/* Optional & supervisor only: */
4053
/* tlbia */
4054
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4055
{
4056
#if defined(CONFIG_USER_ONLY)
4057
    GEN_EXCP_PRIVOPC(ctx);
4058
#else
4059
    if (unlikely(!ctx->supervisor)) {
4060
        if (loglevel != 0)
4061
            fprintf(logfile, "%s: ! supervisor\n", __func__);
4062
        GEN_EXCP_PRIVOPC(ctx);
4063
        return;
4064
    }
4065
    gen_op_tlbia();
4066
#endif
4067
}
4068

    
4069
/* tlbie */
4070
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4071
{
4072
#if defined(CONFIG_USER_ONLY)
4073
    GEN_EXCP_PRIVOPC(ctx);
4074
#else
4075
    if (unlikely(!ctx->supervisor)) {
4076
        GEN_EXCP_PRIVOPC(ctx);
4077
        return;
4078
    }
4079
    gen_op_load_gpr_T0(rB(ctx->opcode));
4080
#if defined(TARGET_PPC64)
4081
    if (ctx->sf_mode)
4082
        gen_op_tlbie_64();
4083
    else
4084
#endif
4085
        gen_op_tlbie();
4086
#endif
4087
}
4088

    
4089
/* tlbsync */
4090
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4091
{
4092
#if defined(CONFIG_USER_ONLY)
4093
    GEN_EXCP_PRIVOPC(ctx);
4094
#else
4095
    if (unlikely(!ctx->supervisor)) {
4096
        GEN_EXCP_PRIVOPC(ctx);
4097
        return;
4098
    }
4099
    /* This has no effect: it should ensure that all previous
4100
     * tlbie have completed
4101
     */
4102
    GEN_STOP(ctx);
4103
#endif
4104
}
4105

    
4106
#if defined(TARGET_PPC64)
4107
/* slbia */
4108
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4109
{
4110
#if defined(CONFIG_USER_ONLY)
4111
    GEN_EXCP_PRIVOPC(ctx);
4112
#else
4113
    if (unlikely(!ctx->supervisor)) {
4114
        if (loglevel != 0)
4115
            fprintf(logfile, "%s: ! supervisor\n", __func__);
4116
        GEN_EXCP_PRIVOPC(ctx);
4117
        return;
4118
    }
4119
    gen_op_slbia();
4120
#endif
4121
}
4122

    
4123
/* slbie */
4124
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4125
{
4126
#if defined(CONFIG_USER_ONLY)
4127
    GEN_EXCP_PRIVOPC(ctx);
4128
#else
4129
    if (unlikely(!ctx->supervisor)) {
4130
        GEN_EXCP_PRIVOPC(ctx);
4131
        return;
4132
    }
4133
    gen_op_load_gpr_T0(rB(ctx->opcode));
4134
    gen_op_slbie();
4135
#endif
4136
}
4137
#endif
4138

    
4139
/***                              External control                         ***/
4140
/* Optional: */
4141
#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4142
#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4143
#if defined(CONFIG_USER_ONLY)
4144
/* User-mode only */
4145
static GenOpFunc *gen_op_eciwx[] = {
4146
    &gen_op_eciwx_raw,
4147
    &gen_op_eciwx_le_raw,
4148
#if defined(TARGET_PPC64)
4149
    &gen_op_eciwx_64_raw,
4150
    &gen_op_eciwx_le_64_raw,
4151
#endif
4152
};
4153
static GenOpFunc *gen_op_ecowx[] = {
4154
    &gen_op_ecowx_raw,
4155
    &gen_op_ecowx_le_raw,
4156
#if defined(TARGET_PPC64)
4157
    &gen_op_ecowx_64_raw,
4158
    &gen_op_ecowx_le_64_raw,
4159
#endif
4160
};
4161
#else
4162
#if defined(TARGET_PPC64)
4163
/* Full system - 64 bits mode */
4164
static GenOpFunc *gen_op_eciwx[] = {
4165
    &gen_op_eciwx_user,
4166
    &gen_op_eciwx_le_user,
4167
    &gen_op_eciwx_64_user,
4168
    &gen_op_eciwx_le_64_user,
4169
    &gen_op_eciwx_kernel,
4170
    &gen_op_eciwx_le_kernel,
4171
    &gen_op_eciwx_64_kernel,
4172
    &gen_op_eciwx_le_64_kernel,
4173
#if defined(TARGET_PPC64H)
4174
    &gen_op_eciwx_hypv,
4175
    &gen_op_eciwx_le_hypv,
4176
    &gen_op_eciwx_64_hypv,
4177
    &gen_op_eciwx_le_64_hypv,
4178
#endif
4179
};
4180
static GenOpFunc *gen_op_ecowx[] = {
4181
    &gen_op_ecowx_user,
4182
    &gen_op_ecowx_le_user,
4183
    &gen_op_ecowx_64_user,
4184
    &gen_op_ecowx_le_64_user,
4185
    &gen_op_ecowx_kernel,
4186
    &gen_op_ecowx_le_kernel,
4187
    &gen_op_ecowx_64_kernel,
4188
    &gen_op_ecowx_le_64_kernel,
4189
#if defined(TARGET_PPC64H)
4190
    &gen_op_ecowx_hypv,
4191
    &gen_op_ecowx_le_hypv,
4192
    &gen_op_ecowx_64_hypv,
4193
    &gen_op_ecowx_le_64_hypv,
4194
#endif
4195
};
4196
#else
4197
/* Full system - 32 bits mode */
4198
static GenOpFunc *gen_op_eciwx[] = {
4199
    &gen_op_eciwx_user,
4200
    &gen_op_eciwx_le_user,
4201
    &gen_op_eciwx_kernel,
4202
    &gen_op_eciwx_le_kernel,
4203
};
4204
static GenOpFunc *gen_op_ecowx[] = {
4205
    &gen_op_ecowx_user,
4206
    &gen_op_ecowx_le_user,
4207
    &gen_op_ecowx_kernel,
4208
    &gen_op_ecowx_le_kernel,
4209
};
4210
#endif
4211
#endif
4212

    
4213
/* eciwx */
4214
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4215
{
4216
    /* Should check EAR[E] & alignment ! */
4217
    gen_addr_reg_index(ctx);
4218
    op_eciwx();
4219
    gen_op_store_T0_gpr(rD(ctx->opcode));
4220
}
4221

    
4222
/* ecowx */
4223
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4224
{
4225
    /* Should check EAR[E] & alignment ! */
4226
    gen_addr_reg_index(ctx);
4227
    gen_op_load_gpr_T1(rS(ctx->opcode));
4228
    op_ecowx();
4229
}
4230

    
4231
/* PowerPC 601 specific instructions */
4232
/* abs - abs. */
4233
GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4234
{
4235
    gen_op_load_gpr_T0(rA(ctx->opcode));
4236
    gen_op_POWER_abs();
4237
    gen_op_store_T0_gpr(rD(ctx->opcode));
4238
    if (unlikely(Rc(ctx->opcode) != 0))
4239
        gen_set_Rc0(ctx);
4240
}
4241

    
4242
/* abso - abso. */
4243
GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4244
{
4245
    gen_op_load_gpr_T0(rA(ctx->opcode));
4246
    gen_op_POWER_abso();
4247
    gen_op_store_T0_gpr(rD(ctx->opcode));
4248
    if (unlikely(Rc(ctx->opcode) != 0))
4249
        gen_set_Rc0(ctx);
4250
}
4251

    
4252
/* clcs */
4253
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4254
{
4255
    gen_op_load_gpr_T0(rA(ctx->opcode));
4256
    gen_op_POWER_clcs();
4257
    /* Rc=1 sets CR0 to an undefined state */
4258
    gen_op_store_T0_gpr(rD(ctx->opcode));
4259
}
4260

    
4261
/* div - div. */
4262
GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4263
{
4264
    gen_op_load_gpr_T0(rA(ctx->opcode));
4265
    gen_op_load_gpr_T1(rB(ctx->opcode));
4266
    gen_op_POWER_div();
4267
    gen_op_store_T0_gpr(rD(ctx->opcode));
4268
    if (unlikely(Rc(ctx->opcode) != 0))
4269
        gen_set_Rc0(ctx);
4270
}
4271

    
4272
/* divo - divo. */
4273
GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4274
{
4275
    gen_op_load_gpr_T0(rA(ctx->opcode));
4276
    gen_op_load_gpr_T1(rB(ctx->opcode));
4277
    gen_op_POWER_divo();
4278
    gen_op_store_T0_gpr(rD(ctx->opcode));
4279
    if (unlikely(Rc(ctx->opcode) != 0))
4280
        gen_set_Rc0(ctx);
4281
}
4282

    
4283
/* divs - divs. */
4284
GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4285
{
4286
    gen_op_load_gpr_T0(rA(ctx->opcode));
4287
    gen_op_load_gpr_T1(rB(ctx->opcode));
4288
    gen_op_POWER_divs();
4289
    gen_op_store_T0_gpr(rD(ctx->opcode));
4290
    if (unlikely(Rc(ctx->opcode) != 0))
4291
        gen_set_Rc0(ctx);
4292
}
4293

    
4294
/* divso - divso. */
4295
GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4296
{
4297
    gen_op_load_gpr_T0(rA(ctx->opcode));
4298
    gen_op_load_gpr_T1(rB(ctx->opcode));
4299
    gen_op_POWER_divso();
4300
    gen_op_store_T0_gpr(rD(ctx->opcode));
4301
    if (unlikely(Rc(ctx->opcode) != 0))
4302
        gen_set_Rc0(ctx);
4303
}
4304

    
4305
/* doz - doz. */
4306
GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4307
{
4308
    gen_op_load_gpr_T0(rA(ctx->opcode));
4309
    gen_op_load_gpr_T1(rB(ctx->opcode));
4310
    gen_op_POWER_doz();
4311
    gen_op_store_T0_gpr(rD(ctx->opcode));
4312
    if (unlikely(Rc(ctx->opcode) != 0))
4313
        gen_set_Rc0(ctx);
4314
}
4315

    
4316
/* dozo - dozo. */
4317
GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4318
{
4319
    gen_op_load_gpr_T0(rA(ctx->opcode));
4320
    gen_op_load_gpr_T1(rB(ctx->opcode));
4321
    gen_op_POWER_dozo();
4322
    gen_op_store_T0_gpr(rD(ctx->opcode));
4323
    if (unlikely(Rc(ctx->opcode) != 0))
4324
        gen_set_Rc0(ctx);
4325
}
4326

    
4327
/* dozi */
4328
GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4329
{
4330
    gen_op_load_gpr_T0(rA(ctx->opcode));
4331
    gen_op_set_T1(SIMM(ctx->opcode));
4332
    gen_op_POWER_doz();
4333
    gen_op_store_T0_gpr(rD(ctx->opcode));
4334
}
4335

    
4336
/* As lscbx load from memory byte after byte, it's always endian safe */
4337
#define op_POWER_lscbx(start, ra, rb)                                         \
4338
(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4339
#if defined(CONFIG_USER_ONLY)
4340
static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4341
    &gen_op_POWER_lscbx_raw,
4342
    &gen_op_POWER_lscbx_raw,
4343
};
4344
#else
4345
static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4346
    &gen_op_POWER_lscbx_user,
4347
    &gen_op_POWER_lscbx_user,
4348
    &gen_op_POWER_lscbx_kernel,
4349
    &gen_op_POWER_lscbx_kernel,
4350
};
4351
#endif
4352

    
4353
/* lscbx - lscbx. */
4354
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4355
{
4356
    int ra = rA(ctx->opcode);
4357
    int rb = rB(ctx->opcode);
4358

    
4359
    gen_addr_reg_index(ctx);
4360
    if (ra == 0) {
4361
        ra = rb;
4362
    }
4363
    /* NIP cannot be restored if the memory exception comes from an helper */
4364
    gen_update_nip(ctx, ctx->nip - 4);
4365
    gen_op_load_xer_bc();
4366
    gen_op_load_xer_cmp();
4367
    op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4368
    gen_op_store_xer_bc();
4369
    if (unlikely(Rc(ctx->opcode) != 0))
4370
        gen_set_Rc0(ctx);
4371
}
4372

    
4373
/* maskg - maskg. */
4374
GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4375
{
4376
    gen_op_load_gpr_T0(rS(ctx->opcode));
4377
    gen_op_load_gpr_T1(rB(ctx->opcode));
4378
    gen_op_POWER_maskg();
4379
    gen_op_store_T0_gpr(rA(ctx->opcode));
4380
    if (unlikely(Rc(ctx->opcode) != 0))
4381
        gen_set_Rc0(ctx);
4382
}
4383

    
4384
/* maskir - maskir. */
4385
GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4386
{
4387
    gen_op_load_gpr_T0(rA(ctx->opcode));
4388
    gen_op_load_gpr_T1(rS(ctx->opcode));
4389
    gen_op_load_gpr_T2(rB(ctx->opcode));
4390
    gen_op_POWER_maskir();
4391
    gen_op_store_T0_gpr(rA(ctx->opcode));
4392
    if (unlikely(Rc(ctx->opcode) != 0))
4393
        gen_set_Rc0(ctx);
4394
}
4395

    
4396
/* mul - mul. */
4397
GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4398
{
4399
    gen_op_load_gpr_T0(rA(ctx->opcode));
4400
    gen_op_load_gpr_T1(rB(ctx->opcode));
4401
    gen_op_POWER_mul();
4402
    gen_op_store_T0_gpr(rD(ctx->opcode));
4403
    if (unlikely(Rc(ctx->opcode) != 0))
4404
        gen_set_Rc0(ctx);
4405
}
4406

    
4407
/* mulo - mulo. */
4408
GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4409
{
4410
    gen_op_load_gpr_T0(rA(ctx->opcode));
4411
    gen_op_load_gpr_T1(rB(ctx->opcode));
4412
    gen_op_POWER_mulo();
4413
    gen_op_store_T0_gpr(rD(ctx->opcode));
4414
    if (unlikely(Rc(ctx->opcode) != 0))
4415
        gen_set_Rc0(ctx);
4416
}
4417

    
4418
/* nabs - nabs. */
4419
GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4420
{
4421
    gen_op_load_gpr_T0(rA(ctx->opcode));
4422
    gen_op_POWER_nabs();
4423
    gen_op_store_T0_gpr(rD(ctx->opcode));
4424
    if (unlikely(Rc(ctx->opcode) != 0))
4425
        gen_set_Rc0(ctx);
4426
}
4427

    
4428
/* nabso - nabso. */
4429
GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4430
{
4431
    gen_op_load_gpr_T0(rA(ctx->opcode));
4432
    gen_op_POWER_nabso();
4433
    gen_op_store_T0_gpr(rD(ctx->opcode));
4434
    if (unlikely(Rc(ctx->opcode) != 0))
4435
        gen_set_Rc0(ctx);
4436
}
4437

    
4438
/* rlmi - rlmi. */
4439
GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4440
{
4441
    uint32_t mb, me;
4442

    
4443
    mb = MB(ctx->opcode);
4444
    me = ME(ctx->opcode);
4445
    gen_op_load_gpr_T0(rS(ctx->opcode));
4446
    gen_op_load_gpr_T1(rA(ctx->opcode));
4447
    gen_op_load_gpr_T2(rB(ctx->opcode));
4448
    gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4449
    gen_op_store_T0_gpr(rA(ctx->opcode));
4450
    if (unlikely(Rc(ctx->opcode) != 0))
4451
        gen_set_Rc0(ctx);
4452
}
4453

    
4454
/* rrib - rrib. */
4455
GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4456
{
4457
    gen_op_load_gpr_T0(rS(ctx->opcode));
4458
    gen_op_load_gpr_T1(rA(ctx->opcode));
4459
    gen_op_load_gpr_T2(rB(ctx->opcode));
4460
    gen_op_POWER_rrib();
4461
    gen_op_store_T0_gpr(rA(ctx->opcode));
4462
    if (unlikely(Rc(ctx->opcode) != 0))
4463
        gen_set_Rc0(ctx);
4464
}
4465

    
4466
/* sle - sle. */
4467
GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4468
{
4469
    gen_op_load_gpr_T0(rS(ctx->opcode));
4470
    gen_op_load_gpr_T1(rB(ctx->opcode));
4471
    gen_op_POWER_sle();
4472
    gen_op_store_T0_gpr(rA(ctx->opcode));
4473
    if (unlikely(Rc(ctx->opcode) != 0))
4474
        gen_set_Rc0(ctx);
4475
}
4476

    
4477
/* sleq - sleq. */
4478
GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4479
{
4480
    gen_op_load_gpr_T0(rS(ctx->opcode));
4481
    gen_op_load_gpr_T1(rB(ctx->opcode));
4482
    gen_op_POWER_sleq();
4483
    gen_op_store_T0_gpr(rA(ctx->opcode));
4484
    if (unlikely(Rc(ctx->opcode) != 0))
4485
        gen_set_Rc0(ctx);
4486
}
4487

    
4488
/* sliq - sliq. */
4489
GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4490
{
4491
    gen_op_load_gpr_T0(rS(ctx->opcode));
4492
    gen_op_set_T1(SH(ctx->opcode));
4493
    gen_op_POWER_sle();
4494
    gen_op_store_T0_gpr(rA(ctx->opcode));
4495
    if (unlikely(Rc(ctx->opcode) != 0))
4496
        gen_set_Rc0(ctx);
4497
}
4498

    
4499
/* slliq - slliq. */
4500
GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4501
{
4502
    gen_op_load_gpr_T0(rS(ctx->opcode));
4503
    gen_op_set_T1(SH(ctx->opcode));
4504
    gen_op_POWER_sleq();
4505
    gen_op_store_T0_gpr(rA(ctx->opcode));
4506
    if (unlikely(Rc(ctx->opcode) != 0))
4507
        gen_set_Rc0(ctx);
4508
}
4509

    
4510
/* sllq - sllq. */
4511
GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4512
{
4513
    gen_op_load_gpr_T0(rS(ctx->opcode));
4514
    gen_op_load_gpr_T1(rB(ctx->opcode));
4515
    gen_op_POWER_sllq();
4516
    gen_op_store_T0_gpr(rA(ctx->opcode));
4517
    if (unlikely(Rc(ctx->opcode) != 0))
4518
        gen_set_Rc0(ctx);
4519
}
4520

    
4521
/* slq - slq. */
4522
GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4523
{
4524
    gen_op_load_gpr_T0(rS(ctx->opcode));
4525
    gen_op_load_gpr_T1(rB(ctx->opcode));
4526
    gen_op_POWER_slq();
4527
    gen_op_store_T0_gpr(rA(ctx->opcode));
4528
    if (unlikely(Rc(ctx->opcode) != 0))
4529
        gen_set_Rc0(ctx);
4530
}
4531

    
4532
/* sraiq - sraiq. */
4533
GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4534
{
4535
    gen_op_load_gpr_T0(rS(ctx->opcode));
4536
    gen_op_set_T1(SH(ctx->opcode));
4537
    gen_op_POWER_sraq();
4538
    gen_op_store_T0_gpr(rA(ctx->opcode));
4539
    if (unlikely(Rc(ctx->opcode) != 0))
4540
        gen_set_Rc0(ctx);
4541
}
4542

    
4543
/* sraq - sraq. */
4544
GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4545
{
4546
    gen_op_load_gpr_T0(rS(ctx->opcode));
4547
    gen_op_load_gpr_T1(rB(ctx->opcode));
4548
    gen_op_POWER_sraq();
4549
    gen_op_store_T0_gpr(rA(ctx->opcode));
4550
    if (unlikely(Rc(ctx->opcode) != 0))
4551
        gen_set_Rc0(ctx);
4552
}
4553

    
4554
/* sre - sre. */
4555
GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4556
{
4557
    gen_op_load_gpr_T0(rS(ctx->opcode));
4558
    gen_op_load_gpr_T1(rB(ctx->opcode));
4559
    gen_op_POWER_sre();
4560
    gen_op_store_T0_gpr(rA(ctx->opcode));
4561
    if (unlikely(Rc(ctx->opcode) != 0))
4562
        gen_set_Rc0(ctx);
4563
}
4564

    
4565
/* srea - srea. */
4566
GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4567
{
4568
    gen_op_load_gpr_T0(rS(ctx->opcode));
4569
    gen_op_load_gpr_T1(rB(ctx->opcode));
4570
    gen_op_POWER_srea();
4571
    gen_op_store_T0_gpr(rA(ctx->opcode));
4572
    if (unlikely(Rc(ctx->opcode) != 0))
4573
        gen_set_Rc0(ctx);
4574
}
4575

    
4576
/* sreq */
4577
GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4578
{
4579
    gen_op_load_gpr_T0(rS(ctx->opcode));
4580
    gen_op_load_gpr_T1(rB(ctx->opcode));
4581
    gen_op_POWER_sreq();
4582
    gen_op_store_T0_gpr(rA(ctx->opcode));
4583
    if (unlikely(Rc(ctx->opcode) != 0))
4584
        gen_set_Rc0(ctx);
4585
}
4586

    
4587
/* sriq */
4588
GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4589
{
4590
    gen_op_load_gpr_T0(rS(ctx->opcode));
4591
    gen_op_set_T1(SH(ctx->opcode));
4592
    gen_op_POWER_srq();
4593
    gen_op_store_T0_gpr(rA(ctx->opcode));
4594
    if (unlikely(Rc(ctx->opcode) != 0))
4595
        gen_set_Rc0(ctx);
4596
}
4597

    
4598
/* srliq */
4599
GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4600
{
4601
    gen_op_load_gpr_T0(rS(ctx->opcode));
4602
    gen_op_load_gpr_T1(rB(ctx->opcode));
4603
    gen_op_set_T1(SH(ctx->opcode));
4604
    gen_op_POWER_srlq();
4605
    gen_op_store_T0_gpr(rA(ctx->opcode));
4606
    if (unlikely(Rc(ctx->opcode) != 0))
4607
        gen_set_Rc0(ctx);
4608
}
4609

    
4610
/* srlq */
4611
GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4612
{
4613
    gen_op_load_gpr_T0(rS(ctx->opcode));
4614
    gen_op_load_gpr_T1(rB(ctx->opcode));
4615
    gen_op_POWER_srlq();
4616
    gen_op_store_T0_gpr(rA(ctx->opcode));
4617
    if (unlikely(Rc(ctx->opcode) != 0))
4618
        gen_set_Rc0(ctx);
4619
}
4620

    
4621
/* srq */
4622
GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4623
{
4624
    gen_op_load_gpr_T0(rS(ctx->opcode));
4625
    gen_op_load_gpr_T1(rB(ctx->opcode));
4626
    gen_op_POWER_srq();
4627
    gen_op_store_T0_gpr(rA(ctx->opcode));
4628
    if (unlikely(Rc(ctx->opcode) != 0))
4629
        gen_set_Rc0(ctx);
4630
}
4631

    
4632
/* PowerPC 602 specific instructions */
4633
/* dsa  */
4634
GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4635
{
4636
    /* XXX: TODO */
4637
    GEN_EXCP_INVAL(ctx);
4638
}
4639

    
4640
/* esa */
4641
GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4642
{
4643
    /* XXX: TODO */
4644
    GEN_EXCP_INVAL(ctx);
4645
}
4646

    
4647
/* mfrom */
4648
GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4649
{
4650
#if defined(CONFIG_USER_ONLY)
4651
    GEN_EXCP_PRIVOPC(ctx);
4652
#else
4653
    if (unlikely(!ctx->supervisor)) {
4654
        GEN_EXCP_PRIVOPC(ctx);
4655
        return;
4656
    }
4657
    gen_op_load_gpr_T0(rA(ctx->opcode));
4658
    gen_op_602_mfrom();
4659
    gen_op_store_T0_gpr(rD(ctx->opcode));
4660
#endif
4661
}
4662

    
4663
/* 602 - 603 - G2 TLB management */
4664
/* tlbld */
4665
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4666
{
4667
#if defined(CONFIG_USER_ONLY)
4668
    GEN_EXCP_PRIVOPC(ctx);
4669
#else
4670
    if (unlikely(!ctx->supervisor)) {
4671
        GEN_EXCP_PRIVOPC(ctx);
4672
        return;
4673
    }
4674
    gen_op_load_gpr_T0(rB(ctx->opcode));
4675
    gen_op_6xx_tlbld();
4676
#endif
4677
}
4678

    
4679
/* tlbli */
4680
GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4681
{
4682
#if defined(CONFIG_USER_ONLY)
4683
    GEN_EXCP_PRIVOPC(ctx);
4684
#else
4685
    if (unlikely(!ctx->supervisor)) {
4686
        GEN_EXCP_PRIVOPC(ctx);
4687
        return;
4688
    }
4689
    gen_op_load_gpr_T0(rB(ctx->opcode));
4690
    gen_op_6xx_tlbli();
4691
#endif
4692
}
4693

    
4694
/* 74xx TLB management */
4695
/* tlbld */
4696
GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4697
{
4698
#if defined(CONFIG_USER_ONLY)
4699
    GEN_EXCP_PRIVOPC(ctx);
4700
#else
4701
    if (unlikely(!ctx->supervisor)) {
4702
        GEN_EXCP_PRIVOPC(ctx);
4703
        return;
4704
    }
4705
    gen_op_load_gpr_T0(rB(ctx->opcode));
4706
    gen_op_74xx_tlbld();
4707
#endif
4708
}
4709

    
4710
/* tlbli */
4711
GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4712
{
4713
#if defined(CONFIG_USER_ONLY)
4714
    GEN_EXCP_PRIVOPC(ctx);
4715
#else
4716
    if (unlikely(!ctx->supervisor)) {
4717
        GEN_EXCP_PRIVOPC(ctx);
4718
        return;
4719
    }
4720
    gen_op_load_gpr_T0(rB(ctx->opcode));
4721
    gen_op_74xx_tlbli();
4722
#endif
4723
}
4724

    
4725
/* POWER instructions not in PowerPC 601 */
4726
/* clf */
4727
GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4728
{
4729
    /* Cache line flush: implemented as no-op */
4730
}
4731

    
4732
/* cli */
4733
GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4734
{
4735
    /* Cache line invalidate: privileged and treated as no-op */
4736
#if defined(CONFIG_USER_ONLY)
4737
    GEN_EXCP_PRIVOPC(ctx);
4738
#else
4739
    if (unlikely(!ctx->supervisor)) {
4740
        GEN_EXCP_PRIVOPC(ctx);
4741
        return;
4742
    }
4743
#endif
4744
}
4745

    
4746
/* dclst */
4747
GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4748
{
4749
    /* Data cache line store: treated as no-op */
4750
}
4751

    
4752
GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4753
{
4754
#if defined(CONFIG_USER_ONLY)
4755
    GEN_EXCP_PRIVOPC(ctx);
4756
#else
4757
    if (unlikely(!ctx->supervisor)) {
4758
        GEN_EXCP_PRIVOPC(ctx);
4759
        return;
4760
    }
4761
    int ra = rA(ctx->opcode);
4762
    int rd = rD(ctx->opcode);
4763

    
4764
    gen_addr_reg_index(ctx);
4765
    gen_op_POWER_mfsri();
4766
    gen_op_store_T0_gpr(rd);
4767
    if (ra != 0 && ra != rd)
4768
        gen_op_store_T1_gpr(ra);
4769
#endif
4770
}
4771

    
4772
GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4773
{
4774
#if defined(CONFIG_USER_ONLY)
4775
    GEN_EXCP_PRIVOPC(ctx);
4776
#else
4777
    if (unlikely(!ctx->supervisor)) {
4778
        GEN_EXCP_PRIVOPC(ctx);
4779
        return;
4780
    }
4781
    gen_addr_reg_index(ctx);
4782
    gen_op_POWER_rac();
4783
    gen_op_store_T0_gpr(rD(ctx->opcode));
4784
#endif
4785
}
4786

    
4787
GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4788
{
4789
#if defined(CONFIG_USER_ONLY)
4790
    GEN_EXCP_PRIVOPC(ctx);
4791
#else
4792
    if (unlikely(!ctx->supervisor)) {
4793
        GEN_EXCP_PRIVOPC(ctx);
4794
        return;
4795
    }
4796
    gen_op_POWER_rfsvc();
4797
    GEN_SYNC(ctx);
4798
#endif
4799
}
4800

    
4801
/* svc is not implemented for now */
4802

    
4803
/* POWER2 specific instructions */
4804
/* Quad manipulation (load/store two floats at a time) */
4805
#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4806
#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4807
#if defined(CONFIG_USER_ONLY)
4808
static GenOpFunc *gen_op_POWER2_lfq[] = {
4809
    &gen_op_POWER2_lfq_le_raw,
4810
    &gen_op_POWER2_lfq_raw,
4811
};
4812
static GenOpFunc *gen_op_POWER2_stfq[] = {
4813
    &gen_op_POWER2_stfq_le_raw,
4814
    &gen_op_POWER2_stfq_raw,
4815
};
4816
#else
4817
static GenOpFunc *gen_op_POWER2_lfq[] = {
4818
    &gen_op_POWER2_lfq_le_user,
4819
    &gen_op_POWER2_lfq_user,
4820
    &gen_op_POWER2_lfq_le_kernel,
4821
    &gen_op_POWER2_lfq_kernel,
4822
};
4823
static GenOpFunc *gen_op_POWER2_stfq[] = {
4824
    &gen_op_POWER2_stfq_le_user,
4825
    &gen_op_POWER2_stfq_user,
4826
    &gen_op_POWER2_stfq_le_kernel,
4827
    &gen_op_POWER2_stfq_kernel,
4828
};
4829
#endif
4830

    
4831
/* lfq */
4832
GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4833
{
4834
    /* NIP cannot be restored if the memory exception comes from an helper */
4835
    gen_update_nip(ctx, ctx->nip - 4);
4836
    gen_addr_imm_index(ctx, 0);
4837
    op_POWER2_lfq();
4838
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4839
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4840
}
4841

    
4842
/* lfqu */
4843
GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4844
{
4845
    int ra = rA(ctx->opcode);
4846

    
4847
    /* NIP cannot be restored if the memory exception comes from an helper */
4848
    gen_update_nip(ctx, ctx->nip - 4);
4849
    gen_addr_imm_index(ctx, 0);
4850
    op_POWER2_lfq();
4851
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4852
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4853
    if (ra != 0)
4854
        gen_op_store_T0_gpr(ra);
4855
}
4856

    
4857
/* lfqux */
4858
GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4859
{
4860
    int ra = rA(ctx->opcode);
4861

    
4862
    /* NIP cannot be restored if the memory exception comes from an helper */
4863
    gen_update_nip(ctx, ctx->nip - 4);
4864
    gen_addr_reg_index(ctx);
4865
    op_POWER2_lfq();
4866
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4867
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4868
    if (ra != 0)
4869
        gen_op_store_T0_gpr(ra);
4870
}
4871

    
4872
/* lfqx */
4873
GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4874
{
4875
    /* NIP cannot be restored if the memory exception comes from an helper */
4876
    gen_update_nip(ctx, ctx->nip - 4);
4877
    gen_addr_reg_index(ctx);
4878
    op_POWER2_lfq();
4879
    gen_op_store_FT0_fpr(rD(ctx->opcode));
4880
    gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4881
}
4882

    
4883
/* stfq */
4884
GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4885
{
4886
    /* NIP cannot be restored if the memory exception comes from an helper */
4887
    gen_update_nip(ctx, ctx->nip - 4);
4888
    gen_addr_imm_index(ctx, 0);
4889
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4890
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4891
    op_POWER2_stfq();
4892
}
4893

    
4894
/* stfqu */
4895
GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4896
{
4897
    int ra = rA(ctx->opcode);
4898

    
4899
    /* NIP cannot be restored if the memory exception comes from an helper */
4900
    gen_update_nip(ctx, ctx->nip - 4);
4901
    gen_addr_imm_index(ctx, 0);
4902
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4903
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4904
    op_POWER2_stfq();
4905
    if (ra != 0)
4906
        gen_op_store_T0_gpr(ra);
4907
}
4908

    
4909
/* stfqux */
4910
GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4911
{
4912
    int ra = rA(ctx->opcode);
4913

    
4914
    /* NIP cannot be restored if the memory exception comes from an helper */
4915
    gen_update_nip(ctx, ctx->nip - 4);
4916
    gen_addr_reg_index(ctx);
4917
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4918
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4919
    op_POWER2_stfq();
4920
    if (ra != 0)
4921
        gen_op_store_T0_gpr(ra);
4922
}
4923

    
4924
/* stfqx */
4925
GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4926
{
4927
    /* NIP cannot be restored if the memory exception comes from an helper */
4928
    gen_update_nip(ctx, ctx->nip - 4);
4929
    gen_addr_reg_index(ctx);
4930
    gen_op_load_fpr_FT0(rS(ctx->opcode));
4931
    gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4932
    op_POWER2_stfq();
4933
}
4934

    
4935
/* BookE specific instructions */
4936
/* XXX: not implemented on 440 ? */
4937
GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
4938
{
4939
    /* XXX: T