Revision c98d174c
ID | c98d174c24b915e9908785feb63eb3b5abe33818 |
target-arm: Clear IT bits when taking exceptions in v7M
When taking an exception for an M profile core, we must clear
the IT bits. Since the IT bits are cached in env->condexec_bits
we must clear them there: writing the bits in env->uncached_cpsr
has no effect. (Reported as LP:944645.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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