Revision c9c1a064 target-mips/translate_init.c

b/target-mips/translate_init.c
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        .SYNCI_Step = 16,
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        .CCRes = 2,
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        .Status_rw_bitmask = 0x3678FFFF,
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        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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	/* XXX: The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
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        .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
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    },
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    {
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        .name = "5Kc",
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        .CP0_PRid = 0x00018100,
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        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
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        .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
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		    (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
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		    (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
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		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
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        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 32,
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        .CCRes = 2,
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        .Status_rw_bitmask = 0x3278FFFF,
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    },
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    {
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        .name = "5Kf",
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        .CP0_PRid = 0x00018100,
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        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
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        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
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		    (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
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		    (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
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		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
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        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 32,
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        .CCRes = 2,
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        .Status_rw_bitmask = 0x3678FFFF,
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	/* XXX: The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
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        .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
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                    (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
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    },
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    {
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        .name = "20Kc",
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        .CP0_PRid = 0x00018200,
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        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (1 << CP0C0_VI),
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        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
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		    (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
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		    (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
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		    (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
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        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 32,
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        .CCRes = 2,
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        .Status_rw_bitmask = 0x36FBFFFF,
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	/* XXX: The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
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        .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
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                    (1 << FCR0_D) | (1 << FCR0_S) |
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                    (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
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                    (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
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    },
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#endif
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};

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