Revision ca27c052 target-arm/translate.c

b/target-arm/translate.c
5778 5778
    int rt = (insn >> 12) & 0xf;
5779 5779
    TCGv tmp;
5780 5780

  
5781
    /* Minimal set of debug registers, since we don't support debug */
5782
    if (op1 == 0 && crn == 0 && op2 == 0) {
5783
        switch (crm) {
5784
        case 0:
5785
            /* DBGDIDR: just RAZ. In particular this means the
5786
             * "debug architecture version" bits will read as
5787
             * a reserved value, which should cause Linux to
5788
             * not try to use the debug hardware.
5789
             */
5790
            tmp = tcg_const_i32(0);
5791
            store_reg(s, rt, tmp);
5792
            return 0;
5793
        case 1:
5794
        case 2:
5795
            /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
5796
             * don't implement memory mapped debug components
5797
             */
5798
            if (ENABLE_ARCH_7) {
5799
                tmp = tcg_const_i32(0);
5800
                store_reg(s, rt, tmp);
5801
                return 0;
5802
            }
5803
            break;
5804
        default:
5805
            break;
5806
        }
5807
    }
5808

  
5781 5809
    if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5782 5810
        if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5783 5811
            /* TEECR */

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