Revision ca87d03b hw/etraxfs_ser.c

b/hw/etraxfs_ser.c
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static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
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{
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	CPUState *env;
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	uint32_t r = 0;
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	env = opaque;
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	D(CPUState *env = opaque);
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	D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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	return r;
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	return 0;
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}
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static uint32_t ser_readw (void *opaque, target_phys_addr_t addr)
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{
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	CPUState *env;
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	uint32_t r = 0;
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	env = opaque;
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	D(CPUState *env = opaque);
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	D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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	return r;
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	return 0;
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}
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static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
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{
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	CPUState *env = opaque;
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	D(CPUState *env = opaque);
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	uint32_t r = 0;
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	switch (addr & 0xfff)
......
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static void
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ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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	CPUState *env;
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	env = opaque;
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	D(CPUState *env = opaque);
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 	D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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ser_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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	CPUState *env;
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	env = opaque;
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	D(CPUState *env = opaque);
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	D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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	CPUState *env = opaque;
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	D(CPUState *env = opaque);
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	switch (addr & 0xfff)
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	{
......
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}
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static CPUReadMemoryFunc *ser_read[] = {
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    &ser_readb,
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    &ser_readw,
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    &ser_readl,
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	&ser_readb,
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	&ser_readw,
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	&ser_readl,
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};
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static CPUWriteMemoryFunc *ser_write[] = {
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    &ser_writeb,
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    &ser_writew,
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    &ser_writel,
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	&ser_writeb,
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	&ser_writew,
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	&ser_writel,
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};
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void etraxfs_ser_init(CPUState *env, qemu_irq *irqs)
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void etraxfs_ser_init(CPUState *env, qemu_irq *irqs, target_phys_addr_t base)
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{
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	int ser_regs;
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	ser_regs = cpu_register_io_memory(0, ser_read, ser_write, env);
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	cpu_register_physical_memory (0xb0026000, 0x3c, ser_regs);
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	cpu_register_physical_memory (0xb0028000, 0x3c, ser_regs);
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	cpu_register_physical_memory (0xb002a000, 0x3c, ser_regs);
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	cpu_register_physical_memory (0xb002c000, 0x3c, ser_regs);
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	cpu_register_physical_memory (base, 0x3c, ser_regs);
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}

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