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/*
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 * QEMU ETRAX System Emulator
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 *
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 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include <stdio.h>
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#include <ctype.h>
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#include "hw.h"
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#define D(x)
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#define RW_TR_DMA_EN 0x04
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#define RW_DOUT 0x1c
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#define RW_STAT_DIN 0x20
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#define R_STAT_DIN 0x24
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static uint32_t ser_readb (void *opaque, target_phys_addr_t addr)
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{
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        D(CPUState *env = opaque);
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        D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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        return 0;
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}
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static uint32_t ser_readw (void *opaque, target_phys_addr_t addr)
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{
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        D(CPUState *env = opaque);
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        D(printf ("%s %x pc=%x\n", __func__, addr, env->pc));
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        return 0;
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}
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static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
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{
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        D(CPUState *env = opaque);
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        uint32_t r = 0;
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        switch (addr & 0xfff)
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        {
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                case RW_TR_DMA_EN:
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                        break;
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                case R_STAT_DIN:
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                        r |= 1 << 24; /* set tr_rdy.  */
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                        r |= 1 << 22; /* set tr_idle.  */
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                        break;
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                default:
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                        D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
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                        break;
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        }
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        return r;
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}
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static void
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ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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        D(CPUState *env = opaque);
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         D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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ser_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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        D(CPUState *env = opaque);
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        D(printf ("%s %x %x pc=%x\n", __func__, addr, value, env->pc));
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}
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static void
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ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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        D(CPUState *env = opaque);
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        switch (addr & 0xfff)
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        {
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                case RW_TR_DMA_EN:
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                        break;
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                case RW_DOUT:
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                        if (isprint(value) || isspace(value))
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                                putchar(value);
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                        else
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                                putchar('.');
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                        fflush(stdout);
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                        break;
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                default:
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                        D(printf ("%s %x %x pc=%x\n",
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                                  __func__, addr, value, env->pc));
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                        break;
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        }
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}
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static CPUReadMemoryFunc *ser_read[] = {
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        &ser_readb,
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        &ser_readw,
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        &ser_readl,
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};
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static CPUWriteMemoryFunc *ser_write[] = {
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        &ser_writeb,
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        &ser_writew,
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        &ser_writel,
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};
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void etraxfs_ser_init(CPUState *env, qemu_irq *irqs, target_phys_addr_t base)
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{
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        int ser_regs;
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        ser_regs = cpu_register_io_memory(0, ser_read, ser_write, env);
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        cpu_register_physical_memory (base, 0x3c, ser_regs);
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}