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1
/*
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 * QEMU KVM support
3
 *
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 * Copyright (C) 2006-2008 Qumranet Technologies
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 * Copyright IBM, Corp. 2008
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 *
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 * Authors:
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 *  Anthony Liguori   <aliguori@us.ibm.com>
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 *
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 * This work is licensed under the terms of the GNU GPL, version 2 or later.
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 * See the COPYING file in the top-level directory.
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 *
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 */
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#include <sys/types.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
18

    
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#include <linux/kvm.h>
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#include "qemu-common.h"
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#include "sysemu.h"
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#include "kvm.h"
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#include "cpu.h"
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#include "gdbstub.h"
26

    
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//#define DEBUG_KVM
28

    
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#ifdef DEBUG_KVM
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#define dprintf(fmt, ...) \
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    do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
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#else
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#define dprintf(fmt, ...) \
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    do { } while (0)
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#endif
36

    
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#ifdef KVM_CAP_EXT_CPUID
38

    
39
static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
40
{
41
    struct kvm_cpuid2 *cpuid;
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    int r, size;
43

    
44
    size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
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    cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
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    cpuid->nent = max;
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    r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
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    if (r == 0 && cpuid->nent >= max) {
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        r = -E2BIG;
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    }
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    if (r < 0) {
52
        if (r == -E2BIG) {
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            qemu_free(cpuid);
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            return NULL;
55
        } else {
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            fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
57
                    strerror(-r));
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            exit(1);
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        }
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    }
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    return cpuid;
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}
63

    
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uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
65
{
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    struct kvm_cpuid2 *cpuid;
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    int i, max;
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    uint32_t ret = 0;
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    uint32_t cpuid_1_edx;
70

    
71
    if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
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        return -1U;
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    }
74

    
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    max = 1;
76
    while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
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        max *= 2;
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    }
79

    
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    for (i = 0; i < cpuid->nent; ++i) {
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        if (cpuid->entries[i].function == function) {
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            switch (reg) {
83
            case R_EAX:
84
                ret = cpuid->entries[i].eax;
85
                break;
86
            case R_EBX:
87
                ret = cpuid->entries[i].ebx;
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                break;
89
            case R_ECX:
90
                ret = cpuid->entries[i].ecx;
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                break;
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            case R_EDX:
93
                ret = cpuid->entries[i].edx;
94
                if (function == 0x80000001) {
95
                    /* On Intel, kvm returns cpuid according to the Intel spec,
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                     * so add missing bits according to the AMD spec:
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                     */
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                    cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
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                    ret |= cpuid_1_edx & 0xdfeff7ff;
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                }
101
                break;
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            }
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        }
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    }
105

    
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    qemu_free(cpuid);
107

    
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    return ret;
109
}
110

    
111
#else
112

    
113
uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
114
{
115
    return -1U;
116
}
117

    
118
#endif
119

    
120
static void kvm_trim_features(uint32_t *features, uint32_t supported)
121
{
122
    int i;
123
    uint32_t mask;
124

    
125
    for (i = 0; i < 32; ++i) {
126
        mask = 1U << i;
127
        if ((*features & mask) && !(supported & mask)) {
128
            *features &= ~mask;
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        }
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    }
131
}
132

    
133
int kvm_arch_init_vcpu(CPUState *env)
134
{
135
    struct {
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        struct kvm_cpuid2 cpuid;
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        struct kvm_cpuid_entry2 entries[100];
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    } __attribute__((packed)) cpuid_data;
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    uint32_t limit, i, j, cpuid_i;
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    uint32_t unused;
141

    
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    env->mp_state = KVM_MP_STATE_RUNNABLE;
143

    
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    kvm_trim_features(&env->cpuid_features,
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        kvm_arch_get_supported_cpuid(env, 1, R_EDX));
146

    
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    i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
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    kvm_trim_features(&env->cpuid_ext_features,
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        kvm_arch_get_supported_cpuid(env, 1, R_ECX));
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    env->cpuid_ext_features |= i;
151

    
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    kvm_trim_features(&env->cpuid_ext2_features,
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        kvm_arch_get_supported_cpuid(env, 0x80000001, R_EDX));
154
    kvm_trim_features(&env->cpuid_ext3_features,
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        kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX));
156

    
157
    cpuid_i = 0;
158

    
159
    cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
160

    
161
    for (i = 0; i <= limit; i++) {
162
        struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
163

    
164
        switch (i) {
165
        case 2: {
166
            /* Keep reading function 2 till all the input is received */
167
            int times;
168

    
169
            c->function = i;
170
            c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
171
                       KVM_CPUID_FLAG_STATE_READ_NEXT;
172
            cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
173
            times = c->eax & 0xff;
174

    
175
            for (j = 1; j < times; ++j) {
176
                c = &cpuid_data.entries[cpuid_i++];
177
                c->function = i;
178
                c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
179
                cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
180
            }
181
            break;
182
        }
183
        case 4:
184
        case 0xb:
185
        case 0xd:
186
            for (j = 0; ; j++) {
187
                c->function = i;
188
                c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
189
                c->index = j;
190
                cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
191

    
192
                if (i == 4 && c->eax == 0)
193
                    break;
194
                if (i == 0xb && !(c->ecx & 0xff00))
195
                    break;
196
                if (i == 0xd && c->eax == 0)
197
                    break;
198

    
199
                c = &cpuid_data.entries[cpuid_i++];
200
            }
201
            break;
202
        default:
203
            c->function = i;
204
            c->flags = 0;
205
            cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
206
            break;
207
        }
208
    }
209
    cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
210

    
211
    for (i = 0x80000000; i <= limit; i++) {
212
        struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
213

    
214
        c->function = i;
215
        c->flags = 0;
216
        cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
217
    }
218

    
219
    cpuid_data.cpuid.nent = cpuid_i;
220

    
221
    return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
222
}
223

    
224
void kvm_arch_reset_vcpu(CPUState *env)
225
{
226
}
227

    
228
static int kvm_has_msr_star(CPUState *env)
229
{
230
    static int has_msr_star;
231
    int ret;
232

    
233
    /* first time */
234
    if (has_msr_star == 0) {        
235
        struct kvm_msr_list msr_list, *kvm_msr_list;
236

    
237
        has_msr_star = -1;
238

    
239
        /* Obtain MSR list from KVM.  These are the MSRs that we must
240
         * save/restore */
241
        msr_list.nmsrs = 0;
242
        ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
243
        if (ret < 0)
244
            return 0;
245

    
246
        /* Old kernel modules had a bug and could write beyond the provided
247
           memory. Allocate at least a safe amount of 1K. */
248
        kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
249
                                              msr_list.nmsrs *
250
                                              sizeof(msr_list.indices[0])));
251

    
252
        kvm_msr_list->nmsrs = msr_list.nmsrs;
253
        ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
254
        if (ret >= 0) {
255
            int i;
256

    
257
            for (i = 0; i < kvm_msr_list->nmsrs; i++) {
258
                if (kvm_msr_list->indices[i] == MSR_STAR) {
259
                    has_msr_star = 1;
260
                    break;
261
                }
262
            }
263
        }
264

    
265
        free(kvm_msr_list);
266
    }
267

    
268
    if (has_msr_star == 1)
269
        return 1;
270
    return 0;
271
}
272

    
273
int kvm_arch_init(KVMState *s, int smp_cpus)
274
{
275
    int ret;
276

    
277
    /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
278
     * directly.  In order to use vm86 mode, a TSS is needed.  Since this
279
     * must be part of guest physical memory, we need to allocate it.  Older
280
     * versions of KVM just assumed that it would be at the end of physical
281
     * memory but that doesn't work with more than 4GB of memory.  We simply
282
     * refuse to work with those older versions of KVM. */
283
    ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
284
    if (ret <= 0) {
285
        fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
286
        return ret;
287
    }
288

    
289
    /* this address is 3 pages before the bios, and the bios should present
290
     * as unavaible memory.  FIXME, need to ensure the e820 map deals with
291
     * this?
292
     */
293
    return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
294
}
295
                    
296
static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
297
{
298
    lhs->selector = rhs->selector;
299
    lhs->base = rhs->base;
300
    lhs->limit = rhs->limit;
301
    lhs->type = 3;
302
    lhs->present = 1;
303
    lhs->dpl = 3;
304
    lhs->db = 0;
305
    lhs->s = 1;
306
    lhs->l = 0;
307
    lhs->g = 0;
308
    lhs->avl = 0;
309
    lhs->unusable = 0;
310
}
311

    
312
static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
313
{
314
    unsigned flags = rhs->flags;
315
    lhs->selector = rhs->selector;
316
    lhs->base = rhs->base;
317
    lhs->limit = rhs->limit;
318
    lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
319
    lhs->present = (flags & DESC_P_MASK) != 0;
320
    lhs->dpl = rhs->selector & 3;
321
    lhs->db = (flags >> DESC_B_SHIFT) & 1;
322
    lhs->s = (flags & DESC_S_MASK) != 0;
323
    lhs->l = (flags >> DESC_L_SHIFT) & 1;
324
    lhs->g = (flags & DESC_G_MASK) != 0;
325
    lhs->avl = (flags & DESC_AVL_MASK) != 0;
326
    lhs->unusable = 0;
327
}
328

    
329
static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
330
{
331
    lhs->selector = rhs->selector;
332
    lhs->base = rhs->base;
333
    lhs->limit = rhs->limit;
334
    lhs->flags =
335
        (rhs->type << DESC_TYPE_SHIFT)
336
        | (rhs->present * DESC_P_MASK)
337
        | (rhs->dpl << DESC_DPL_SHIFT)
338
        | (rhs->db << DESC_B_SHIFT)
339
        | (rhs->s * DESC_S_MASK)
340
        | (rhs->l << DESC_L_SHIFT)
341
        | (rhs->g * DESC_G_MASK)
342
        | (rhs->avl * DESC_AVL_MASK);
343
}
344

    
345
static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
346
{
347
    if (set)
348
        *kvm_reg = *qemu_reg;
349
    else
350
        *qemu_reg = *kvm_reg;
351
}
352

    
353
static int kvm_getput_regs(CPUState *env, int set)
354
{
355
    struct kvm_regs regs;
356
    int ret = 0;
357

    
358
    if (!set) {
359
        ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
360
        if (ret < 0)
361
            return ret;
362
    }
363

    
364
    kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
365
    kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
366
    kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
367
    kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
368
    kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
369
    kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
370
    kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
371
    kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
372
#ifdef TARGET_X86_64
373
    kvm_getput_reg(&regs.r8, &env->regs[8], set);
374
    kvm_getput_reg(&regs.r9, &env->regs[9], set);
375
    kvm_getput_reg(&regs.r10, &env->regs[10], set);
376
    kvm_getput_reg(&regs.r11, &env->regs[11], set);
377
    kvm_getput_reg(&regs.r12, &env->regs[12], set);
378
    kvm_getput_reg(&regs.r13, &env->regs[13], set);
379
    kvm_getput_reg(&regs.r14, &env->regs[14], set);
380
    kvm_getput_reg(&regs.r15, &env->regs[15], set);
381
#endif
382

    
383
    kvm_getput_reg(&regs.rflags, &env->eflags, set);
384
    kvm_getput_reg(&regs.rip, &env->eip, set);
385

    
386
    if (set)
387
        ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
388

    
389
    return ret;
390
}
391

    
392
static int kvm_put_fpu(CPUState *env)
393
{
394
    struct kvm_fpu fpu;
395
    int i;
396

    
397
    memset(&fpu, 0, sizeof fpu);
398
    fpu.fsw = env->fpus & ~(7 << 11);
399
    fpu.fsw |= (env->fpstt & 7) << 11;
400
    fpu.fcw = env->fpuc;
401
    for (i = 0; i < 8; ++i)
402
        fpu.ftwx |= (!env->fptags[i]) << i;
403
    memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
404
    memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
405
    fpu.mxcsr = env->mxcsr;
406

    
407
    return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
408
}
409

    
410
static int kvm_put_sregs(CPUState *env)
411
{
412
    struct kvm_sregs sregs;
413

    
414
    memcpy(sregs.interrupt_bitmap,
415
           env->interrupt_bitmap,
416
           sizeof(sregs.interrupt_bitmap));
417

    
418
    if ((env->eflags & VM_MASK)) {
419
            set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
420
            set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
421
            set_v8086_seg(&sregs.es, &env->segs[R_ES]);
422
            set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
423
            set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
424
            set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
425
    } else {
426
            set_seg(&sregs.cs, &env->segs[R_CS]);
427
            set_seg(&sregs.ds, &env->segs[R_DS]);
428
            set_seg(&sregs.es, &env->segs[R_ES]);
429
            set_seg(&sregs.fs, &env->segs[R_FS]);
430
            set_seg(&sregs.gs, &env->segs[R_GS]);
431
            set_seg(&sregs.ss, &env->segs[R_SS]);
432

    
433
            if (env->cr[0] & CR0_PE_MASK) {
434
                /* force ss cpl to cs cpl */
435
                sregs.ss.selector = (sregs.ss.selector & ~3) |
436
                        (sregs.cs.selector & 3);
437
                sregs.ss.dpl = sregs.ss.selector & 3;
438
            }
439
    }
440

    
441
    set_seg(&sregs.tr, &env->tr);
442
    set_seg(&sregs.ldt, &env->ldt);
443

    
444
    sregs.idt.limit = env->idt.limit;
445
    sregs.idt.base = env->idt.base;
446
    sregs.gdt.limit = env->gdt.limit;
447
    sregs.gdt.base = env->gdt.base;
448

    
449
    sregs.cr0 = env->cr[0];
450
    sregs.cr2 = env->cr[2];
451
    sregs.cr3 = env->cr[3];
452
    sregs.cr4 = env->cr[4];
453

    
454
    sregs.cr8 = cpu_get_apic_tpr(env);
455
    sregs.apic_base = cpu_get_apic_base(env);
456

    
457
    sregs.efer = env->efer;
458

    
459
    return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
460
}
461

    
462
static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
463
                              uint32_t index, uint64_t value)
464
{
465
    entry->index = index;
466
    entry->data = value;
467
}
468

    
469
static int kvm_put_msrs(CPUState *env)
470
{
471
    struct {
472
        struct kvm_msrs info;
473
        struct kvm_msr_entry entries[100];
474
    } msr_data;
475
    struct kvm_msr_entry *msrs = msr_data.entries;
476
    int n = 0;
477

    
478
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
479
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
480
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
481
    if (kvm_has_msr_star(env))
482
        kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
483
    kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
484
#ifdef TARGET_X86_64
485
    /* FIXME if lm capable */
486
    kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
487
    kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
488
    kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
489
    kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
490
#endif
491
    msr_data.info.nmsrs = n;
492

    
493
    return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
494

    
495
}
496

    
497

    
498
static int kvm_get_fpu(CPUState *env)
499
{
500
    struct kvm_fpu fpu;
501
    int i, ret;
502

    
503
    ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
504
    if (ret < 0)
505
        return ret;
506

    
507
    env->fpstt = (fpu.fsw >> 11) & 7;
508
    env->fpus = fpu.fsw;
509
    env->fpuc = fpu.fcw;
510
    for (i = 0; i < 8; ++i)
511
        env->fptags[i] = !((fpu.ftwx >> i) & 1);
512
    memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
513
    memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
514
    env->mxcsr = fpu.mxcsr;
515

    
516
    return 0;
517
}
518

    
519
static int kvm_get_sregs(CPUState *env)
520
{
521
    struct kvm_sregs sregs;
522
    uint32_t hflags;
523
    int ret;
524

    
525
    ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
526
    if (ret < 0)
527
        return ret;
528

    
529
    memcpy(env->interrupt_bitmap, 
530
           sregs.interrupt_bitmap,
531
           sizeof(sregs.interrupt_bitmap));
532

    
533
    get_seg(&env->segs[R_CS], &sregs.cs);
534
    get_seg(&env->segs[R_DS], &sregs.ds);
535
    get_seg(&env->segs[R_ES], &sregs.es);
536
    get_seg(&env->segs[R_FS], &sregs.fs);
537
    get_seg(&env->segs[R_GS], &sregs.gs);
538
    get_seg(&env->segs[R_SS], &sregs.ss);
539

    
540
    get_seg(&env->tr, &sregs.tr);
541
    get_seg(&env->ldt, &sregs.ldt);
542

    
543
    env->idt.limit = sregs.idt.limit;
544
    env->idt.base = sregs.idt.base;
545
    env->gdt.limit = sregs.gdt.limit;
546
    env->gdt.base = sregs.gdt.base;
547

    
548
    env->cr[0] = sregs.cr0;
549
    env->cr[2] = sregs.cr2;
550
    env->cr[3] = sregs.cr3;
551
    env->cr[4] = sregs.cr4;
552

    
553
    cpu_set_apic_base(env, sregs.apic_base);
554

    
555
    env->efer = sregs.efer;
556
    //cpu_set_apic_tpr(env, sregs.cr8);
557

    
558
#define HFLAG_COPY_MASK ~( \
559
                        HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
560
                        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
561
                        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
562
                        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
563

    
564

    
565

    
566
    hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
567
    hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
568
    hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
569
            (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
570
    hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
571
    hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
572
            (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
573

    
574
    if (env->efer & MSR_EFER_LMA) {
575
        hflags |= HF_LMA_MASK;
576
    }
577

    
578
    if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
579
        hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
580
    } else {
581
        hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
582
                (DESC_B_SHIFT - HF_CS32_SHIFT);
583
        hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
584
                (DESC_B_SHIFT - HF_SS32_SHIFT);
585
        if (!(env->cr[0] & CR0_PE_MASK) ||
586
                   (env->eflags & VM_MASK) ||
587
                   !(hflags & HF_CS32_MASK)) {
588
                hflags |= HF_ADDSEG_MASK;
589
            } else {
590
                hflags |= ((env->segs[R_DS].base |
591
                                env->segs[R_ES].base |
592
                                env->segs[R_SS].base) != 0) <<
593
                    HF_ADDSEG_SHIFT;
594
            }
595
    }
596
    env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
597

    
598
    return 0;
599
}
600

    
601
static int kvm_get_msrs(CPUState *env)
602
{
603
    struct {
604
        struct kvm_msrs info;
605
        struct kvm_msr_entry entries[100];
606
    } msr_data;
607
    struct kvm_msr_entry *msrs = msr_data.entries;
608
    int ret, i, n;
609

    
610
    n = 0;
611
    msrs[n++].index = MSR_IA32_SYSENTER_CS;
612
    msrs[n++].index = MSR_IA32_SYSENTER_ESP;
613
    msrs[n++].index = MSR_IA32_SYSENTER_EIP;
614
    if (kvm_has_msr_star(env))
615
        msrs[n++].index = MSR_STAR;
616
    msrs[n++].index = MSR_IA32_TSC;
617
#ifdef TARGET_X86_64
618
    /* FIXME lm_capable_kernel */
619
    msrs[n++].index = MSR_CSTAR;
620
    msrs[n++].index = MSR_KERNELGSBASE;
621
    msrs[n++].index = MSR_FMASK;
622
    msrs[n++].index = MSR_LSTAR;
623
#endif
624
    msr_data.info.nmsrs = n;
625
    ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
626
    if (ret < 0)
627
        return ret;
628

    
629
    for (i = 0; i < ret; i++) {
630
        switch (msrs[i].index) {
631
        case MSR_IA32_SYSENTER_CS:
632
            env->sysenter_cs = msrs[i].data;
633
            break;
634
        case MSR_IA32_SYSENTER_ESP:
635
            env->sysenter_esp = msrs[i].data;
636
            break;
637
        case MSR_IA32_SYSENTER_EIP:
638
            env->sysenter_eip = msrs[i].data;
639
            break;
640
        case MSR_STAR:
641
            env->star = msrs[i].data;
642
            break;
643
#ifdef TARGET_X86_64
644
        case MSR_CSTAR:
645
            env->cstar = msrs[i].data;
646
            break;
647
        case MSR_KERNELGSBASE:
648
            env->kernelgsbase = msrs[i].data;
649
            break;
650
        case MSR_FMASK:
651
            env->fmask = msrs[i].data;
652
            break;
653
        case MSR_LSTAR:
654
            env->lstar = msrs[i].data;
655
            break;
656
#endif
657
        case MSR_IA32_TSC:
658
            env->tsc = msrs[i].data;
659
            break;
660
        }
661
    }
662

    
663
    return 0;
664
}
665

    
666
static int kvm_put_mp_state(CPUState *env)
667
{
668
    struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
669

    
670
    return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
671
}
672

    
673
static int kvm_get_mp_state(CPUState *env)
674
{
675
    struct kvm_mp_state mp_state;
676
    int ret;
677

    
678
    ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
679
    if (ret < 0) {
680
        return ret;
681
    }
682
    env->mp_state = mp_state.mp_state;
683
    return 0;
684
}
685

    
686
int kvm_arch_put_registers(CPUState *env)
687
{
688
    int ret;
689

    
690
    ret = kvm_getput_regs(env, 1);
691
    if (ret < 0)
692
        return ret;
693

    
694
    ret = kvm_put_fpu(env);
695
    if (ret < 0)
696
        return ret;
697

    
698
    ret = kvm_put_sregs(env);
699
    if (ret < 0)
700
        return ret;
701

    
702
    ret = kvm_put_msrs(env);
703
    if (ret < 0)
704
        return ret;
705

    
706
    ret = kvm_put_mp_state(env);
707
    if (ret < 0)
708
        return ret;
709

    
710
    ret = kvm_get_mp_state(env);
711
    if (ret < 0)
712
        return ret;
713

    
714
    return 0;
715
}
716

    
717
int kvm_arch_get_registers(CPUState *env)
718
{
719
    int ret;
720

    
721
    ret = kvm_getput_regs(env, 0);
722
    if (ret < 0)
723
        return ret;
724

    
725
    ret = kvm_get_fpu(env);
726
    if (ret < 0)
727
        return ret;
728

    
729
    ret = kvm_get_sregs(env);
730
    if (ret < 0)
731
        return ret;
732

    
733
    ret = kvm_get_msrs(env);
734
    if (ret < 0)
735
        return ret;
736

    
737
    return 0;
738
}
739

    
740
int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
741
{
742
    /* Try to inject an interrupt if the guest can accept it */
743
    if (run->ready_for_interrupt_injection &&
744
        (env->interrupt_request & CPU_INTERRUPT_HARD) &&
745
        (env->eflags & IF_MASK)) {
746
        int irq;
747

    
748
        env->interrupt_request &= ~CPU_INTERRUPT_HARD;
749
        irq = cpu_get_pic_interrupt(env);
750
        if (irq >= 0) {
751
            struct kvm_interrupt intr;
752
            intr.irq = irq;
753
            /* FIXME: errors */
754
            dprintf("injected interrupt %d\n", irq);
755
            kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
756
        }
757
    }
758

    
759
    /* If we have an interrupt but the guest is not ready to receive an
760
     * interrupt, request an interrupt window exit.  This will
761
     * cause a return to userspace as soon as the guest is ready to
762
     * receive interrupts. */
763
    if ((env->interrupt_request & CPU_INTERRUPT_HARD))
764
        run->request_interrupt_window = 1;
765
    else
766
        run->request_interrupt_window = 0;
767

    
768
    dprintf("setting tpr\n");
769
    run->cr8 = cpu_get_apic_tpr(env);
770

    
771
    return 0;
772
}
773

    
774
int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
775
{
776
    if (run->if_flag)
777
        env->eflags |= IF_MASK;
778
    else
779
        env->eflags &= ~IF_MASK;
780
    
781
    cpu_set_apic_tpr(env, run->cr8);
782
    cpu_set_apic_base(env, run->apic_base);
783

    
784
    return 0;
785
}
786

    
787
static int kvm_handle_halt(CPUState *env)
788
{
789
    if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
790
          (env->eflags & IF_MASK)) &&
791
        !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
792
        env->halted = 1;
793
        env->exception_index = EXCP_HLT;
794
        return 0;
795
    }
796

    
797
    return 1;
798
}
799

    
800
int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
801
{
802
    int ret = 0;
803

    
804
    switch (run->exit_reason) {
805
    case KVM_EXIT_HLT:
806
        dprintf("handle_hlt\n");
807
        ret = kvm_handle_halt(env);
808
        break;
809
    }
810

    
811
    return ret;
812
}
813

    
814
#ifdef KVM_CAP_SET_GUEST_DEBUG
815
int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
816
{
817
    static const uint8_t int3 = 0xcc;
818

    
819
    if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
820
        cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
821
        return -EINVAL;
822
    return 0;
823
}
824

    
825
int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
826
{
827
    uint8_t int3;
828

    
829
    if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
830
        cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
831
        return -EINVAL;
832
    return 0;
833
}
834

    
835
static struct {
836
    target_ulong addr;
837
    int len;
838
    int type;
839
} hw_breakpoint[4];
840

    
841
static int nb_hw_breakpoint;
842

    
843
static int find_hw_breakpoint(target_ulong addr, int len, int type)
844
{
845
    int n;
846

    
847
    for (n = 0; n < nb_hw_breakpoint; n++)
848
        if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
849
            (hw_breakpoint[n].len == len || len == -1))
850
            return n;
851
    return -1;
852
}
853

    
854
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
855
                                  target_ulong len, int type)
856
{
857
    switch (type) {
858
    case GDB_BREAKPOINT_HW:
859
        len = 1;
860
        break;
861
    case GDB_WATCHPOINT_WRITE:
862
    case GDB_WATCHPOINT_ACCESS:
863
        switch (len) {
864
        case 1:
865
            break;
866
        case 2:
867
        case 4:
868
        case 8:
869
            if (addr & (len - 1))
870
                return -EINVAL;
871
            break;
872
        default:
873
            return -EINVAL;
874
        }
875
        break;
876
    default:
877
        return -ENOSYS;
878
    }
879

    
880
    if (nb_hw_breakpoint == 4)
881
        return -ENOBUFS;
882

    
883
    if (find_hw_breakpoint(addr, len, type) >= 0)
884
        return -EEXIST;
885

    
886
    hw_breakpoint[nb_hw_breakpoint].addr = addr;
887
    hw_breakpoint[nb_hw_breakpoint].len = len;
888
    hw_breakpoint[nb_hw_breakpoint].type = type;
889
    nb_hw_breakpoint++;
890

    
891
    return 0;
892
}
893

    
894
int kvm_arch_remove_hw_breakpoint(target_ulong addr,
895
                                  target_ulong len, int type)
896
{
897
    int n;
898

    
899
    n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
900
    if (n < 0)
901
        return -ENOENT;
902

    
903
    nb_hw_breakpoint--;
904
    hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
905

    
906
    return 0;
907
}
908

    
909
void kvm_arch_remove_all_hw_breakpoints(void)
910
{
911
    nb_hw_breakpoint = 0;
912
}
913

    
914
static CPUWatchpoint hw_watchpoint;
915

    
916
int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
917
{
918
    int handle = 0;
919
    int n;
920

    
921
    if (arch_info->exception == 1) {
922
        if (arch_info->dr6 & (1 << 14)) {
923
            if (cpu_single_env->singlestep_enabled)
924
                handle = 1;
925
        } else {
926
            for (n = 0; n < 4; n++)
927
                if (arch_info->dr6 & (1 << n))
928
                    switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
929
                    case 0x0:
930
                        handle = 1;
931
                        break;
932
                    case 0x1:
933
                        handle = 1;
934
                        cpu_single_env->watchpoint_hit = &hw_watchpoint;
935
                        hw_watchpoint.vaddr = hw_breakpoint[n].addr;
936
                        hw_watchpoint.flags = BP_MEM_WRITE;
937
                        break;
938
                    case 0x3:
939
                        handle = 1;
940
                        cpu_single_env->watchpoint_hit = &hw_watchpoint;
941
                        hw_watchpoint.vaddr = hw_breakpoint[n].addr;
942
                        hw_watchpoint.flags = BP_MEM_ACCESS;
943
                        break;
944
                    }
945
        }
946
    } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
947
        handle = 1;
948

    
949
    if (!handle)
950
        kvm_update_guest_debug(cpu_single_env,
951
                        (arch_info->exception == 1) ?
952
                        KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
953

    
954
    return handle;
955
}
956

    
957
void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
958
{
959
    const uint8_t type_code[] = {
960
        [GDB_BREAKPOINT_HW] = 0x0,
961
        [GDB_WATCHPOINT_WRITE] = 0x1,
962
        [GDB_WATCHPOINT_ACCESS] = 0x3
963
    };
964
    const uint8_t len_code[] = {
965
        [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
966
    };
967
    int n;
968

    
969
    if (kvm_sw_breakpoints_active(env))
970
        dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
971

    
972
    if (nb_hw_breakpoint > 0) {
973
        dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
974
        dbg->arch.debugreg[7] = 0x0600;
975
        for (n = 0; n < nb_hw_breakpoint; n++) {
976
            dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
977
            dbg->arch.debugreg[7] |= (2 << (n * 2)) |
978
                (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
979
                (len_code[hw_breakpoint[n].len] << (18 + n*4));
980
        }
981
    }
982
}
983
#endif /* KVM_CAP_SET_GUEST_DEBUG */