Revision cb380f61

b/hw/mainstone.c
18 18 
#include "sysemu.h"
19 19 
#include "flash.h"
20 20 
#include "blockdev.h"
21 
#include "sysbus.h"
21 22 

  		





  22
  23
  
    
static struct keymap map[0xE0] = {


  		





  23
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    [0 ... 0xDF] = { -1, -1 },


  		





  ......




  77
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    uint32_t sector_len = 256 * 1024;


  		





  78
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    target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };


  		





  79
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    PXA2xxState *cpu;


  		





  80
  
  
    
    qemu_irq *mst_irq;


  		





  
  81
  
    
    DeviceState *mst_irq;


  		





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    DriveInfo *dinfo;


  		





  82
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    int i;


  		





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    int be;


  		





  ......




  117
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        }


  		





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    }


  		





  119
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  120
  
  
    
    mst_irq = mst_irq_init(MST_FPGA_PHYS, cpu->pic[PXA2XX_PIC_GPIO_0]);


  		





  
  121
  
    
    mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,


  		





  
  122
  
    
                    cpu->pic[PXA2XX_PIC_GPIO_0]);


  		





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    /* setup keypad */


  		





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    printf("map addr %p\n", &map);


  		





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    pxa27x_register_keypad(cpu->kp, map, 0xe0);


  		





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    /* MMC/SD host */


  		





  127
  
  
    
    pxa2xx_mmci_handlers(cpu->mmc, NULL, mst_irq[MMC_IRQ]);


  		





  
  129
  
    
    pxa2xx_mmci_handlers(cpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));


  		





  128
  130
  
    

  		





  129
  
  
    
    smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);


  		





  
  131
  
    
    smc91c111_init(&nd_table[0], MST_ETH_PHYS,


  		





  
  132
  
    
                    qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));


  		





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    mainstone_binfo.kernel_filename = kernel_filename;


  		





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    mainstone_binfo.kernel_cmdline = kernel_cmdline;


  		












  

    
      b/hw/mainstone.h
    
  






  32
  32
  
    
#define S1_STSCHG_IRQ 14


  		





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#define S1_IRQ        15


  		





  34
  34
  
    

  		





  35
  
  
    
extern qemu_irq


  		





  36
  
  
    
*mst_irq_init(uint32_t base, qemu_irq irq);


  		





  37
  
  
    

  		





  38
  35
  
    
#endif /* __MAINSTONE_H__ */


  		












  

    
      b/hw/mst_fpga.c
    
  






  8
  8
  
    
 * This code is licensed under the GNU GPL v2.


  		





  9
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 */


  		





  10
  10
  
    
#include "hw.h"


  		





  11
  
  
    
#include "mainstone.h"


  		





  
  11
  
    
#include "sysbus.h"


  		





  12
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/* Mainstone FPGA for extern irqs */


  		





  14
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#define FPGA_GPIO_PIN	0


  		





  ......




  27
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#define MST_PCMCIA1		0xe4


  		





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typedef struct mst_irq_state{


  		





  
  30
  
    
	SysBusDevice busdev;


  		





  
  31
  
    

  		





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	qemu_irq parent;


  		





  31
  
  
    
	qemu_irq *pins;


  		





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	uint32_t prev_level;


  		





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	uint32_t leddat1;


  		





  ......




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	mst_fpga_writeb,


  		





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};


  		





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  166
  
  
    
static void


  		





  167
  
  
    
mst_fpga_save(QEMUFile *f, void *opaque)


  		





  168
  
  
    
{


  		





  169
  
  
    
	struct mst_irq_state *s = (mst_irq_state *) opaque;


  		





  170
  
  
    

  		





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	qemu_put_be32s(f, &s->prev_level);


  		





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	qemu_put_be32s(f, &s->leddat1);


  		





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	qemu_put_be32s(f, &s->leddat2);


  		





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	qemu_put_be32s(f, &s->ledctrl);


  		





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	qemu_put_be32s(f, &s->gpswr);


  		





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	qemu_put_be32s(f, &s->mscwr1);


  		





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	qemu_put_be32s(f, &s->mscwr2);


  		





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	qemu_put_be32s(f, &s->mscwr3);


  		





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	qemu_put_be32s(f, &s->mscrd);


  		





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	qemu_put_be32s(f, &s->intmskena);


  		





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	qemu_put_be32s(f, &s->intsetclr);


  		





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	qemu_put_be32s(f, &s->pcmcia0);


  		





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	qemu_put_be32s(f, &s->pcmcia1);


  		





  184
  
  
    
}


  		





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  186
  
  
    
static int


  		





  187
  
  
    
mst_fpga_load(QEMUFile *f, void *opaque, int version_id)


  		





  
  168
  
    
static int mst_fpga_post_load(void *opaque, int version_id)


  		





  188
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{


  		





  189
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	mst_irq_state *s = (mst_irq_state *) opaque;


  		





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  191
  
  
    
	qemu_get_be32s(f, &s->prev_level);


  		





  192
  
  
    
	qemu_get_be32s(f, &s->leddat1);


  		





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	qemu_get_be32s(f, &s->leddat2);


  		





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	qemu_get_be32s(f, &s->ledctrl);


  		





  195
  
  
    
	qemu_get_be32s(f, &s->gpswr);


  		





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	qemu_get_be32s(f, &s->mscwr1);


  		





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	qemu_get_be32s(f, &s->mscwr2);


  		





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	qemu_get_be32s(f, &s->mscwr3);


  		





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	qemu_get_be32s(f, &s->mscrd);


  		





  200
  
  
    
	qemu_get_be32s(f, &s->intmskena);


  		





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	qemu_get_be32s(f, &s->intsetclr);


  		





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	qemu_get_be32s(f, &s->pcmcia0);


  		





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	qemu_get_be32s(f, &s->pcmcia1);


  		





  204
  
  
    

  		





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	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);


  		





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	return 0;


  		





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}


  		





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  209
  
  
    
qemu_irq *mst_irq_init(uint32_t base, qemu_irq irq)


  		





  
  176
  
    
static int mst_fpga_init(SysBusDevice *dev)


  		





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{


  		





  211
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	mst_irq_state *s;


  		





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	int iomemtype;


  		





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	qemu_irq *qi;


  		





  214
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  215
  
  
    
	s = (mst_irq_state  *)


  		





  216
  
  
    
		qemu_mallocz(sizeof(mst_irq_state));


  		





  
  181
  
    
	s = FROM_SYSBUS(mst_irq_state, dev);


  		





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  182
  
    

  		





  218
  
  
    
	s->parent = irq;


  		





  
  183
  
    
	sysbus_init_irq(dev, &s->parent);


  		





  219
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  220
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	/* alloc the external 16 irqs */


  		





  221
  
  
    
	qi  = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);


  		





  222
  
  
    
	s->pins = qi;


  		





  
  186
  
    
	qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);


  		





  223
  187
  
    

  		





  224
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	iomemtype = cpu_register_io_memory(mst_fpga_readfn,


  		





  225
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		mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);


  		





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	cpu_register_physical_memory(base, 0x00100000, iomemtype);


  		





  227
  
  
    
	register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save,


  		





  228
  
  
    
                        mst_fpga_load, s);


  		





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	return qi;


  		





  
  190
  
    
	sysbus_init_mmio(dev, 0x00100000, iomemtype);


  		





  
  191
  
    
	return 0;


  		





  
  192
  
    
}


  		





  
  193
  
    

  		





  
  194
  
    
static VMStateDescription vmstate_mst_fpga_regs = {


  		





  
  195
  
    
	.name = "mainstone_fpga",


  		





  
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	.version_id = 0,


  		





  
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	.minimum_version_id = 0,


  		





  
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	.minimum_version_id_old = 0,


  		





  
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	.post_load = mst_fpga_post_load,


  		





  
  200
  
    
	.fields = (VMStateField []) {


  		





  
  201
  
    
		VMSTATE_UINT32(prev_level, mst_irq_state),


  		





  
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		VMSTATE_UINT32(leddat1, mst_irq_state),


  		





  
  203
  
    
		VMSTATE_UINT32(leddat2, mst_irq_state),


  		





  
  204
  
    
		VMSTATE_UINT32(ledctrl, mst_irq_state),


  		





  
  205
  
    
		VMSTATE_UINT32(gpswr, mst_irq_state),


  		





  
  206
  
    
		VMSTATE_UINT32(mscwr1, mst_irq_state),


  		





  
  207
  
    
		VMSTATE_UINT32(mscwr2, mst_irq_state),


  		





  
  208
  
    
		VMSTATE_UINT32(mscwr3, mst_irq_state),


  		





  
  209
  
    
		VMSTATE_UINT32(mscrd, mst_irq_state),


  		





  
  210
  
    
		VMSTATE_UINT32(intmskena, mst_irq_state),


  		





  
  211
  
    
		VMSTATE_UINT32(intsetclr, mst_irq_state),


  		





  
  212
  
    
		VMSTATE_UINT32(pcmcia0, mst_irq_state),


  		





  
  213
  
    
		VMSTATE_UINT32(pcmcia1, mst_irq_state),


  		





  
  214
  
    
		VMSTATE_END_OF_LIST(),


  		





  
  215
  
    
	},


  		





  
  216
  
    
};


  		





  
  217
  
    

  		





  
  218
  
    
static SysBusDeviceInfo mst_fpga_info = {


  		





  
  219
  
    
	.init = mst_fpga_init,


  		





  
  220
  
    
	.qdev.name = "mainstone-fpga",


  		





  
  221
  
    
	.qdev.desc = "Mainstone II FPGA",


  		





  
  222
  
    
	.qdev.size = sizeof(mst_irq_state),


  		





  
  223
  
    
	.qdev.vmsd = &vmstate_mst_fpga_regs,


  		





  
  224
  
    
};


  		





  
  225
  
    

  		





  
  226
  
    
static void mst_fpga_register(void)


  		





  
  227
  
    
{


  		





  
  228
  
    
	sysbus_register_withprop(&mst_fpga_info);


  		





  230
  229
  
    
}


  		





  
  230
  
    
device_init(mst_fpga_register);


  		












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