Revision cb380f61 hw/mst_fpga.c

b/hw/mst_fpga.c
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 * This code is licensed under the GNU GPL v2.
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 */
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#include "hw.h"
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#include "mainstone.h"
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#include "sysbus.h"
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/* Mainstone FPGA for extern irqs */
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#define FPGA_GPIO_PIN	0
......
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#define MST_PCMCIA1		0xe4
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typedef struct mst_irq_state{
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	SysBusDevice busdev;
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	qemu_irq parent;
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	qemu_irq *pins;
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	uint32_t prev_level;
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	uint32_t leddat1;
......
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	mst_fpga_writeb,
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};
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static void
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mst_fpga_save(QEMUFile *f, void *opaque)
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{
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	struct mst_irq_state *s = (mst_irq_state *) opaque;
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	qemu_put_be32s(f, &s->prev_level);
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	qemu_put_be32s(f, &s->leddat1);
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	qemu_put_be32s(f, &s->leddat2);
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	qemu_put_be32s(f, &s->ledctrl);
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	qemu_put_be32s(f, &s->gpswr);
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	qemu_put_be32s(f, &s->mscwr1);
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	qemu_put_be32s(f, &s->mscwr2);
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	qemu_put_be32s(f, &s->mscwr3);
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	qemu_put_be32s(f, &s->mscrd);
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	qemu_put_be32s(f, &s->intmskena);
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	qemu_put_be32s(f, &s->intsetclr);
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	qemu_put_be32s(f, &s->pcmcia0);
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	qemu_put_be32s(f, &s->pcmcia1);
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}
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static int
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mst_fpga_load(QEMUFile *f, void *opaque, int version_id)
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static int mst_fpga_post_load(void *opaque, int version_id)
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{
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	mst_irq_state *s = (mst_irq_state *) opaque;
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	qemu_get_be32s(f, &s->prev_level);
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	qemu_get_be32s(f, &s->leddat1);
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	qemu_get_be32s(f, &s->leddat2);
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	qemu_get_be32s(f, &s->ledctrl);
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	qemu_get_be32s(f, &s->gpswr);
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	qemu_get_be32s(f, &s->mscwr1);
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	qemu_get_be32s(f, &s->mscwr2);
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	qemu_get_be32s(f, &s->mscwr3);
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	qemu_get_be32s(f, &s->mscrd);
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	qemu_get_be32s(f, &s->intmskena);
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	qemu_get_be32s(f, &s->intsetclr);
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	qemu_get_be32s(f, &s->pcmcia0);
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	qemu_get_be32s(f, &s->pcmcia1);
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	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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	return 0;
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}
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qemu_irq *mst_irq_init(uint32_t base, qemu_irq irq)
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static int mst_fpga_init(SysBusDevice *dev)
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{
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	mst_irq_state *s;
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	int iomemtype;
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	qemu_irq *qi;
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	s = (mst_irq_state  *)
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		qemu_mallocz(sizeof(mst_irq_state));
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	s = FROM_SYSBUS(mst_irq_state, dev);
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	s->parent = irq;
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	sysbus_init_irq(dev, &s->parent);
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	/* alloc the external 16 irqs */
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	qi  = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);
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	s->pins = qi;
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	qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
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	iomemtype = cpu_register_io_memory(mst_fpga_readfn,
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		mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
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	cpu_register_physical_memory(base, 0x00100000, iomemtype);
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	register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save,
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                        mst_fpga_load, s);
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	return qi;
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	sysbus_init_mmio(dev, 0x00100000, iomemtype);
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	return 0;
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}
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static VMStateDescription vmstate_mst_fpga_regs = {
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	.name = "mainstone_fpga",
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	.version_id = 0,
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	.minimum_version_id = 0,
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	.minimum_version_id_old = 0,
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	.post_load = mst_fpga_post_load,
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	.fields = (VMStateField []) {
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		VMSTATE_UINT32(prev_level, mst_irq_state),
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		VMSTATE_UINT32(leddat1, mst_irq_state),
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		VMSTATE_UINT32(leddat2, mst_irq_state),
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		VMSTATE_UINT32(ledctrl, mst_irq_state),
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		VMSTATE_UINT32(gpswr, mst_irq_state),
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		VMSTATE_UINT32(mscwr1, mst_irq_state),
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		VMSTATE_UINT32(mscwr2, mst_irq_state),
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		VMSTATE_UINT32(mscwr3, mst_irq_state),
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		VMSTATE_UINT32(mscrd, mst_irq_state),
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		VMSTATE_UINT32(intmskena, mst_irq_state),
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		VMSTATE_UINT32(intsetclr, mst_irq_state),
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		VMSTATE_UINT32(pcmcia0, mst_irq_state),
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		VMSTATE_UINT32(pcmcia1, mst_irq_state),
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		VMSTATE_END_OF_LIST(),
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	},
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};
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static SysBusDeviceInfo mst_fpga_info = {
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	.init = mst_fpga_init,
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	.qdev.name = "mainstone-fpga",
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	.qdev.desc = "Mainstone II FPGA",
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	.qdev.size = sizeof(mst_irq_state),
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	.qdev.vmsd = &vmstate_mst_fpga_regs,
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};
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static void mst_fpga_register(void)
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{
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	sysbus_register_withprop(&mst_fpga_info);
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}
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device_init(mst_fpga_register);

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