Revision cb63669a target-arm/translate.c
| b/target-arm/translate.c | ||
|---|---|---|
| 662 | 662 |
{
|
| 663 | 663 |
TCGv tmp; |
| 664 | 664 |
TCGv tmp2; |
| 665 |
TCGv zero; |
|
| 666 | 665 |
int inv; |
| 667 | 666 |
|
| 668 |
zero = tcg_const_i32(0); |
|
| 669 | 667 |
switch (cc) {
|
| 670 | 668 |
case 0: /* eq: Z */ |
| 671 | 669 |
tmp = load_cpu_field(ZF); |
| 672 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label);
|
|
| 670 |
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
|
|
| 673 | 671 |
break; |
| 674 | 672 |
case 1: /* ne: !Z */ |
| 675 | 673 |
tmp = load_cpu_field(ZF); |
| 676 |
tcg_gen_brcond_i32(TCG_COND_NE, tmp, zero, label);
|
|
| 674 |
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
|
|
| 677 | 675 |
break; |
| 678 | 676 |
case 2: /* cs: C */ |
| 679 | 677 |
tmp = load_cpu_field(CF); |
| 680 |
tcg_gen_brcond_i32(TCG_COND_NE, tmp, zero, label);
|
|
| 678 |
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
|
|
| 681 | 679 |
break; |
| 682 | 680 |
case 3: /* cc: !C */ |
| 683 | 681 |
tmp = load_cpu_field(CF); |
| 684 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label);
|
|
| 682 |
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
|
|
| 685 | 683 |
break; |
| 686 | 684 |
case 4: /* mi: N */ |
| 687 | 685 |
tmp = load_cpu_field(NF); |
| 688 |
tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label);
|
|
| 686 |
tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
|
|
| 689 | 687 |
break; |
| 690 | 688 |
case 5: /* pl: !N */ |
| 691 | 689 |
tmp = load_cpu_field(NF); |
| 692 |
tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label);
|
|
| 690 |
tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
|
|
| 693 | 691 |
break; |
| 694 | 692 |
case 6: /* vs: V */ |
| 695 | 693 |
tmp = load_cpu_field(VF); |
| 696 |
tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label);
|
|
| 694 |
tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
|
|
| 697 | 695 |
break; |
| 698 | 696 |
case 7: /* vc: !V */ |
| 699 | 697 |
tmp = load_cpu_field(VF); |
| 700 |
tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label);
|
|
| 698 |
tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
|
|
| 701 | 699 |
break; |
| 702 | 700 |
case 8: /* hi: C && !Z */ |
| 703 | 701 |
inv = gen_new_label(); |
| 704 | 702 |
tmp = load_cpu_field(CF); |
| 705 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, inv);
|
|
| 703 |
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
|
|
| 706 | 704 |
dead_tmp(tmp); |
| 707 | 705 |
tmp = load_cpu_field(ZF); |
| 708 |
tcg_gen_brcond_i32(TCG_COND_NE, tmp, zero, label);
|
|
| 706 |
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
|
|
| 709 | 707 |
gen_set_label(inv); |
| 710 | 708 |
break; |
| 711 | 709 |
case 9: /* ls: !C || Z */ |
| 712 | 710 |
tmp = load_cpu_field(CF); |
| 713 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label);
|
|
| 711 |
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
|
|
| 714 | 712 |
dead_tmp(tmp); |
| 715 | 713 |
tmp = load_cpu_field(ZF); |
| 716 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label);
|
|
| 714 |
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
|
|
| 717 | 715 |
break; |
| 718 | 716 |
case 10: /* ge: N == V -> N ^ V == 0 */ |
| 719 | 717 |
tmp = load_cpu_field(VF); |
| 720 | 718 |
tmp2 = load_cpu_field(NF); |
| 721 | 719 |
tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 722 | 720 |
dead_tmp(tmp2); |
| 723 |
tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label);
|
|
| 721 |
tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
|
|
| 724 | 722 |
break; |
| 725 | 723 |
case 11: /* lt: N != V -> N ^ V != 0 */ |
| 726 | 724 |
tmp = load_cpu_field(VF); |
| 727 | 725 |
tmp2 = load_cpu_field(NF); |
| 728 | 726 |
tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 729 | 727 |
dead_tmp(tmp2); |
| 730 |
tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label);
|
|
| 728 |
tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
|
|
| 731 | 729 |
break; |
| 732 | 730 |
case 12: /* gt: !Z && N == V */ |
| 733 | 731 |
inv = gen_new_label(); |
| 734 | 732 |
tmp = load_cpu_field(ZF); |
| 735 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, inv);
|
|
| 733 |
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
|
|
| 736 | 734 |
dead_tmp(tmp); |
| 737 | 735 |
tmp = load_cpu_field(VF); |
| 738 | 736 |
tmp2 = load_cpu_field(NF); |
| 739 | 737 |
tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 740 | 738 |
dead_tmp(tmp2); |
| 741 |
tcg_gen_brcond_i32(TCG_COND_GE, tmp, zero, label);
|
|
| 739 |
tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
|
|
| 742 | 740 |
gen_set_label(inv); |
| 743 | 741 |
break; |
| 744 | 742 |
case 13: /* le: Z || N != V */ |
| 745 | 743 |
tmp = load_cpu_field(ZF); |
| 746 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, zero, label);
|
|
| 744 |
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
|
|
| 747 | 745 |
dead_tmp(tmp); |
| 748 | 746 |
tmp = load_cpu_field(VF); |
| 749 | 747 |
tmp2 = load_cpu_field(NF); |
| 750 | 748 |
tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 751 | 749 |
dead_tmp(tmp2); |
| 752 |
tcg_gen_brcond_i32(TCG_COND_LT, tmp, zero, label);
|
|
| 750 |
tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
|
|
| 753 | 751 |
break; |
| 754 | 752 |
default: |
| 755 | 753 |
fprintf(stderr, "Bad condition code 0x%x\n", cc); |
| ... | ... | |
| 6233 | 6231 |
int label = gen_new_label(); |
| 6234 | 6232 |
rm = insn & 0xf; |
| 6235 | 6233 |
gen_helper_test_exclusive(cpu_T[0], cpu_env, addr); |
| 6236 |
tcg_gen_brcond_i32(TCG_COND_NE, cpu_T[0], |
|
| 6237 |
tcg_const_i32(0), label);
|
|
| 6234 |
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0],
|
|
| 6235 |
0, label);
|
|
| 6238 | 6236 |
tmp = load_reg(s,rm); |
| 6239 | 6237 |
gen_st32(tmp, cpu_T[1], IS_USER(s)); |
| 6240 | 6238 |
gen_set_label(label); |
| ... | ... | |
| 6984 | 6982 |
} else {
|
| 6985 | 6983 |
int label = gen_new_label(); |
| 6986 | 6984 |
gen_helper_test_exclusive(cpu_T[0], cpu_env, addr); |
| 6987 |
tcg_gen_brcond_i32(TCG_COND_NE, cpu_T[0], |
|
| 6988 |
tcg_const_i32(0), label);
|
|
| 6985 |
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0],
|
|
| 6986 |
0, label);
|
|
| 6989 | 6987 |
tmp = load_reg(s, rs); |
| 6990 | 6988 |
gen_st32(tmp, cpu_T[1], IS_USER(s)); |
| 6991 | 6989 |
gen_set_label(label); |
| ... | ... | |
| 7047 | 7045 |
int label = gen_new_label(); |
| 7048 | 7046 |
/* Must use a global that is not killed by the branch. */ |
| 7049 | 7047 |
gen_helper_test_exclusive(cpu_T[0], cpu_env, addr); |
| 7050 |
tcg_gen_brcond_i32(TCG_COND_NE, cpu_T[0], tcg_const_i32(0), |
|
| 7051 |
label); |
|
| 7048 |
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0], 0, label); |
|
| 7052 | 7049 |
tmp = load_reg(s, rs); |
| 7053 | 7050 |
switch (op) {
|
| 7054 | 7051 |
case 0: |
| ... | ... | |
| 8364 | 8361 |
case 1: case 3: case 9: case 11: /* czb */ |
| 8365 | 8362 |
rm = insn & 7; |
| 8366 | 8363 |
tmp = load_reg(s, rm); |
| 8367 |
tmp2 = tcg_const_i32(0); |
|
| 8368 | 8364 |
s->condlabel = gen_new_label(); |
| 8369 | 8365 |
s->condjmp = 1; |
| 8370 | 8366 |
if (insn & (1 << 11)) |
| 8371 |
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, s->condlabel);
|
|
| 8367 |
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
|
|
| 8372 | 8368 |
else |
| 8373 |
tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, s->condlabel);
|
|
| 8369 |
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
|
|
| 8374 | 8370 |
dead_tmp(tmp); |
| 8375 | 8371 |
offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; |
| 8376 | 8372 |
val = (uint32_t)s->pc + 2; |
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