Revision cbfb6ae9 target-ppc/translate.c

b/target-ppc/translate.c
6144 6144
    tcg_temp_free(EA);                                                        \
6145 6145
}
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6147
#define GEN_VR_LVE(name, opc2, opc3)                                    \
6148
    GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)   \
6149
    {                                                                   \
6150
        TCGv EA;                                                        \
6151
        TCGv_ptr rs;                                                    \
6152
        if (unlikely(!ctx->altivec_enabled)) {                          \
6153
            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
6154
            return;                                                     \
6155
        }                                                               \
6156
        gen_set_access_type(ctx, ACCESS_INT);                           \
6157
        EA = tcg_temp_new();                                            \
6158
        gen_addr_reg_index(ctx, EA);                                    \
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        rs = gen_avr_ptr(rS(ctx->opcode));                              \
6160
        gen_helper_lve##name (rs, EA);                                  \
6161
        tcg_temp_free(EA);                                              \
6162
        tcg_temp_free_ptr(rs);                                          \
6163
    }
6164

  
6165
#define GEN_VR_STVE(name, opc2, opc3)                                   \
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    GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)  \
6167
    {                                                                   \
6168
        TCGv EA;                                                        \
6169
        TCGv_ptr rs;                                                    \
6170
        if (unlikely(!ctx->altivec_enabled)) {                          \
6171
            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
6172
            return;                                                     \
6173
        }                                                               \
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        gen_set_access_type(ctx, ACCESS_INT);                           \
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        EA = tcg_temp_new();                                            \
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        gen_addr_reg_index(ctx, EA);                                    \
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        rs = gen_avr_ptr(rS(ctx->opcode));                              \
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        gen_helper_stve##name (rs, EA);                                 \
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        tcg_temp_free(EA);                                              \
6180
        tcg_temp_free_ptr(rs);                                          \
6181
    }
6182

  
6147 6183
GEN_VR_LDX(lvx, 0x07, 0x03);
6148 6184
/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6149 6185
GEN_VR_LDX(lvxl, 0x07, 0x0B);
6150 6186

  
6187
GEN_VR_LVE(bx, 0x07, 0x00);
6188
GEN_VR_LVE(hx, 0x07, 0x01);
6189
GEN_VR_LVE(wx, 0x07, 0x02);
6190

  
6151 6191
GEN_VR_STX(svx, 0x07, 0x07);
6152 6192
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6153 6193
GEN_VR_STX(svxl, 0x07, 0x0F);
6154 6194

  
6195
GEN_VR_STVE(bx, 0x07, 0x04);
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GEN_VR_STVE(hx, 0x07, 0x05);
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GEN_VR_STVE(wx, 0x07, 0x06);
6198

  
6155 6199
GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6156 6200
{
6157 6201
    TCGv_ptr rd;

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