Revision cc9577cf hw/omap2.c
b/hw/omap2.c | ||
---|---|---|
1245 | 1245 |
return base; |
1246 | 1246 |
} |
1247 | 1247 |
|
1248 |
/* TEST-Chip-level TAP */ |
|
1249 |
static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr) |
|
1250 |
{ |
|
1251 |
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
1252 |
|
|
1253 |
switch (addr) { |
|
1254 |
case 0x204: /* IDCODE_reg */ |
|
1255 |
switch (s->mpu_model) { |
|
1256 |
case omap2420: |
|
1257 |
case omap2422: |
|
1258 |
case omap2423: |
|
1259 |
return 0x5b5d902f; /* ES 2.2 */ |
|
1260 |
case omap2430: |
|
1261 |
return 0x5b68a02f; /* ES 2.2 */ |
|
1262 |
case omap3430: |
|
1263 |
return 0x1b7ae02f; /* ES 2 */ |
|
1264 |
default: |
|
1265 |
hw_error("%s: Bad mpu model\n", __FUNCTION__); |
|
1266 |
} |
|
1267 |
|
|
1268 |
case 0x208: /* PRODUCTION_ID_reg for OMAP2 */ |
|
1269 |
case 0x210: /* PRODUCTION_ID_reg for OMAP3 */ |
|
1270 |
switch (s->mpu_model) { |
|
1271 |
case omap2420: |
|
1272 |
return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ |
|
1273 |
case omap2422: |
|
1274 |
return 0x000400f0; |
|
1275 |
case omap2423: |
|
1276 |
return 0x000800f0; |
|
1277 |
case omap2430: |
|
1278 |
return 0x000000f0; |
|
1279 |
case omap3430: |
|
1280 |
return 0x000000f0; |
|
1281 |
default: |
|
1282 |
hw_error("%s: Bad mpu model\n", __FUNCTION__); |
|
1283 |
} |
|
1284 |
|
|
1285 |
case 0x20c: |
|
1286 |
switch (s->mpu_model) { |
|
1287 |
case omap2420: |
|
1288 |
case omap2422: |
|
1289 |
case omap2423: |
|
1290 |
return 0xcafeb5d9; /* ES 2.2 */ |
|
1291 |
case omap2430: |
|
1292 |
return 0xcafeb68a; /* ES 2.2 */ |
|
1293 |
case omap3430: |
|
1294 |
return 0xcafeb7ae; /* ES 2 */ |
|
1295 |
default: |
|
1296 |
hw_error("%s: Bad mpu model\n", __FUNCTION__); |
|
1297 |
} |
|
1298 |
|
|
1299 |
case 0x218: /* DIE_ID_reg */ |
|
1300 |
return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
|
1301 |
case 0x21c: /* DIE_ID_reg */ |
|
1302 |
return 0x54 << 24; |
|
1303 |
case 0x220: /* DIE_ID_reg */ |
|
1304 |
return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
|
1305 |
case 0x224: /* DIE_ID_reg */ |
|
1306 |
return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); |
|
1307 |
} |
|
1308 |
|
|
1309 |
OMAP_BAD_REG(addr); |
|
1310 |
return 0; |
|
1311 |
} |
|
1312 |
|
|
1313 |
static void omap_tap_write(void *opaque, target_phys_addr_t addr, |
|
1314 |
uint32_t value) |
|
1315 |
{ |
|
1316 |
OMAP_BAD_REG(addr); |
|
1317 |
} |
|
1318 |
|
|
1319 |
static CPUReadMemoryFunc * const omap_tap_readfn[] = { |
|
1320 |
omap_badwidth_read32, |
|
1321 |
omap_badwidth_read32, |
|
1322 |
omap_tap_read, |
|
1323 |
}; |
|
1324 |
|
|
1325 |
static CPUWriteMemoryFunc * const omap_tap_writefn[] = { |
|
1326 |
omap_badwidth_write32, |
|
1327 |
omap_badwidth_write32, |
|
1328 |
omap_tap_write, |
|
1329 |
}; |
|
1330 |
|
|
1331 |
void omap_tap_init(struct omap_target_agent_s *ta, |
|
1332 |
struct omap_mpu_state_s *mpu) |
|
1333 |
{ |
|
1334 |
omap_l4_attach(ta, 0, l4_register_io_memory( |
|
1335 |
omap_tap_readfn, omap_tap_writefn, mpu)); |
|
1336 |
} |
|
1337 |
|
|
1338 | 1248 |
/* Power, Reset, and Clock Management */ |
1339 | 1249 |
struct omap_prcm_s { |
1340 | 1250 |
qemu_irq irq[3]; |
Also available in: Unified diff