Revision ccc9cc5b target-sh4/translate.c
| b/target-sh4/translate.c | ||
|---|---|---|
| 337 | 337 |
gen_op_movl_imm_rN(B7_0s, REG(B11_8)); |
| 338 | 338 |
return; |
| 339 | 339 |
case 0x9000: /* mov.w @(disp,PC),Rn */ |
| 340 |
gen_op_movl_imm_T0(ctx->pc + 4 + B7_0 * 2);
|
|
| 340 |
tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
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|
| 341 | 341 |
gen_op_ldw_T0_T0(ctx); |
| 342 | 342 |
gen_op_movl_T0_rN(REG(B11_8)); |
| 343 | 343 |
return; |
| 344 | 344 |
case 0xd000: /* mov.l @(disp,PC),Rn */ |
| 345 |
gen_op_movl_imm_T0((ctx->pc + 4 + B7_0 * 4) & ~3);
|
|
| 345 |
tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
|
|
| 346 | 346 |
gen_op_ldl_T0_T0(ctx); |
| 347 | 347 |
gen_op_movl_T0_rN(REG(B11_8)); |
| 348 | 348 |
return; |
| ... | ... | |
| 1181 | 1181 |
break; |
| 1182 | 1182 |
case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
| 1183 | 1183 |
if (!(ctx->fpscr & FPSCR_PR)) {
|
| 1184 |
gen_op_movl_imm_T0(0);
|
|
| 1184 |
tcg_gen_movi_tl(cpu_T[0], 0);
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|
| 1185 | 1185 |
gen_op_fmov_T0_frN(FREG(B11_8)); |
| 1186 | 1186 |
return; |
| 1187 | 1187 |
} |
| 1188 | 1188 |
break; |
| 1189 | 1189 |
case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
| 1190 | 1190 |
if (!(ctx->fpscr & FPSCR_PR)) {
|
| 1191 |
gen_op_movl_imm_T0(0x3f800000);
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|
| 1191 |
tcg_gen_movi_tl(cpu_T[0], 0x3f800000);
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|
| 1192 | 1192 |
gen_op_fmov_T0_frN(FREG(B11_8)); |
| 1193 | 1193 |
return; |
| 1194 | 1194 |
} |
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