Revision ccd4a219
| b/target-sparc/cpu.h | ||
|---|---|---|
| 320 | 320 |
void raise_exception(int tt); |
| 321 | 321 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
| 322 | 322 |
int is_asi); |
| 323 |
void do_tick_set_count(void *opaque, uint64_t count); |
|
| 324 |
uint64_t do_tick_get_count(void *opaque); |
|
| 325 |
void do_tick_set_limit(void *opaque, uint64_t limit); |
|
| 326 | 323 |
void cpu_check_irqs(CPUSPARCState *env); |
| 327 | 324 |
|
| 328 | 325 |
#define CPUState CPUSPARCState |
| b/target-sparc/helper.c | ||
|---|---|---|
| 612 | 612 |
#include "qemu-timer.h" |
| 613 | 613 |
#endif |
| 614 | 614 |
|
| 615 |
void do_tick_set_count(void *opaque, uint64_t count)
|
|
| 615 |
void helper_tick_set_count(void *opaque, uint64_t count)
|
|
| 616 | 616 |
{
|
| 617 | 617 |
#if !defined(CONFIG_USER_ONLY) |
| 618 | 618 |
ptimer_set_count(opaque, -count); |
| 619 | 619 |
#endif |
| 620 | 620 |
} |
| 621 | 621 |
|
| 622 |
uint64_t do_tick_get_count(void *opaque)
|
|
| 622 |
uint64_t helper_tick_get_count(void *opaque)
|
|
| 623 | 623 |
{
|
| 624 | 624 |
#if !defined(CONFIG_USER_ONLY) |
| 625 | 625 |
return -ptimer_get_count(opaque); |
| ... | ... | |
| 628 | 628 |
#endif |
| 629 | 629 |
} |
| 630 | 630 |
|
| 631 |
void do_tick_set_limit(void *opaque, uint64_t limit)
|
|
| 631 |
void helper_tick_set_limit(void *opaque, uint64_t limit)
|
|
| 632 | 632 |
{
|
| 633 | 633 |
#if !defined(CONFIG_USER_ONLY) |
| 634 | 634 |
ptimer_set_limit(opaque, -limit, 0); |
| b/target-sparc/helper.h | ||
|---|---|---|
| 19 | 19 |
target_ulong TCG_HELPER_PROTO |
| 20 | 20 |
helper_casx_asi(target_ulong addr, target_ulong val1, |
| 21 | 21 |
target_ulong val2, uint32_t asi); |
| 22 |
void TCG_HELPER_PROTO helper_tick_set_count(void *opaque, uint64_t count); |
|
| 23 |
uint64_t TCG_HELPER_PROTO helper_tick_get_count(void *opaque); |
|
| 24 |
void TCG_HELPER_PROTO helper_tick_set_limit(void *opaque, uint64_t limit); |
|
| 22 | 25 |
#endif |
| 23 | 26 |
void TCG_HELPER_PROTO helper_trap(target_ulong nb_trap); |
| 24 | 27 |
void TCG_HELPER_PROTO helper_trapcc(target_ulong nb_trap, |
| b/target-sparc/op.c | ||
|---|---|---|
| 806 | 806 |
PUT_CCR(env, T0); |
| 807 | 807 |
} |
| 808 | 808 |
|
| 809 |
void OPPROTO op_rdtick(void) |
|
| 810 |
{
|
|
| 811 |
T0 = do_tick_get_count(env->tick); |
|
| 812 |
} |
|
| 813 |
|
|
| 814 |
void OPPROTO op_wrtick(void) |
|
| 815 |
{
|
|
| 816 |
do_tick_set_count(env->tick, T0); |
|
| 817 |
} |
|
| 818 |
|
|
| 819 |
void OPPROTO op_wrtick_cmpr(void) |
|
| 820 |
{
|
|
| 821 |
do_tick_set_limit(env->tick, T0); |
|
| 822 |
} |
|
| 823 |
|
|
| 824 |
void OPPROTO op_rdstick(void) |
|
| 825 |
{
|
|
| 826 |
T0 = do_tick_get_count(env->stick); |
|
| 827 |
} |
|
| 828 |
|
|
| 829 |
void OPPROTO op_wrstick(void) |
|
| 830 |
{
|
|
| 831 |
do_tick_set_count(env->stick, T0); |
|
| 832 |
do_tick_set_count(env->hstick, T0); |
|
| 833 |
} |
|
| 834 |
|
|
| 835 |
void OPPROTO op_wrstick_cmpr(void) |
|
| 836 |
{
|
|
| 837 |
do_tick_set_limit(env->stick, T0); |
|
| 838 |
} |
|
| 839 |
|
|
| 840 |
void OPPROTO op_wrhstick_cmpr(void) |
|
| 841 |
{
|
|
| 842 |
do_tick_set_limit(env->hstick, T0); |
|
| 843 |
} |
|
| 844 |
|
|
| 845 | 809 |
void OPPROTO op_rdtpc(void) |
| 846 | 810 |
{
|
| 847 | 811 |
T0 = env->tpc[env->tl]; |
| b/target-sparc/translate.c | ||
|---|---|---|
| 1204 | 1204 |
gen_movl_T0_reg(rd); |
| 1205 | 1205 |
break; |
| 1206 | 1206 |
case 0x4: /* V9 rdtick */ |
| 1207 |
gen_op_rdtick(); |
|
| 1208 |
gen_movl_T0_reg(rd); |
|
| 1207 |
{
|
|
| 1208 |
TCGv r_tickptr; |
|
| 1209 |
|
|
| 1210 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 1211 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
|
| 1212 |
offsetof(CPUState, tick)); |
|
| 1213 |
tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], |
|
| 1214 |
r_tickptr); |
|
| 1215 |
gen_movl_T0_reg(rd); |
|
| 1216 |
} |
|
| 1209 | 1217 |
break; |
| 1210 | 1218 |
case 0x5: /* V9 rdpc */ |
| 1211 | 1219 |
tcg_gen_movi_tl(cpu_T[0], dc->pc); |
| ... | ... | |
| 1228 | 1236 |
gen_movl_T0_reg(rd); |
| 1229 | 1237 |
break; |
| 1230 | 1238 |
case 0x18: /* System tick */ |
| 1231 |
gen_op_rdstick(); |
|
| 1232 |
gen_movl_T0_reg(rd); |
|
| 1239 |
{
|
|
| 1240 |
TCGv r_tickptr; |
|
| 1241 |
|
|
| 1242 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 1243 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
|
| 1244 |
offsetof(CPUState, stick)); |
|
| 1245 |
tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], |
|
| 1246 |
r_tickptr); |
|
| 1247 |
gen_movl_T0_reg(rd); |
|
| 1248 |
} |
|
| 1233 | 1249 |
break; |
| 1234 | 1250 |
case 0x19: /* System tick compare */ |
| 1235 | 1251 |
gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr)); |
| ... | ... | |
| 1299 | 1315 |
gen_op_rdtt(); |
| 1300 | 1316 |
break; |
| 1301 | 1317 |
case 4: // tick |
| 1302 |
gen_op_rdtick(); |
|
| 1318 |
{
|
|
| 1319 |
TCGv r_tickptr; |
|
| 1320 |
|
|
| 1321 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 1322 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
|
| 1323 |
offsetof(CPUState, tick)); |
|
| 1324 |
tcg_gen_helper_1_1(helper_tick_get_count, cpu_T[0], |
|
| 1325 |
r_tickptr); |
|
| 1326 |
gen_movl_T0_reg(rd); |
|
| 1327 |
} |
|
| 1303 | 1328 |
break; |
| 1304 | 1329 |
case 5: // tba |
| 1305 | 1330 |
gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr)); |
| ... | ... | |
| 2281 | 2306 |
if (!supervisor(dc)) |
| 2282 | 2307 |
goto illegal_insn; |
| 2283 | 2308 |
#endif |
| 2284 |
gen_op_xor_T1_T0(); |
|
| 2285 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr)); |
|
| 2286 |
gen_op_wrtick_cmpr(); |
|
| 2309 |
{
|
|
| 2310 |
TCGv r_tickptr; |
|
| 2311 |
|
|
| 2312 |
gen_op_xor_T1_T0(); |
|
| 2313 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, |
|
| 2314 |
tick_cmpr)); |
|
| 2315 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 2316 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
|
| 2317 |
offsetof(CPUState, tick)); |
|
| 2318 |
tcg_gen_helper_0_2(helper_tick_set_limit, |
|
| 2319 |
r_tickptr, cpu_T[0]); |
|
| 2320 |
} |
|
| 2287 | 2321 |
break; |
| 2288 | 2322 |
case 0x18: /* System tick */ |
| 2289 | 2323 |
#if !defined(CONFIG_USER_ONLY) |
| 2290 | 2324 |
if (!supervisor(dc)) |
| 2291 | 2325 |
goto illegal_insn; |
| 2292 | 2326 |
#endif |
| 2293 |
gen_op_xor_T1_T0(); |
|
| 2294 |
gen_op_wrstick(); |
|
| 2327 |
{
|
|
| 2328 |
TCGv r_tickptr; |
|
| 2329 |
|
|
| 2330 |
gen_op_xor_T1_T0(); |
|
| 2331 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 2332 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
|
| 2333 |
offsetof(CPUState, stick)); |
|
| 2334 |
tcg_gen_helper_0_2(helper_tick_set_count, |
|
| 2335 |
r_tickptr, cpu_T[0]); |
|
| 2336 |
} |
|
| 2295 | 2337 |
break; |
| 2296 | 2338 |
case 0x19: /* System tick compare */ |
| 2297 | 2339 |
#if !defined(CONFIG_USER_ONLY) |
| 2298 | 2340 |
if (!supervisor(dc)) |
| 2299 | 2341 |
goto illegal_insn; |
| 2300 | 2342 |
#endif |
| 2301 |
gen_op_xor_T1_T0(); |
|
| 2302 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr)); |
|
| 2303 |
gen_op_wrstick_cmpr(); |
|
| 2343 |
{
|
|
| 2344 |
TCGv r_tickptr; |
|
| 2345 |
|
|
| 2346 |
gen_op_xor_T1_T0(); |
|
| 2347 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, |
|
| 2348 |
stick_cmpr)); |
|
| 2349 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 2350 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
|
| 2351 |
offsetof(CPUState, stick)); |
|
| 2352 |
tcg_gen_helper_0_2(helper_tick_set_limit, |
|
| 2353 |
r_tickptr, cpu_T[0]); |
|
| 2354 |
} |
|
| 2304 | 2355 |
break; |
| 2305 | 2356 |
|
| 2306 | 2357 |
case 0x10: /* Performance Control */ |
| ... | ... | |
| 2366 | 2417 |
gen_op_wrtt(); |
| 2367 | 2418 |
break; |
| 2368 | 2419 |
case 4: // tick |
| 2369 |
gen_op_wrtick(); |
|
| 2420 |
{
|
|
| 2421 |
TCGv r_tickptr; |
|
| 2422 |
|
|
| 2423 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 2424 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
|
| 2425 |
offsetof(CPUState, tick)); |
|
| 2426 |
tcg_gen_helper_0_2(helper_tick_set_count, |
|
| 2427 |
r_tickptr, cpu_T[0]); |
|
| 2428 |
} |
|
| 2370 | 2429 |
break; |
| 2371 | 2430 |
case 5: // tba |
| 2372 | 2431 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr)); |
| ... | ... | |
| 2448 | 2507 |
gen_op_movl_env_T0(offsetof(CPUSPARCState, htba)); |
| 2449 | 2508 |
break; |
| 2450 | 2509 |
case 31: // hstick_cmpr |
| 2451 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr)); |
|
| 2452 |
gen_op_wrhstick_cmpr(); |
|
| 2510 |
{
|
|
| 2511 |
TCGv r_tickptr; |
|
| 2512 |
|
|
| 2513 |
gen_op_movtl_env_T0(offsetof(CPUSPARCState, |
|
| 2514 |
hstick_cmpr)); |
|
| 2515 |
r_tickptr = tcg_temp_new(TCG_TYPE_PTR); |
|
| 2516 |
tcg_gen_ld_ptr(r_tickptr, cpu_env, |
|
| 2517 |
offsetof(CPUState, hstick)); |
|
| 2518 |
tcg_gen_helper_0_2(helper_tick_set_limit, |
|
| 2519 |
r_tickptr, cpu_T[0]); |
|
| 2520 |
} |
|
| 2453 | 2521 |
break; |
| 2454 | 2522 |
case 6: // hver readonly |
| 2455 | 2523 |
default: |
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